KR20040029525A - Flash memory device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A flash memory device and fabricating method thereof are provided to form easily a contact hole for opening a fuse by locating a top side of the fuse and a top side of a gate electrode body on the same line. CONSTITUTION: A flash memory device includes a semiconductor substrate(100), a gate electrode body of a cell transistor, and a fuse(155). The semiconductor substrate(100) includes a cell region and a peripheral region. An isolation layer is formed on the semiconductor substrate(100). The gate electrode body is formed on the cell region of the semiconductor substrate(100). The fuse(155) is formed on the peripheral region of the semiconductor substrate(100). The gate electrode body is formed by stacking a floating gate electrode and a control gate electrode(150). A top side of the fuse(155) and a top side of the gate electrode body are located on the same line.

Description

Flash memory device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device capable of reducing a step difference between a cell region and a peripheral region where a fuse is formed during a fuse forming process and a method of manufacturing the same. .

Flash memory devices are highly integrated like DRAM (Dynamic Random Access Memory), and because they are non-volatile and have excellent data integrity, they can be replaced as main memory in a system, thereby enabling application of interfaces with DRAM. In addition, the high integration and large capacity is possible, which is rapidly attracting attention in the memory market as a device to replace the existing hard disk and floppy disk. In particular, since the standby power consumption is not only low, but also excellent in reliability, and miniaturization and light weight are possible, it has optimal characteristics as an external storage device of the electronic portable device.

Such a flash memory device includes a cell transistor for storing and erasing data by tunneling electrons, and a driving circuit unit for driving the cell transistor. Here, unlike the general MOS transistor, the cell transistor includes a tunnel oxide film, a floating gate electrode, an inter-electrode oxide film, and a control gate electrode, and is formed in the cell region of the semiconductor substrate. On the other hand, the driving circuit portion is formed in the peripheral region.

On the other hand, the flash memory device, like the DRAM, a repair process is performed, and the fuse for performing the repair is buried in the peripheral area where the driving circuit unit is formed. The fuse of the flash memory device is generally formed of the same material as the control gate electrode of the cell transistor.

1A to 1C are cross-sectional views illustrating processes of a flash memory device having a fuse formed of the same material as a control gate electrode.

As shown in FIG. 1A, a first polysilicon film and an inter-gate electrode insulating film 16 are deposited on a semiconductor substrate 10 having a defined cell region and a peripheral region. In this case, an isolation layer may be formed on the surface of the semiconductor substrate 10. Thereafter, the first polysilicon film and the inter-electrode insulating film 16 in the peripheral region portion where the fuse is to be removed are removed, leaving the first polysilicon film and the inter-gate insulating film 16 only in the cell region. Thereafter, the second polysilicon film 18 and the tungsten silicide film 20 are sequentially deposited on the semiconductor substrate resultant, and then the hard mask film 24 is deposited on the tungsten silicide film 20.

Subsequently, the hard mask film 24, the tungsten silicide film 20, the second polysilicon film 18, the inter-gate insulating film 16 and the first polysilicon film are partially patterned, and the first polysilicon is formed in the cell region. A floating gate electrode 14 made of a film and a control gate electrode 22 made of a second polysilicon film 18 and a tungsten silicide film 20 are formed, and a second polysilicon film 18 and A fuse 23 made of a tungsten silicide film 20 is formed.

Thereafter, the control gate electrode 22 is partially etched to partially expose the floating gate electrode 14. This process is called a butted process.

As shown in FIG. 1B, an etch stopper 26 is formed on the semiconductor substrate 10 on which the floating gate electrode 14, the control gate electrode 22, and the fuse 23 are formed.

Referring to FIG. 1C, the interlayer insulating layer 28 is formed on the etch stopper 26, and the interlayer insulating layer 28, the etch stopper 26, and the hard mask are exposed to expose the surfaces of the fuse and gate electrodes 14 and 22. The film 24 is etched to form the contact hole H. Thereafter, the conductive material is filled in the contact hole H to form the wiring 30.

However, due to the absence of the first polysilicon film in the peripheral region, there is a step between the cell region and the peripheral region by the thickness of the first polysilicon film. Accordingly, when forming the contact hole, since the etching depths of the interlayer insulating layers are different from each other, the fuse portion of the peripheral area having a relatively low step is not easily exposed. When the excessive etching is performed during the contact hole etching to solve this problem, the junction region may be partially lost because the contact hole and the contact hole for exposing the fuse are simultaneously formed.

As another conventional method, in order to remove the step, a method of forming the first polysilicon pattern in only the region where the fuse opening contact hole is formed is proposed. However, in the above method, the trouble of forming the first polysilicon pattern in a predetermined line width only in the predetermined area of the contact hole for opening the fuse, and the hassle of having to align with the first polysilicon pattern when forming the contact hole for opening the fuse, is present. .

Accordingly, an object of the present invention is to provide a flash memory device capable of facilitating fuse opening.

In addition, another technical problem to be achieved by the present invention is to provide a flash memory device capable of facilitating the opening of the fuse by reducing the step difference between the fuse and the gate electrode body of the flash memory device.

Another object of the present invention is to provide a method of manufacturing a flash memory device that can simplify the manufacturing process.

1A to 1C are cross-sectional views illustrating processes of a flash memory device having a fuse formed of the same material as a control gate electrode.

2A to 2D are cross-sectional views of respective processes for describing the flash memory device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 115 floating gate electrode

120: insulating film between gate electrodes 150: control gate electrode

155: fuse 160: hard mask film

170: etch stopper 190: wiring

The flash memory device of the present invention for achieving the above technical problem of the present invention, a semiconductor substrate including a cell region and a peripheral region, the device isolation film is formed, the gate electrode of the cell transistor formed in the cell region of the semiconductor substrate And a fuse formed in a peripheral region of the semiconductor substrate, wherein the gate electrode body is formed of a floating gate electrode formed of a first polysilicon film, an insulating film between gate electrodes, and a second polysilicon film and a silicide film. The control gate electrode is stacked, and the fuse is formed by stacking a first polysilicon film, an inter-gate insulating film, a second polysilicon film, and a silicide film, and each top of each of the fuse and the gate electrode body. This is located on the same line.

The gate electrode body includes a tunnel oxide film, a floating gate electrode formed of a first polysilicon film, an insulating film between gate electrodes, and a control gate electrode in which a second polysilicon film and a silicide film are stacked. The first polysilicon film, the insulating film between gate electrodes, the second polysilicon film and the silicide film are laminated.

An oxide-nitride-oxide (ONO) film may be used as the insulating film between gate electrodes, and a tungsten silicide film or a cobalt silicide film may be used as the silicide film.

The line width of the floating gate electrode is greater than the line width of the control gate electrode, and a predetermined portion of the floating gate electrode is exposed by the control gate electrode.

In addition, an interlayer insulating film and wirings formed in the interlayer insulating film are formed on the gate electrode body and the fuse part, and the wires contacting the gate electrode body and the fuse part are further formed, and the wiring contacting the gate electrode body is the control gate. It can be contacted simultaneously with the electrode and the floating gate electrode.

The semiconductor substrate further includes an isolation layer, and the fuse is formed on the isolation layer.

In addition, a method of manufacturing a flash memory device according to another aspect of the present invention is as follows. First, a device isolation film is formed, and a tunnel oxide film, a first polysilicon film, an inter-gate electrode insulating film, a second polysilicon film, and a silicide film are formed on a semiconductor substrate having a defined cell region and a peripheral region. Laminate sequentially. Thereafter, a hard mask film is formed, and the hard mask film, the silicide film, the second polysilicon film, the inter-gate insulating film and the first polysilicon film are patterned to form a floating gate electrode, a control gate electrode and a fuse. Accordingly, the total heights of the stacked floating gate electrodes and the control gate electrodes become the same as the heights of the fuses.

Here, after the forming of the floating gate electrode, the control gate electrode and the fuse, performing a butted process of etching a predetermined portion of the control gate electrode to expose a predetermined portion of the floating gate electrode, the semiconductor substrate Forming an interlayer insulating film on the resultant, simultaneously forming a contact hole for simultaneously exposing a floating gate electrode and a control gate electrode and a contact hole for opening a fuse in the interlayer insulating film, and forming a wiring in the contact hole It may further include.

In addition, in the method of manufacturing a flash memory device according to another embodiment of the present invention, a tunnel oxide film is formed on a semiconductor substrate in which a cell region and a peripheral region are defined, and a first polysilicon film is deposited on the tunnel oxide film. Next, after the device isolation film is formed on the first polysilicon film, the tunnel oxide film, and a predetermined portion in the semiconductor substrate, an inter-gate electrode insulating film is deposited on the first polysilicon film. Thereafter, a second polysilicon film and a silicide film are sequentially stacked on the inter-gate electrode insulating film, and then a hard mask film is formed on the silicide film, and the hard mask film, the silicide film, the second polysilicon film, and the gate are formed. Patterning the inter-electrode insulating film and the first polysilicon film to form a floating gate electrode, a control gate electrode, and a fuse, wherein an uppermost end of the control gate electrode is positioned on the same line as the uppermost end of the fuse.

In this case, the method may further include forming a polysilicon layer on the first polysilicon layer between forming the device isolation layer and forming the insulating film between the gate electrodes.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

2A to 2D are cross-sectional views of respective processes for describing the flash memory device according to the present invention.

First, referring to FIG. 2A, a first polysilicon film 110 is deposited on the semiconductor substrate 100. In this case, the semiconductor substrate 100 may include an isolation layer (not shown), and the first polysilicon layer 110 may be formed on the isolation layer. In addition, the semiconductor substrate 100 is limited to a cell region and a peripheral region, and the polysilicon layer doped as the floating gate electrode material is used as the first polysilicon layer 110.

For example, a tunnel oxide film (not shown) and a first polysilicon film 110 for floating gate are deposited on the semiconductor substrate 100. Thereafter, a trench is formed by etching the first polysilicon film 110, the tunnel oxide film, and a predetermined portion of the semiconductor substrate 100, and an isolation layer is embedded in the trench to form an isolation layer (not shown). Then, the first polysilicon film for the floating gate electrode may be further deposited to increase the thickness of the floating gate electrode.

As shown in FIG. 2B, the inter-gate insulating film 120, the second polysilicon film 130, the silicide film 140, and the hard mask film 160 are sequentially formed on the first polysilicon film 110. Deposit. In this case, for example, an ONO (oxide-nitride-oxide) film is used as the inter-gate insulating film 120, and the second polysilicon film 130 is a doped polysilicon film like the first polysilicon film 110. Can be. In addition, a tungsten silicide layer may be used as the silicide layer 140, and for example, a silicon nitride layer may be used as the hard mask layer 160. Thereafter, the hard mask film 160, the silicide film 140, the second polysilicon film 130, the inter-gate insulating film 120, and the first polysilicon film 110 are partially patterned to form the first polysilicon. The floating gate electrode 115 formed of the film 110, the second polysilicon film 130, and the control gate electrode 150 formed of the silicide film 140, and the first and second polysilicon films 110 and 130; A fuse 155 formed of the silicide layer 140 is formed.

In this case, the floating gate electrode 115 and the control gate electrode 150 are stacked on the cell region and the fuse 155 is formed on the peripheral region. In this case, although the fuse 155 includes the first polysilicon layer 110, substantially the second polysilicon layer 130 and the silicide layer 140 serve as the fuse 155. In this embodiment, the floating gate electrode 115 and the control gate electrode 150 are collectively referred to as a gate electrode body.

Thereafter, as shown in FIG. 2C, a butted process of etching a predetermined portion of the hard mask layer 160 and the control gate electrode 150 in the cell region may be performed to expose a predetermined portion of the floating gate electrode 115. Proceed. At this time, when the surface of the floating gate electrode 115 is exposed, the inter-gate insulating film 120 is left on the floating gate electrode 115. As a result, the cell transistor gate electrode bodies 115 and 150 of the flash memory device are completed.

As illustrated in FIG. 2D, an etch stopper 170 is formed on the entire surface of the semiconductor substrate 100 on which the gate electrode bodies 115 and 150 and the fuse 155 of the cell transistor are formed, and then etched. An interlayer insulating layer 180 is formed on the stopper 170. Next, the interlayer insulating layer 180, the etch stopper 170, and the hard mask are exposed to expose a predetermined portion of the control gate electrode 150, a predetermined portion of the floating gate electrode 115, and a predetermined portion of the fuse 155 in the cell region. The film 160 is etched to form the contact hole H. Next, the metal wiring 190 is formed in the contact hole H to contact the exposed floating gate electrode 115, the control gate electrode 150, and the fuse 155.

As the fuse 155 is formed of the first polysilicon film 110, the inter-gate insulating film 120, the second polysilicon film 130, and the silicide film 140, the gate electrode bodies 115 and 150 are formed. Have the same height as). Accordingly, during etching for forming the contact hole, the fuse 155 and the gate electrode bodies 115 and 150 may be exposed without excessive etching.

In addition, since the first polysilicon film does not need to be etched in the peripheral area where the fuse 155 is formed, the process is simplified and a separate alignment process is not required when forming the contact hole for opening the fuse.

In addition, when the conductive characteristics of the fuse 155 and the control gate electrode 150 are to be improved, the heights of the fuse 155 and the control gate electrode 150 are the same, so that the fuse 155 and After exposing the second polysilicon layer of the control gate electrode 150, a cobalt silicide layer may be selectively formed on the second polysilicon layer.

As described in detail above, according to the present invention, the fuse of the flash memory element is also formed of the first polysilicon film, the insulating film between the gate electrodes, and the second polysilicon film, similarly to the gate electrode body. Accordingly, since the heights of the gate electrode bodies of the fuse and the cell transistor are positioned on the same line, not only the contact hole for opening the fuse can be easily formed, but also the excessive etching can be eliminated, thereby improving leakage current characteristics.

In addition, since the process of removing the first polysilicon film is excluded before the second polysilicon film is formed, the process is simplified and a separate alignment is excluded when forming a contact hole for opening the fuse.

In addition, as the heights of the fuse and the gate electrode body are the same, a cobalt silicide film may be formed collectively on the surface of the fuse and the gate electrode body.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (15)

A semiconductor substrate including a cell region and a peripheral region, on which a device isolation layer is formed; A gate electrode body of a cell transistor formed in a cell region of the semiconductor substrate; And A fuse formed in a peripheral region of the semiconductor substrate, The gate electrode body is configured by stacking a floating gate electrode formed of a first polysilicon film, an insulating film between gate electrodes, and a control gate electrode formed of a second polysilicon film and a silicide film, The fuse is formed by stacking a first polysilicon film, an insulating film between gate electrodes, a second polysilicon film, and a silicide film, And a top end of each of the fuse and the gate electrode body on the same line. 2. The flash memory device of claim 1, wherein the inter-gate insulating film is an oxide-nitride-oxide (ONO) film. The flash memory device of claim 1, wherein the silicide layer is a tungsten silicide layer or a cobalt silicide layer. The flash memory device of claim 1, wherein a line width of the floating gate electrode is greater than a line width of the control gate electrode, and a portion of the floating gate electrode is exposed by the control gate electrode. The semiconductor device of claim 1, further comprising: an interlayer insulating layer covering the gate electrode body and the fuse unit; And A wiring formed in the interlayer insulating film and contacting the gate electrode body and the fuse unit, respectively; And a wire in contact with the gate electrode body is in contact with the control gate electrode and the floating gate electrode at the same time. The flash memory device of claim 1, wherein the semiconductor substrate further comprises an isolation layer, and the fuse is formed on the isolation layer. Forming a tunnel oxide film on a semiconductor substrate having a device isolation film formed thereon and defining a cell region and a peripheral region; Depositing a first polysilicon film on the tunnel oxide film; Depositing an insulating film between gate electrodes on the first polysilicon layer; Sequentially stacking a second polysilicon film and a silicide film on the inter-gate insulating film; Forming a hard mask layer on the silicide layer; And Patterning the hard mask film, the silicide film, the second polysilicon film, the inter-gate electrode insulating film, and the first polysilicon film to form a floating gate electrode, a control gate electrode, and a fuse; And a top end of the control gate electrode is positioned on the same line as the top end of the fuse. The method of claim 7, wherein after forming the floating gate electrode, the control gate electrode and the fuse, Performing a butted process of etching a predetermined portion of the control gate electrode to expose a predetermined portion of the floating gate electrode; Forming an interlayer insulating film on the semiconductor substrate product; Simultaneously forming a contact hole for simultaneously exposing a floating gate electrode and a control gate electrode and a contact hole for opening a fuse in the interlayer insulating film; And And forming a wiring in the contact hole. The method of claim 7, wherein the insulating film between gate electrodes is an oxide-nitride-oxide (ONO) film. The method of claim 7, wherein the silicide layer is a tungsten silicide layer or a cobalt silicide layer. Forming a tunnel oxide film on a semiconductor substrate having defined cell regions and peripheral regions; Depositing a first polysilicon film on the tunnel oxide film; Forming an isolation layer in a portion of the first polysilicon film, the tunnel oxide film, and the semiconductor substrate; Depositing an inter-gate insulating film on the first polysilicon film; Sequentially stacking a second polysilicon film and a silicide film on the inter-gate insulating film; Forming a hard mask layer on the silicide layer; And Patterning the hard mask film, the silicide film, the second polysilicon film, the inter-gate electrode insulating film, and the first polysilicon film to form a floating gate electrode, a control gate electrode, and a fuse; And a top end of the control gate electrode is positioned on the same line as the top end of the fuse. The method of claim 11, after the forming of the floating gate electrode, the control gate electrode and the fuse, Performing a butted process of etching a predetermined portion of the control gate electrode to expose a predetermined portion of the floating gate electrode; Forming an interlayer insulating film on the semiconductor substrate product; Simultaneously forming a contact hole for simultaneously exposing a floating gate electrode and a control gate electrode and a contact hole for opening a fuse in the interlayer insulating film; And And forming a wiring in the contact hole. 12. The method of claim 11, wherein the insulating film between gate electrodes is an oxide-nitride-oxide (ONO) film. 12. The method of claim 11, wherein the silicide layer is a tungsten silicide layer or a cobalt silicide layer. 12. The method of claim 11, further comprising: forming a polysilicon film on the first polysilicon film between the forming of the device isolation film and forming the insulating film between gate electrodes. Method of manufacturing a flash memory device.