JP2009289813A - Production method of non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production method of a nonvolatile semiconductor memory device having a laminate gate structure in which variation in gate height is reduced by rounding the top face of a floating gate electrode for avoiding the convergence of the electric field. <P>SOLUTION: This production method includes: laminating a gate insulating film 5, a polycrystalline silicon film 6 and an insulating film for processing on a silicon substrate 1; etching the resultant laminate by an RIE method to form grooves 1a, 1b; embedding a silicon oxide film in the grooves and subjecting the film to a CMP treatment; etching and dropping the silicon oxide film only in a memory cell region; coating the laminate with an underlayer resist; and etching the underlayer resist in a memory cell region to expose the polycrystalline silicon film 6, so that the top face edge part 6a of the silicon film is subjected to rounding. By this method, only the upper part of the polycrystalline silicon film 6 is exposed for rounding, so that the variation of the height is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device in which data is electrically written and erased and has a stacked gate structure.

  In general, in the manufacturing process of a MOS type semiconductor device, immediately after the gate electrode is processed, polycrystalline silicon as an electrode material is exposed on the side wall portion of the gate electrode, and the vicinity of the processed portion of the gate electrode of the gate oxide film is , Damaged during processing. For this reason, it is necessary to recover damage due to post-oxidation and to cover the gate electrode with an insulating film. In particular, in the case of a non-volatile memory having a stacked gate structure, the charge is held in the floating gate electrode, so that the film quality of the gate oxide film in the vicinity of the corner portion of the floating gate electrode greatly affects the device characteristics. For this reason, many proposals have been made for improving the gate electrode corner.

  For example, in Patent Document 1, after a SiON film is selectively formed on the sidewall portion of the floating gate electrode and the upper and sidewall portions of the control gate electrode, post-oxidation is performed by annealing in an oxidizing atmosphere. Perform the process. Then, an oxide film grows at the edge portion of the tunnel oxide film or the interelectrode insulating film. As described above, by forming the SiON film on the side wall portion of the floating gate electrode, the edge portion of the floating gate electrode is formed so that the corner portion is rounded while suppressing oxidation at that portion. ing.

  On the other hand, Patent Document 2 discloses a semiconductor device in which an ONO (oxide-nitride-oxide) film is used as an interelectrode insulating film of a stacked gate and a gate sidewall insulating film is provided. When forming the gate sidewall insulating film, oxygen radical oxidation is used to round the corners of the floating gate electrode and the control gate electrode that are in contact with the ONO film, thereby relaxing the electric field concentration at the electrode end. Furthermore, a preferred relationship between the radius of curvature of the interelectrode insulating film and the gate electrode corner is proposed.

  In addition, in a floating gate type nonvolatile memory having a tunnel insulating film and an interelectrode insulating film, in order to suppress a leakage current flowing through the interelectrode insulating film, the thickness of the insulating film is increased and the applied electric field is reduced. It is usually done. As the film thickness increases, the capacitance of the interelectrode insulating film decreases, so it is necessary to increase the surface area of the floating gate electrode. Usually, the shape of the surface of the floating gate electrode on which the interelectrode insulating film is formed is not a simple plane, but the surface is pushed up three-dimensionally to increase the capacitor area and increase the capacitance. Here, as a problem at the time of three-dimensionalization, a plurality of convex portions are always formed on the three-dimensional capacitor. When a voltage is applied to the control gate electrode, the electric field concentrates on the convex portion, and this is the main path for leakage current. Furthermore, since the current is concentrated, local breakdown resistance deterioration occurs, and electrical reliability is deteriorated.

  Usually, a polycrystalline silicon film is used for the floating gate electrode. However, since there are grain boundaries, there are irregularities and the surface morphology is not uniform. Even in the uneven portion, an increase in leakage current due to electric field concentration is observed, and deterioration of electrical reliability is observed. It is very important how to control the unevenness in these three-dimensional capacitors to suppress the leakage current.

Therefore, in order to suppress the leakage current in the interelectrode insulating film, the conventional technique removes the silicon nitride film formed on the upper surface as a mask material and exposes the upper part of the floating gate electrode. The silicon oxide film and the floating gate electrode are simultaneously etched to round the upper part of the floating gate electrode. However, since the floating gate electrode is etched, the film thickness varies. When the film thickness variation of the floating gate electrode occurs, the write voltage variation of the memory cell is deteriorated. In addition, it is difficult to control the film thickness of the floating gate electrode for obtaining a desired writing characteristic with the conventional formation processing technique.
Japanese Patent Laid-Open No. 11-154711 JP 2003-31705 A

  An object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device that can suppress variation in the thickness of a floating gate electrode film during rounding of the gate electrode.

  A first aspect of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of stacking a gate insulating film, a polycrystalline silicon film, and a silicon nitride film on an upper surface of a semiconductor substrate having a memory cell region and a peripheral circuit region. Etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film, and the semiconductor substrate to form an element isolation trench; and embedding an element isolation insulating film in the element isolation trench; Dropping the element isolation insulating film to a predetermined depth by etching to expose a side surface of the silicon nitride film; selectively dropping the element isolation insulating film in the memory cell region to a predetermined depth by etching; A step of exposing a side surface of the polycrystalline silicon, and a step of removing the processing insulating film to expose the upper surface of the polycrystalline silicon film. Depositing a first resist on the entire surface of the semiconductor substrate and patterning a second resist so as to cover a portion excluding the memory cell region; and using the second resist as a mask, Etching back the resist to expose the polycrystalline silicon film and rounding the upper surface thereof; removing the first and second resists; and separating the polycrystalline silicon film and the element And a step of laminating an interelectrode insulating film and a control gate electrode film on the upper surface of the insulating film.

  According to a second aspect of the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a gate insulating film, a polycrystalline silicon film, and a silicon nitride film are stacked on the upper surface of a semiconductor substrate having a memory cell region and a peripheral circuit region. Etching a silicon nitride film, the polycrystalline silicon film, the gate insulating film, and the semiconductor substrate to form an element isolation trench; and embedding an element isolation insulating film in the element isolation trench A step of etching the element isolation insulating film to a predetermined depth to expose a side surface of the silicon nitride film; and masking the peripheral circuit region to form the element isolation insulating film in the memory cell region Selectively etching to a predetermined depth by etching, depositing a resist on the entire surface of the semiconductor substrate, and etching the resist. Back, removing the silicon nitride film in the memory cell region while leaving the silicon nitride film in the peripheral circuit region, and rounding the exposed upper surface of the polycrystalline silicon film in the memory cell region And a step of removing the resist, and a step of forming an interelectrode insulating film and a control gate electrode film on the upper surfaces of the polycrystalline silicon film and the element isolation insulating film.

  According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, it is possible to suppress variations in the thickness of the floating gate electrode that affects the write characteristics of the memory cell.

(First embodiment)
A first embodiment in which the present invention is applied to a NAND flash memory device will be described below with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NAND flash memory device of this embodiment will be described.
FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.
The memory cell array of the NAND flash memory device has two selection gate transistors Trs and a plurality (for example, 8: n to the power of 2 (n is a positive number) connected in series between the selection gate transistors Trs. ) Memory cell transistors Trm are formed in a matrix. In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2A shows a partial layout pattern of the memory cell region, and FIG. 2B is a plan view showing, for example, a low-voltage transistor in the peripheral circuit portion. 2A, a plurality of STIs (shallow trench isolation) 2 as element isolation insulating films are formed at predetermined intervals along the Y direction in FIG. 2 on a silicon substrate 1 as a semiconductor substrate. Region 3 is formed separately in the X direction in FIG. Word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2 orthogonal to the active region 3. Further, a selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of selection gate lines SGL1. A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1.

  In FIG. 2B, the transistor TrP formed in the peripheral circuit section is provided in a portion where the STI 2 is formed on the silicon substrate 1 so as to leave the active region 4 in a rectangular shape. In the active region 4, a gate electrode PG is formed so as to cross this, and source / drain regions formed by diffusing impurities are provided on both sides thereof.

  FIGS. 3A and 3B are cross-sectional views taken along lines AA and BB in FIGS. 2A and 2B, respectively. That is, it is a schematic cross-sectional view in the middle of the manufacturing process of the memory cell transistor Trm in the memory cell region and the transistor TrP in the peripheral circuit portion shown with the gate electrode MG portion in the active region 3 as the center. And one stage of the PG formation process.

  3A and 3B, grooves 1a and 1b, which are element isolation grooves for partitioning and forming active regions 3 and 4 are formed in the surface layer of the silicon substrate 1, and a silicon oxide film is formed in the grooves. STI2 formed by embedding is formed. Gate electrodes MG and PG are formed on the upper surfaces of the active regions 3 and 4 via a tunnel insulating film 5 as a gate insulating film.

  Each gate electrode MG and PG is a conductive layer for a floating gate electrode in the gate electrode MG, and in the gate electrode PG, a polycrystalline silicon film 6 which is a lower conductive layer, an ONO (oxide nitride oxide) film or a NONON (nitride). The inter-electrode insulating film 7 made of an oxide nitride oxide film, etc., the gate electrode MG is a conductive layer for a control gate electrode, and the gate electrode PG is a structure in which a polycrystalline silicon film 8 which is an upper conductive layer is laminated. It has become.

  The polycrystalline silicon film 6 is laminated with the same width as the active regions 3 and 4, and the polycrystalline silicon film 6 of the memory cell transistor, that is, the upper surface of the floating gate electrode is rounded at both end portions 6a. And is formed in a shape that alleviates electric field concentration. The interelectrode insulating film 7 and the polycrystalline silicon film 8 are continuously formed so as to cross over the STI 2 between the adjacent polycrystalline silicon films 6. The STI 2 is formed at a height not lower than the upper surface of the silicon substrate 1 and down to a position lower than the upper surface of the polycrystalline silicon film 6, and the interelectrode insulating film 7 is laminated so as to follow the shape of the unevenness. Has been.

  On the upper surface of the polycrystalline silicon film 8, a silicon nitride film 9 is formed as a processing etching mask. The etching mask is not limited to a single layer of the silicon nitride film 9 but can be used, for example, by laminating a silicon nitride film / BSG (boron silicate glass) film / TEOS (tetraethyl orthosilicate) film.

  As shown in FIG. 3B, the interelectrode insulating film 7 of the gate electrode PG is formed with an opening 7a for conducting the polycrystalline silicon film 6 and the polycrystalline silicon film 8, and this opening. A polycrystalline silicon film 8 is embedded in 7 a and is in contact with the polycrystalline silicon film 6. Since the periphery of the active region 4 is formed so as to be surrounded by the STI 2, the gate electrode PG is formed so as to reach the STI 2 across the active region 4. Further, in the transistor TrP in the peripheral circuit portion, in addition to the case where the gate insulating film 5 having the same film thickness is formed as shown in the figure on the gate insulating film 5 of the memory cell transistor Trm, A thick gate insulating film is formed.

  The above configuration shows a state in the middle of the manufacturing process, but after that, the upper part of the polycrystalline silicon film 8 that becomes the control gate electrode is silicided, and processing is performed to reduce the wiring resistance of the word line WL. The Furthermore, an interlayer insulating film, contacts, and the like are sequentially formed to form a NAND flash memory device.

  According to the above configuration, the leak characteristics of the interelectrode insulating film 7 can be improved by rounding the both end portions 6a of the upper portion of the polycrystalline silicon film 6 to be the floating gate electrode. Furthermore, since the film thickness of the polycrystalline silicon 6 can be freely controlled without changing the gate electrode film thickness of the transistor in the peripheral circuit area, the write characteristics are not adversely affected to the transistor characteristics in the peripheral circuit area. Can be controlled.

  Next, the manufacturing process of the said structure is demonstrated with reference to FIGS. 4A to 16B are sectional views corresponding to the portions shown in FIGS. 3A and 3B, respectively.

  First, as shown in FIG. 4, a gate oxide film 5 of, eg, a 10 nm-thickness is formed on the upper surface of the silicon substrate 1 by thermal oxidation. Next, a polycrystalline silicon film 6 doped with phosphorus (P) having a thickness of, for example, about 75 nm is formed by a low pressure chemical vapor deposition (CVD) method. Subsequently, the film thickness is, for example, about 50 nm by the low pressure CVD method. A silicon nitride film 10 is stacked and formed as a mask material for trench processing.

  Next, as shown in FIG. 5, the resist film 11 is formed in a predetermined pattern by performing a lithography process. In this case, the pattern of the resist film 11 is formed in a shape for forming the band-shaped active regions 3 at predetermined intervals in the memory cell region shown in FIG. 5A, and the peripheral circuit shown in FIG. The region transistor is formed in a shape for forming a groove so as to surround the rectangular active region 4.

  Subsequently, as shown in FIG. 6, the silicon nitride film 9, the polycrystalline silicon film 6, the gate oxide film 5, and the silicon substrate 1 are sequentially etched by RIE (reactive ion etching) using the resist film 11 as a mask. Then, grooves 1a and 1b reaching a predetermined depth of the silicon substrate 1 are formed, and then the resist film 11 is removed using an ashing technique.

  Next, as shown in FIG. 7, the silicon oxide film 2a is formed with a film thickness of, for example, about 500 nm by a low pressure CVD method, an HDP (high density plasma) method, or an SOG (spin on glass) film. Thereafter, as shown in FIG. 8, the silicon oxide film 2a is ground and planarized by CMP (chemical mechanical polishing) using the silicon nitride film 10 as a stopper.

Next, as shown in FIG. 9, the silicon oxide film 2 a is etched by, for example, about 50 nm by the RIE method, and dropped to the same depth as the lower surface of the silicon nitride film 10.
Thereafter, as shown in FIG. 10, a lithography process is performed to form a resist film 12 in a predetermined pattern. In this case, the pattern of the resist film 12 is not formed in the memory cell region portion shown in FIG. 5A, but the region other than the memory cell region including the transistor portion in the peripheral circuit region shown in FIG. It is patterned so as to cover.

Subsequently, as shown in FIG. 11, the silicon oxide film 2a in the memory cell region is etched by about 50 nm using the resist film 12 as a mask (the etching depth is indicated by H in the figure), and the height of the upper surface of the silicon oxide film 2a Is dropped to a height of about the middle part of the polycrystalline silicon film 6. Thereafter, the resist film 12 is removed using an ashing cleaning technique. Thereby, STI2 is formed.
During this etching, the silicon nitride film 10 in the memory cell region is also slightly etched, so that the thickness of the silicon nitride film 10 in the memory cell region is smaller than the thickness of the silicon nitride film 10 in the peripheral circuit region.

  Next, as shown in FIG. 12, the silicon nitride film 10 is removed by phosphoric acid treatment. As a result, the upper surface of the polycrystalline silicon film 6 is exposed. Further, as shown in FIG. 12B, since the silicon oxide film 2a is not dropped for the transistors in the peripheral circuit region, the STI 2 formed by the silicon oxide film 2a is removed when the resist film 12 is removed. And the upper surface of the polycrystalline silicon film 6 have substantially the same height.

  Subsequently, as shown in FIG. 13, a lower resist film 13 which is a first resist is applied so as to cover the entire surface. This lower layer resist 13 is a resist that does not have photosensitivity. Usually, a resist having photosensitivity is applied thereon and subjected to photosensitive patterning, and the lower layer resist is patterned using the resist as a mask. In this embodiment, the lower layer resist 13 is not used for patterning.

  Thereafter, a normal resist film 14 as a second resist is applied by lithography and patterned into a predetermined shape. In this case, as shown in FIGS. 13A and 13B, the resist film 14 is removed from the memory cell region and covers a region other than the memory cell region including the transistors in the peripheral circuit region. Formed into a pattern.

  Next, as shown in FIG. 14, by using the resist 14 as a mask, the lower resist film 13 is etched by RIE until the upper portion of the polycrystalline silicon film 6 is exposed. At this time, when the upper portion of the polycrystalline silicon film 6 is exposed, the surface is also etched, and as shown in FIG. 14A, both end portions 6a on the upper surface of the polycrystalline silicon film 6 are rounded. Processed, and thereby rounded.

  Thereafter, as shown in FIG. 15, the lower resist film 13 and the resist film 14 are removed by using an ashing cleaning technique. Thus, the polycrystalline silicon film 6 in the memory cell region of FIG. 15A is formed as a floating gate electrode having a shape in which both end portions 6a on the upper surface are rounded.

  Thereafter, as shown in FIG. 16, an interelectrode insulating film 7 is formed over the entire upper surface and side surfaces of the polycrystalline silicon film 6 and the entire upper surface of the STI 2. At this time, in the memory cell region, since the polycrystalline silicon film 6 is formed so as to protrude with respect to the height of the STI 2, the interelectrode insulating film 7 is formed along the protruding portion.

  Thereafter, as shown in FIG. 4, a polycrystalline silicon film 9 is formed, and a processing silicon nitride film 9 is laminated. Then, a silicidation process on the upper part of the polycrystalline silicon film 9 is performed, and an NAND type flash memory device is formed through a process of embedding an interlayer insulating film or forming a contact, a wiring, and the like.

  According to the present embodiment, since the manufacturing process as described above is adopted, when the upper surface of the polycrystalline silicon film 6 is rounded, etching is performed with the lower resist film 13 being embedded, The rounding process can be performed when the upper surface of the polycrystalline silicon film 6 is exposed, whereby the variation in the height dimension of the polycrystalline silicon film 6, that is, the floating gate electrode due to the variation in etching can be reduced. As a result, variations in electrical characteristics due to variations in the thickness of the floating gate electrode can be suppressed.

(Second Embodiment)
FIGS. 17 to 21 show a second embodiment of the present invention. Hereinafter, parts different from the first embodiment will be described. That is, in the second embodiment, the final shape is the same as that of the first embodiment, but the steps before and after the step of rounding the upper end portions 6a of the polycrystalline silicon film 6 are different.

FIG. 17 shows a state in which the manufacturing process is performed in the same manner as in the first embodiment, and the same process as the process shown in FIG. 11 is performed.
Next, as shown in FIG. 18, a lower resist film 16 that is a first resist is applied so as to cover the entire surface.
Then, from this state, as shown in FIG. 19, the lower resist film 16 and the silicon nitride film 10 are etched by the RIE method, so that the polycrystalline silicon film 6 in the peripheral circuit region is not exposed and the memory cell region It forms so that the upper part of the crystalline silicon film 6 may be exposed.

  Subsequently, the upper surface of the polycrystalline silicon film 6 is rounded. As a result, as shown in FIG. 19A, both end portions 6a of the upper surface of the polycrystalline silicon film 6 are formed in a rounded state. At this time, as shown in FIG. 19B, for the transistors in the peripheral circuit region, the thickness of the silicon nitride film 10 is larger than that of the silicon nitride film 10 in the memory cell region due to the difference in processing in the previous process. Therefore, the upper surface of the polycrystalline silicon film 6 of the transistor in the peripheral circuit region is not exposed.

Next, as shown in FIG. 20, the lower resist film 16 is removed using an ashing technique. Subsequently, as shown in FIG. 21, the silicon nitride film 10 is removed from the transistors in the peripheral circuit region by phosphoric acid treatment. As a result, it is formed in the same state as that shown in FIG. 12 in the first embodiment. Thereafter, a NAND flash memory device is formed through the same processing steps as in the first embodiment.
Also according to the second embodiment, it is possible to obtain the same operational effects as those of the first embodiment.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the first embodiment, the lower resist film 13 is used as the first resist. However, the present invention is not limited to this, and a normal resist can also be used. In this case, it is necessary to set a process so that the second resist 14 is not patterned at the same time when it is patterned.

  In addition to the ONO film and the NONON film, the interelectrode insulating film 7 includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film containing at least one of Al, Hf, Zr, and La, Al, Hf, A metal oxynitride film containing at least one of Zr and La, a single-layer film of the above thin films, or a laminated structure containing two or more of the thin films can be used.

Instead of the polycrystalline silicon films 6 and 8, an amorphous silicon film can be used.
In addition to the NAND flash memory device, the present invention can be applied to a NOR flash memory device, and can also be applied to a nonvolatile semiconductor memory device having other stacked gate electrode structures.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device showing a first embodiment of the present invention; Schematic plan view showing a layout pattern of a part of the memory cell region and peripheral circuit transistors Sectional drawing of the part shown by the cutting lines AA and BB in FIG. Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic cross-sectional view at one stage of the manufacturing process (Part 5) Schematic sectional view at one stage of the manufacturing process (No. 6) Schematic cross-sectional view at one stage of the manufacturing process (Part 7) Schematic cross-sectional view at one stage of the manufacturing process (No. 8) Schematic cross-sectional view at one stage of the manufacturing process (No. 9) Schematic cross-sectional view at one stage of the manufacturing process (No. 10) Schematic cross-sectional view at one stage of the manufacturing process (Part 11) Schematic cross-sectional view at one stage of the manufacturing process (No. 12) Schematic cross-sectional view at one stage of the manufacturing process (No. 13) Typical sectional drawing in the stage of the manufacturing process in the 2nd Embodiment of this invention (the 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic cross-sectional view at one stage of the manufacturing process (Part 5)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is an STI, 3 is an active region, 4 is a gate insulating film, 6 is a polycrystalline silicon film, 7 is an interelectrode insulating film, 8 is a polycrystalline silicon film, 9 is a silicon nitride film, 10 is a silicon nitride film, 13 is a lower resist film (first resist), and 14 is a resist film (second resist).

Claims (4)

Forming a gate insulating film, a polycrystalline silicon film, and a silicon nitride film on the upper surface of a semiconductor substrate having a memory cell region and a peripheral circuit region; and
Etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film and the semiconductor substrate to form an element isolation trench;
Embedding an element isolation insulating film in the element isolation trench;
Dropping the element isolation insulating film to a predetermined depth by etching to expose a side surface of the silicon nitride film;
Selectively dropping the element isolation insulating film in the memory cell region to a predetermined depth by etching to expose a side surface of the polycrystalline silicon; and
Removing the processing insulating film to expose the upper surface of the polycrystalline silicon film;
Depositing a first resist on the entire surface of the semiconductor substrate and patterning a second resist so as to cover a portion excluding the memory cell region;
Etching back the first resist using the second resist as a mask to expose the polycrystalline silicon film and rounding the upper surface thereof;
Removing the first and second resists;
And a step of laminating an interelectrode insulating film and a control gate electrode film on the upper surfaces of the polycrystalline silicon film and the element isolation insulating film. Forming a gate insulating film, a polycrystalline silicon film, and a silicon nitride film on the upper surface of a semiconductor substrate having a memory cell region and a peripheral circuit region; and
Etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film and the semiconductor substrate to form an element isolation trench;
Embedding an element isolation insulating film in the element isolation trench;
Dropping the element isolation insulating film to a predetermined depth by etching to expose a side surface of the silicon nitride film;
Masking the peripheral circuit region and selectively dropping the element isolation insulating film in the memory cell region to a predetermined depth by etching;
Depositing a resist on the entire surface of the semiconductor substrate;
The resist is etched back to remove the silicon nitride film in the memory cell region while leaving the silicon nitride film in the peripheral circuit region, and to round the upper surface of the exposed polycrystalline silicon film in the memory cell region. A process of processing;
Removing the resist;
And a step of laminating an interelectrode insulating film and a control gate electrode film on the upper surfaces of the polycrystalline silicon film and the element isolation insulating film. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1,
A method of manufacturing a nonvolatile semiconductor memory device, wherein a non-photosensitive resist is used as a resist used in a process of rounding an upper surface of the polycrystalline silicon film. In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
In the step of etching the element isolation insulating film to a predetermined depth and exposing the side surface of the silicon nitride film, the depth of dropping is set to be equal to the film thickness of the silicon nitride film. A method for manufacturing a nonvolatile semiconductor memory device.

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