JP2010129740A - Non-volatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the capacitance of a capacitor per unit area of a capacitor element and reduce the area of the capacitor element in a non-volatile semiconductor memory device including an MONOS type memory cell. <P>SOLUTION: In the capacitor element, the capacitance of the capacitor per unit area of the capacitor element is increased and the area of the capacitor element is reduced by setting a polycrystalline silicon film 2 of a gate electrode of a peripheral transistor to be an intermediate electrode and setting a gate insulating film 1 and a block insulating film 10 of a memory cell transistor to be capacitor insulating films. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type memory cell including a capacitor element and a manufacturing method thereof. is there.

  When miniaturizing a nonvolatile semiconductor memory device (for example, a NAND flash memory), in a conventional floating gate type memory cell, the threshold value written in the memory cell is reduced due to interference between adjacent memory cells. The problem of fluctuations occurs. In order to solve this problem, a MONOS type memory cell with less interference between adjacent cells has been proposed.

However, when the MONOS type memory cell is employed, the same insulating film as the gate insulating film of the memory cell is used as the capacitor insulating film in the capacitor element (Patent Document 1). In this case, compared to a floating gate type memory cell in which the insulating film above and below the floating gate can be used as a capacitor insulating film, the capacitor capacity per unit area of the capacitor element decreases, so the area of the capacitor element increases, As a result, there is a problem that the chip area increases.
JP 2004-200504 A (page 26, FIG. 1)

  An object of the present invention is to increase the capacitance of a capacitor element per unit area and reduce the area of the capacitor element in view of the above problems.

  In order to achieve the above object, a nonvolatile semiconductor memory device of one embodiment of the present invention includes a semiconductor substrate, a charge trap film formed over the semiconductor substrate with a tunnel insulating film interposed therebetween, and a charge on the charge trap film. A memory cell transistor having a first gate electrode laminated via a block film; and a second gate electrode comprising a polycrystalline silicon film and a silicide film formed on the semiconductor substrate via a gate insulating film. A peripheral circuit transistor having: (a) a lower electrode made of the semiconductor substrate; (b) a first insulating film formed on the semiconductor substrate and made of the same film as the gate insulating film; An intermediate electrode formed on the insulating film and having the same film type as the polycrystalline silicon film of the second gate electrode; and (d) the same as the charge blocking film formed on the intermediate electrode A second insulating film having a film; and (e) a capacitor element formed on the second insulating film and formed by an upper electrode made of the same film as the first gate electrode. It is said.

  According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device including: a first semiconductor region including a region for forming a memory cell transistor and a region for forming a capacitor element; Forming an insulating film; forming a first conductive film over the entire region of the semiconductor substrate on the first insulating film; and charging the entire region of the semiconductor substrate over the first conductive film. After stacking the trap insulating film, a step of peeling the charge trap insulating film in a region where the capacitor element is formed; and a second insulating film over the entire region of the semiconductor substrate on the first conductive film. Forming a second conductive film on the second insulating film over the entire region of the semiconductor substrate, and forming the second conductive film and the second insulating film Processing the shape of the upper electrode of the scita element, processing the first conductive film and the first insulating film into the shape of the intermediate electrode of the capacitor element, and the semiconductor on the first conductive film The method includes a step of depositing an interlayer insulating film over the entire region on the substrate, and a step of forming a contact with the first conductive film through the interlayer insulating film.

  By using both the gate insulating film of the peripheral transistor and the block insulating film of the memory cell transistor as the capacitor insulating film, the capacitor capacity per unit area of the capacitor element can be increased and the area of the capacitor element can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view of a NAND flash memory including a MONOS type memory cell according to the first embodiment of the present invention. FIG. 1A is a memory cell transistor, FIG. 1B is a peripheral transistor, FIG. 1C shows a capacitor element. 2 is a cross-sectional view of FIG. 1, FIG. 2 (a) is a cross-sectional view taken along line AA of FIG. 1 (a), and FIG. 2 (b) is B1-B1 of FIG. 1 (b). FIG. 2C is a cross-sectional view taken along line C1-C1 in FIG. 1C.

  First, the structure of the memory cell transistor will be described with reference to FIGS. 1 (a) and 2 (a).

  As shown in FIG. 1A, a plurality of element regions 20 are provided on the main surface of a semiconductor substrate 100 in a memory cell array region where memory cell transistors are formed. These element regions 20 are formed in a strip shape in a predetermined direction, that is, in the lateral direction in FIG.

  These element regions 20 are insulated and isolated by an element isolation region 23 composed of an element isolation insulating film 24 embedded in an element isolation groove 22 (see FIG. 2B). In the element region 20, a plurality of n-type semiconductor regions 101 serving as the source / drain of the memory cell transistor are formed apart from each other. By sharing adjacent n-type semiconductor regions 101, a plurality of memory cell transistors are connected in series to form a NAND string.

  On the element region 20 and the element isolation region 23, the word lines WL of the plurality of memory cell transistors C are arranged between the separated source / drains in the direction orthogonal to the predetermined direction, that is, the upper and lower sides in FIG. The selection gate lines SL of the selection gate transistors S are arranged in parallel with the word lines WL.

  A channel of the memory cell transistor C is formed below the word line WL that intersects each element region 20, and a channel of the selection gate transistor S is formed below the selection gate line SL that intersects each element region 20. Each is formed. The n-type diffusion region 101 of the select gate transistor S is connected to the source line contact 40 and the bit line contact 41, respectively. As shown in FIG. 1A, these memory cell transistors are arranged in an array and constitute a memory cell array region.

  As shown in FIG. 2A, the word line WL of the memory cell transistor is connected to the upper surface of the semiconductor substrate 100 (element region 20) via the tunnel insulating film 21, the charge trap nitride film 3, the pad oxide film 4, and the charge block. An Al2O3 film 10 as an insulating film and a TaN film 11, a polycrystalline silicon film 12, and a NiSi film 18 are deposited as a gate electrode. That is, the memory cell transistor has a Metal (gate electrode) -Oxide (Al2O3) -Nitride (charge trap nitride film) -Oxide (tunnel insulating film) -Silicon (semiconductor substrate) structure.

  A silicon dioxide film 19 is deposited on the side walls of the word line WL of the memory cell transistor and the selection gate line SL of the selection gate transistor. In addition, the space between the word line WL of the memory cell transistor and the selection gate line SL of the selection gate transistor is planarized using the interlayer insulating film 17.

  Next, the structure of the peripheral transistor will be described with reference to FIGS. 1B and 2B.

  As shown in FIG. 1B, in the peripheral transistor region where the peripheral transistor is formed, an element region 20 is formed so as to be surrounded by an element isolation region formed on the main surface of the semiconductor substrate 100. In the element region 20, a plurality of n-type semiconductor regions 101 serving as source / drains of peripheral transistors are formed apart from each other.

  On the element region 20 and the element isolation insulating region, the gate electrode G4 of the peripheral transistor is disposed between the separated source / drain. Peripheral transistors are arranged around the memory cell array region.

  As shown in FIG. 2B, the peripheral transistor is configured by sequentially depositing the polycrystalline silicon film 2 and the NiSi film 18 on the upper surface of the semiconductor substrate 100 (element region 20) via the gate oxide film 1. ing. The polycrystalline silicon film 2 and the NiSi film 18 become the gate electrode G4 of the peripheral transistor. The element isolation region 23 is configured by embedding an element isolation insulating film 24 in an element isolation trench 22 formed in the main surface of the semiconductor substrate 100.

  A silicon dioxide film 19 is deposited on the side wall of the gate electrode G4 of the peripheral transistor. Further, the space of the gate electrode G4 of the peripheral transistor is planarized using the interlayer insulating film 17.

  Next, the structure of the capacitor element of the present embodiment will be described with reference to FIGS. 1C and 2C.

  In the capacitor element region where the capacitor element is formed, an element region 20 is formed so as to be surrounded by an element isolation region provided on the main surface of the semiconductor substrate 100. This element region 20 becomes the lower electrode G1 of the capacitor element. A polycrystalline silicon film 2 is deposited on the upper surface of the element region 20 with the gate insulating film 1 interposed therebetween. This gate insulating film 1 is the same film as the gate insulating film 1 of the peripheral transistor described above. The polycrystalline silicon film 2 is the same film type as the polycrystalline silicon film 2 that is a part of the gate electrode G4 of the peripheral transistor described above, and serves as the intermediate electrode G2 of the capacitor element.

  On the upper surface of the polycrystalline silicon film 2, the gate oxide film (SG oxide film) 9, the Al2O3 film 10, the TaN film 11, the polycrystalline silicon film 12, and the NiSi film 18 of the aforementioned select gate transistor are sequentially deposited. The Al2O3 film 10 is the same film as the charge block insulating film 10 of the memory cell transistor described above. The TaN film 11, the polycrystalline silicon film 12, and the NiSi film 18 are the same films as the gate electrode of the memory cell transistor described above, and serve as the upper electrode G3 of the capacitor element. The element isolation region 23 is configured by embedding an element isolation insulating film 24 in an element isolation trench 22 formed in the main surface of the semiconductor substrate 100.

  The capacitor element includes a first capacitor structure in which the element region 20 which is the lower electrode G1 and the polycrystalline silicon film 2 which is the intermediate electrode G2 are the first capacitor electrodes and the gate insulating film 1 is the first capacitor insulating film. The polycrystalline silicon film 2 (intermediate electrode G2), the TaN film 11, the polycrystalline silicon film 12, and the NiSi film 18 (upper electrode G3) are used as the second capacitor electrodes, and the SG oxide film 9 and the Al2O3 film 10 are used as the first capacitor electrodes. And a second capacitor structure as a capacitor insulating film. Usually, the first capacitor structure and the second capacitor structure are combined and used as one capacitor element in which the lower electrode G1 and the upper electrode G3 are nodes having the same potential and the intermediate electrode G2 is a node facing each other. A silicon dioxide film 19 is deposited on the sidewall of the capacitor element. Further, the periphery of the capacitor element is planarized using an interlayer insulating film 17.

  Next, a method for manufacturing a NAND flash memory including the MONOS memory cell according to the first embodiment of the present invention will be described with reference to process cross-sectional views from FIG. 3 to FIG. 3 (a) to 11 (a) are cross-sectional views taken along the line AA in FIG. 1 (a) and viewed in the direction of the arrows, and FIGS. 3 (b) to 11 (b) are respectively illustrated. FIG. 3B is a sectional view taken along the line BB in FIG. 1B and viewed in the direction of the arrow, and FIGS. 3C to 11C are taken along the line CC in FIG. It is process sectional drawing cut | disconnected and looked at the arrow direction.

  First, a well and a sacrificial oxide film (not shown) for channel ion implantation are formed on the semiconductor substrate 100 in each of the capacitor element region, the memory cell array region, and the peripheral transistor region. Next, after a photoresist (not shown) is formed on the sacrificial oxide film using a photolithography technique, boron (B) ions are implanted using the photoresist as a mask.

  Next, as shown in FIG. 3, after removing the photoresist and the sacrificial oxide film, the gate insulating film 1 is formed on the semiconductor substrate 100 in each of the capacitor element region, the memory cell array region, and the peripheral transistor region. Next, a polycrystalline silicon film 2 is deposited on the gate insulating film. Next, after applying a photoresist 501 on the polycrystalline silicon film 2, only the photoresist in the memory cell array region is opened by photolithography. FIG. 3 is a sectional view at the end of this step.

  Next, the polycrystalline silicon film 2 and the gate insulating film 1 in the memory cell array region are etched by RIE (Reactive Ion Etching) using the photoresist as a mask to expose the semiconductor substrate 100. Thereafter, the photoresist 501 is peeled off.

  Next, as shown in FIG. 4, a tunnel insulating film 21 is formed on the semiconductor substrate 100 in the memory cell array region and on the polycrystalline silicon film 2 in the capacitor element region and the peripheral transistor region. Next, a charge trap nitride film 3, a pad oxide film 4, and an amorphous silicon film 5 are deposited on the tunnel insulating film 21. Next, after applying a photoresist 503 on the amorphous silicon film 5, a photoresist other than the memory cell array region is opened by photolithography. FIG. 4 is a sectional view at the end of this step.

  Next, with the photoresist 503 as a mask, the amorphous silicon film 5 in the capacitor element region and the peripheral transistor region is etched by the RIE method, and the upper surface of the amorphous silicon film 5 in the capacitor element region and the peripheral transistor region is etched. The height is made equal to the height of the upper surface of the amorphous silicon film 5 in the memory cell array region. Thereafter, the photoresist 503 is peeled off.

  Next, as shown in FIG. 5, a pad nitride film 6, a mask TEOS (Tetraethoxysilane) film 7, a mask nitride film 8, and an amorphous silicon film 26 are deposited on the amorphous silicon film 5.

  Next, after applying a photoresist (not shown) on the amorphous silicon film 26, the photoresist is processed into a shape of each of the capacitor element region, the memory cell array region, and the peripheral transistor region by a photolithography technique. Then, using the photoresist as a mask, the amorphous silicon film 26, the mask nitride film 8, and the mask TEOS film 7 in the capacitor element region, the memory cell array region, and the peripheral transistor region are etched by RIE, and the photoresist is peeled off. . Subsequently, by using the amorphous silicon film 26, the mask nitride film 8, and the mask TEOS film 7 as a mask, the pad nitride film 6 and the amorphous silicon film in the capacitor element region, the memory cell array region, and the peripheral transistor region are formed by RIE. 5, the pad oxide film 4, the charge trap nitride film 3, the polycrystalline silicon film 2, the gate insulating film 1, and the semiconductor substrate 100 are etched to form an element isolation groove 22 in the element isolation region in the semiconductor substrate 100 (see FIG. 2). (Element region forming step). The mask TEOS film 7 remaining during the formation of the element isolation trench is removed in a post-processing wet process.

  Next, an element isolation insulating film 24 (see FIG. 2) such as a silicon oxide film by HDP (High Density Plasma) method is deposited in the element isolation trench 22, and CMP (Chemical Mechanical Polishing) is performed using the pad nitride film 6 as a stopper. The element isolation insulating film 24 is planarized by the method.

  In forming the pattern of the element region 20, a sidewall processing process may be used in order to create a fine pattern below the resolution limit of the photolithography technique in the memory cell array region.

  Next, in each of the capacitor element region, the memory cell array region, and the peripheral transistor region, the element isolation insulating film 24 is etched back to the same height as the amorphous silicon film 5 by the RIE method, and then padded by a wet process using phosphoric acid or the like. The amorphous silicon film 5 is peeled off from the nitride film 6 by the RIE method.

  Next, as shown in FIG. 6, after applying a photoresist 505 on the pad oxide film 4, a photoresist other than the memory cell array region is opened by photolithography.

  Using the photoresist 505 as a mask, the pad oxide film 4 and the charge trap nitride film 3 other than the memory cell array region are etched by RIE. At this time, the tunnel insulating film formed in the select gate transistor region is also removed. Thereafter, the photoresist 505 is peeled off.

  Next, as shown in FIG. 7, a gate insulating film (SG gate insulating film) 9 of the select gate transistor is formed in the select gate transistor formation region by thermal oxidation. At this time, the SG gate insulating film 9 is also formed on the polycrystalline silicon film 2 in the capacitor element region and the peripheral transistor region. Next, an Al2O3 film 10, a TaN film 11, and a polycrystalline silicon film 12 are sequentially deposited on the SG gate insulating film 9 in the capacitor element region and the peripheral transistor region and on the pad oxide film 4 in the memory cell array region. Next, after applying a photoresist 507 on the polycrystalline silicon film 12, the photoresist 507 in the peripheral transistor region is opened by photolithography.

  Next, the polycrystalline silicon film 12, the TaN film 11, the Al2O3 film 10, and the SG gate insulating film 9 in the peripheral transistor region are etched by RIE using the photoresist 507 as a mask. Thereafter, the photoresist 507 is peeled off.

  Next, as shown in FIG. 8, on the upper surface of the polycrystalline silicon film 2 in the peripheral transistor region, the upper surface of the polycrystalline silicon film 12 in the capacitor element region and the memory cell array region, a polycrystalline silicon film 13, a pad nitride film 14, and a mask. A TEOS film 15 and an amorphous silicon film 16 are sequentially deposited.

  Next, after applying a photoresist (not shown) on the amorphous silicon film 16, the photoresist is processed into the shape of the gate electrode in each of the capacitor element region, the memory cell array region, and the peripheral transistor region by photolithography. . Next, using the photoresist as a mask, the amorphous silicon film 16 and the mask TEOS film 15 are etched by RIE, and the photoresist is peeled off. Subsequently, the pad nitride film 14 is etched by the RIE method using the amorphous silicon film 16 and the mask TEOS film 15 as a mask (gate electrode forming step).

  Next, as shown in FIG. 9, a photoresist 509 is applied on the pad nitride film 14, and a photoresist 509 other than the peripheral transistor region is opened by photolithography. In the memory cell array region and the capacitor element region other than the peripheral transistor region, the polycrystalline silicon films 13 and 12, the TaN film 11, the Al2O3 film 10, and the SG oxide film 9 (in the case of the capacitor element region) are used with the pad nitride film 14 as a mask. Alternatively, the polycrystalline silicon films 13 and 12, the TaN film 11, the Al2O3 film 10, the pad oxide film 4, and the charge trap nitride film 3 (in the case of the memory cell array region) are etched. After the etching is completed, the photoresist 509 is peeled off.

  Next, as shown in FIG. 10, a photoresist 511 is applied on the semiconductor substrate 100, and the photoresist 511 in the peripheral transistor region is opened by photolithography. In the peripheral transistor region, the polycrystalline silicon film 13 and the polycrystalline silicon film 2 are etched using the pad nitride film 14 as a mask. After the etching is completed, the photoresist 511 is peeled off. FIG. 11 is a cross-sectional view after the completion of this process.

  In forming each gate electrode pattern, a sidewall processing process may be used in order to create a fine pattern below the resolution limit of the photolithography technique in the memory cell array region.

  In the capacitor element, since the polycrystalline silicon film 2 is not etched in the final processing step of the gate electrode of the memory cell transistor in FIG. It must be etched without being covered with resist 511. However, since the polycrystalline silicon film 2 is the intermediate electrode G2 of the capacitor element, in order to provide the potential by arranging the contact, it is necessary to cover the portion where the contact is disposed with a photoresist so as not to be etched. is there. Therefore, a plan view of the photoresist pattern of the capacitor element in each step of the element region forming step, the gate electrode forming step, the gate electrode final processing step of the memory cell transistor, and the gate electrode final processing step of the peripheral transistor is as shown in FIG. . A portion obtained by removing the photoresist pattern in the gate electrode forming step from the overlap of the photoresist pattern in the element region forming step and the gate electrode final processing step in the peripheral transistor is a portion where the contact is arranged in the intermediate electrode G2 of the capacitor element.

  Next, as shown in FIG. 2, a silicon dioxide film 19 serving as a sidewall for forming the source / drain diffusion region 101 is deposited on each gate electrode, and ion implantation for forming the source / drain diffusion region 101 is performed. . Next, an interlayer insulating film 17 is deposited, and the interlayer insulating film 17 is planarized by CMP using the cap nitride film 14 as a stopper. Next, the cap nitride film 14 on each gate electrode is removed by the RIE method to expose the polycrystalline silicon film 13. Next, Ni is deposited on the polycrystalline silicon film 13 and annealed at about 350 ° C. to 500 ° C. to silicide part of the polycrystalline silicon film 13 to form a NiSi film 18. FIG. 2 is a sectional view at the end of the silicidation process.

  The metal for siliciding the polycrystalline silicon film 13 may be any metal such as Co, W, Ti, etc., as long as it reacts with silicon to form a low resistance silicide.

  Next, an interlayer insulating film is deposited on the NiSi film 18 and planarized by CMP. Similar to the normal NAND flash memory production process, a NAND flash memory is produced by forming wiring layers such as bit line contacts, peripheral contacts, and bit lines.

  As described above, according to the NAND flash memory according to the first embodiment of the present invention, the capacitance per unit area is increased by the capacitor element having the intermediate electrode G2 while adopting the MONOS memory cell. The area occupied by the capacitor element can be reduced.

(Second Embodiment)
Next, a NAND flash memory including the MONOS memory cell according to the second embodiment of the present invention will be described.

  FIG. 13 is a cross-sectional view of a NAND flash memory including a MONOS type memory cell according to the second embodiment of the present invention. This embodiment has the same basic configuration as that of the first embodiment, but is characterized in that the capacitor element is formed after the semiconductor substrate 100 in the capacitor element region is etched by the RIE method.

  Since the structure of the capacitor element of the present invention is a laminated structure in which the polycrystalline silicon film 2 of the peripheral transistor is added to the memory cell transistor, the capacitor element (gate insulating film 1) is more than the gate electrode of the memory cell transistor. The height of the gate electrode of the intermediate electrode G2, the SG oxide film 9, the Al2O3 film 10, and the upper electrode G3) is high. However, if the semiconductor substrate 100 of the capacitor element portion is etched in advance by the difference in thickness between the polycrystalline silicon film 2 and the charge trap nitride film 3, the upper surface of the cap nitride film 14 is formed in the capacitor element region and the memory cell transistor region. The height is almost the same. By doing so, an effect of facilitating the planarization process of the interlayer insulating film 17 can be obtained.

  Next, a method for manufacturing a NAND flash memory having a MONOS memory cell according to the second embodiment of the present invention will be described with reference to the process cross-sectional views of FIGS.

  First, a sacrificial oxide film (not shown) is formed on the semiconductor substrate 100 in each of the capacitor element region, the memory cell array region, and the peripheral transistor region. Next, after applying a photoresist (not shown), the photoresist in the capacitor element region is opened by a photolithography technique. Using this photoresist as a mask, the semiconductor substrate 100 is etched by the RIE method. The etching amount is, for example, about 30 nm when the thickness of the polycrystalline silicon film 2 is 35 nm and the thickness of the charge trap nitride film 3 is 5 nm.

  Next, the photoresist and the sacrificial oxide film are removed, and a sacrificial oxide film is formed again on the semiconductor substrate 100 in each of the capacitor element region, the memory cell array region, and the peripheral transistor region. After a photoresist (not shown) is formed on the sacrificial oxide film using a photolithography technique, boron (B) ions are implanted using the photoresist as a mask.

  Next, after removing the photoresist and the sacrificial oxide film, the gate insulating film 1 is formed on the semiconductor substrate 100 in each of the capacitor element region, the memory cell array region, and the peripheral transistor region. Next, a polycrystalline silicon film 2 is deposited on the gate insulating film 1. Next, after applying a photoresist 501 on the polycrystalline silicon film 2, only the photoresist in the memory cell portion is opened by photolithography. FIG. 14 is a sectional view at the end of this step.

  The subsequent steps are performed in the same manner as in Example 1. After completion of the charge trap nitride film peeling step, the heights of the upper surfaces of the pad oxide film 4 in the memory cell array region and the polycrystalline silicon film 2 in the capacitor element region are substantially the same. As shown in FIG. 15, the height of the upper surface of the polycrystalline silicon film 12 is substantially the same in the capacitor element region and the memory cell array region during the step of stripping the peripheral transistor region such as Al 2 O 3.

  As described above, according to the NAND flash memory according to the second embodiment of the present invention, the semiconductor substrate 100 in the capacitor element region is etched in advance by the thickness difference between the polycrystalline silicon film 2 and the charge trap nitride film 3. As a result, the height of the upper surface of the cap nitride film 14 is approximately the same in the capacitor element region and the memory cell array region after the gate electrode is formed, and the planarization process of the interlayer insulating film 17 is facilitated.

1 is a plan view of a NAND flash memory including a MONOS type memory cell according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view of a NAND flash memory including a MONOS type memory cell according to the first embodiment of the present invention, and FIG. 2A is a cross-sectional view taken along the line AA in FIG. FIG. 2B is a cross-sectional view taken along line B1-B1 in FIG. 1B, and FIG. 2C is a cross-sectional view taken along line C1-C1 in FIG. FIG. 3A is a process cross-sectional view (part 1) illustrating the manufacture of a NAND flash memory including a MONOS memory cell according to the first embodiment of the present invention, and FIG. 3A is a cross-sectional view taken along line AA in FIG. 3B is a process sectional view taken along line BB in FIG. 1B, and FIG. 3C is a process taken along line CC in FIG. 1C. It is sectional drawing. FIG. 4A is a process cross-sectional view (part 2) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the present invention. FIG. 4A is a cross-sectional view taken along line AA in FIG. 4B is a process sectional view taken along line BB in FIG. 1B, and FIG. 4C is a process taken along line CC in FIG. 1C. It is sectional drawing. FIG. 5A is a process cross-sectional view (part 3) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 5A is a cross-sectional view taken along line AA in FIG. 5B is a process cross-sectional view along the line BB in FIG. 1B, and FIG. 5C is a process along the line CC in FIG. 1C. It is sectional drawing. FIG. 6A is a process cross-sectional view (part 4) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 6A is a cross-sectional view taken along line AA in FIG. 6B is a process sectional view taken along line BB in FIG. 1B, and FIG. 6C is a process taken along line CC in FIG. 1C. It is sectional drawing. FIG. 7A is a process cross-sectional view (part 5) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 7A is a cross-sectional view taken along line AA in FIG. 7B is a process sectional view taken along line BB in FIG. 1B, and FIG. 7C is a process taken along line CC in FIG. 1C. It is sectional drawing. FIG. 8A is a process cross-sectional view (part 6) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 8A is a cross-sectional view taken along line AA in FIG. 8B is a process sectional view taken along line BB in FIG. 1B, and FIG. 8C is a process taken along line CC in FIG. 1C. It is sectional drawing. FIG. 9A is a process cross-sectional view (part 7) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 9A is a cross-sectional view along the AA line in FIG. 9B is a process cross-sectional view taken along line BB in FIG. 1B, and FIG. 9C is a process taken along line CC in FIG. 1C. It is sectional drawing. FIG. 10A is a process cross-sectional view (part 8) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 10A is a cross-sectional view along the AA line in FIG. FIG. 10B is a process sectional view taken along the line BB in FIG. 1B, and FIG. 10C is a process taken along the line CC in FIG. 1C. It is sectional drawing. FIG. 11A is a process cross-sectional view (part 9) illustrating the manufacture of the NAND flash memory including the MONOS type memory cell according to the first embodiment of the invention, and FIG. 11A is a cross-sectional view along the AA line in FIG. 11B is a process sectional view taken along line BB in FIG. 1B, and FIG. 11C is a process taken along line CC in FIG. 1C. It is sectional drawing. 1 is a top view of a capacitor element of a NAND flash memory including a MONOS type memory cell according to a first embodiment of the present invention. 13A is a cross-sectional view of a NAND flash memory including a MONOS type memory cell according to the second embodiment of the present invention. FIG. 13A is a cross-sectional view taken along the line AA in FIG. FIG. 13B is a cross-sectional view taken along line BB in FIG. 1B, and FIG. 13C is a cross-sectional view taken along line CC in FIG. FIG. 14A is a process cross-sectional view illustrating the manufacture of a NAND flash memory including a MONOS memory cell according to the second embodiment of the present invention (part 1), and FIG. 14A is a cross-sectional view taken along line AA in FIG. 14B is a process cross-sectional view along the line BB in FIG. 1B, and FIG. 14C is a process along the line CC in FIG. 1C. It is sectional drawing. FIG. 15A is a process cross-sectional view (part 2) illustrating the manufacture of the NAND flash memory including the MONOS memory cell according to the second embodiment of the present invention, in which FIG. 15A is the AA line in FIG. FIG. 15B is a process sectional view taken along the line BB in FIG. 1B, and FIG. 15C is a process taken along the line CC in FIG. 1C. It is sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Gate insulating film 2, 12, 13 Polycrystalline silicon film 3 Charge trap nitride film 4 Pad oxide film 5, 16, 26 Amorphous silicon film 6 Pad nitride film 7, 15 Mask TEOS film 8 Mask nitride film 9 SG oxide film 10 Al 2 O 3 film 11 TaN film 14 Cap nitride film 17 Interlayer insulating film 18 NiSi film 19 Silicon dioxide film 20 Element region 21 Tunnel insulating film 22 Element isolation trench 23 Element isolation insulating region 24 Element isolation insulating film 30 Photoresist in element region forming step Pattern 31 Photoresist pattern 32 in gate electrode formation step Photoresist opening 33 in gate electrode final processing step of memory cell transistor Photoresist pattern 100 in gate electrode final processing step of peripheral transistor Semiconductor substrate (p-sub) / P- well
101 n-type diffusion regions 501, 503, 505, 507, 509, 511 Photoresist G1 Lower electrode G2 of capacitor element Intermediate electrode G3 of capacitor element Upper electrode G4 of capacitor element Gate electrode C of peripheral transistor C Memory cell transistor S Select gate transistor WL Memory cell transistor word line (gate electrode)
SL selection gate line

Claims (3)

A semiconductor substrate;
A memory cell transistor having a charge trap film formed on the semiconductor substrate via a tunnel insulating film and a first gate electrode stacked on the charge trap film via a charge block film;
A peripheral circuit transistor having a second gate electrode made of a polycrystalline silicon film and a silicide film formed on the semiconductor substrate via a gate insulating film;
(A) a lower electrode made of the semiconductor substrate; (b) a first insulating film formed on the semiconductor substrate and made of the same film as the gate insulating film; and (c) formed on the first insulating film. Further, an intermediate electrode (d) which is the same film type as the polycrystalline silicon film of the second gate electrode, and a second insulating film (d) formed on the intermediate electrode and having the same film as the charge blocking film ( e) a capacitor element formed of an upper electrode made of the same film as the first gate electrode, formed on the second insulating film;
A non-volatile semiconductor memory device comprising:   The distance between the main surface of the semiconductor substrate and the back surface of the semiconductor substrate in the region where the memory cell transistors are arranged in an array is larger than the distance between the main surface of the semiconductor substrate and the back surface of the semiconductor substrate in the region where the capacitor element is formed. The nonvolatile semiconductor memory device according to claim 1. Forming a first insulating film over the entire region of the semiconductor substrate on a semiconductor substrate having a region for forming a memory cell transistor and a region for forming a capacitor element;
After forming a first conductive film over the entire region on the semiconductor substrate on the first insulating film and stacking a charge trap insulating film over the entire region on the semiconductor substrate on the first conductive film Peeling the charge trap insulating film in a region where the capacitor element is formed;
A second insulating film is formed on the first conductive film over the entire region on the semiconductor substrate, and a second conductive film is stacked on the second insulating film over the entire region on the semiconductor substrate. Process,
Processing the second conductive film and the second insulating film into the shape of the upper electrode of the capacitor element;
Processing the first conductive film and the first insulating film into the shape of the intermediate electrode of the capacitor element;
Depositing an interlayer insulating film over the entire region of the semiconductor substrate on the first conductive film;
Forming a contact with the first conductive film through the interlayer insulating film;
A method of manufacturing a nonvolatile semiconductor memory device, comprising:

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