JP2010087159A - Nonvolatile semiconductor storage and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress interference between adjacent memory cells. <P>SOLUTION: A formation region R of a cavity section of an element separation insulation film 4 is provided in an opposed region between a floating gate electrode FGa and an active region Sa positioned directly at a lower portion of floating gate electrodes FGc, FGd, thus reducing coupling capacitance between the floating gate electrode FGa and an active region Sa that opposes while sandwiching the element separation region Sb. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device having an air gap in an element isolation insulating film and a method for manufacturing the same.

  For example, a nonvolatile semiconductor memory device such as a flash memory device employs an element isolation structure by STI (Shallow Trench Isolation) in order to form a fine element isolation structure. In this STI structure, a device isolation region is formed by forming an elongated device isolation groove on the surface of a semiconductor substrate and forming an element isolation insulating film in the device isolation trench. 2. Description of the Related Art In recent years, with the expansion of demand for increasing the capacity of semiconductor devices, transistors and cell structures have been rapidly miniaturized. Among them, the influence between adjacent cells due to the narrowing of the cell wiring pitch is one of the major issues as miniaturization progresses. Therefore, in order to suppress interference between adjacent cells, that is, to reduce the capacitance of the capacitor between adjacent cells, a structure is known in which elements are insulated by a cavity, that is, an air gap (for example, Patent Documents). 1).

In the configuration disclosed in Patent Document 1, an air gap is provided in a silicon oxide film embedded in an element isolation trench. In the case of this configuration, the position of the upper end portion of the air gap is substantially the same as the position of the upper surface of the active region of the semiconductor substrate. When the above-mentioned Patent Document 1 was filed, miniaturization has not progressed so far, and therefore the interference between adjacent cells could be sufficiently suppressed by the air gap having the above-described configuration. However, when the miniaturization further progresses, the shrinkage of the design progresses, and there is a problem that the inter-adjacent cell interference cannot be sufficiently suppressed with the air gap having the above configuration.
JP 2001-15616 A

  It is an object of the present invention to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can reduce the coupling capacitance between memory cells and suppress interference between adjacent cells.

  According to one embodiment of the present invention, an element isolation groove is formed on a surface along a predetermined first direction in the surface, and the first active region and the second active region are formed in the first direction by the element isolation groove. A plurality of semiconductor substrates partitioned in a second direction within the surface perpendicular to each other; and a charge storage layer formed on a first active region of the semiconductor substrate via a gate insulating film, the first direction And a charge storage layer formed on the second active region of the semiconductor substrate via a gate insulating film, the first charge storage layer A third charge storage layer arranged in parallel in the second direction; and a charge storage layer formed on a second active region of the semiconductor substrate via a gate insulating film, the second charge storage layer, A fourth charge storage layer arranged in parallel in the second direction, a lower portion embedded in the element isolation trench, and An element isolation insulating film comprising an upper portion protruding from the surface of the semiconductor substrate, wherein the upper surface portion has a height from the upper surface of the semiconductor substrate lower than the height of the upper surfaces of the first to fourth charge storage layers. An element isolation insulating film, and the element isolation insulating film includes the first charge storage layer opposed to the second direction and a synthesis direction of a third direction orthogonal to the surface of the semiconductor substrate, and the first charge storage layer. Between the second active region, between the second charge storage layer and the second active region, between the third charge storage layer and the first active region, and in the fourth charge storage. A cavity is formed between the lower part and the upper part between at least one of the layer and the first active region.

  One embodiment of the present invention includes a step of forming a charge storage layer over a semiconductor substrate via a gate insulating film, and a first portion along the first direction on the charge storage layer, the gate insulating film, and the semiconductor substrate. A step of forming a trench, and an element isolation insulation along the first direction so that the upper surface is located below the upper surface of the charge storage layer and above the upper surface of the gate insulating film in the first trench. Forming a film, and forming a second groove along a second direction orthogonal to the first direction for the charge storage layer and the element isolation insulating film, wherein the second groove is formed in the element isolation insulating film. A step of forming the second groove so that a bottom portion of the second groove is positioned below the upper surface of the semiconductor substrate, and a step of forming an interlayer insulating film so as to cover the second groove. It is a feature.

  According to the present invention, it is possible to suppress interference between adjacent cells.

  Hereinafter, an embodiment of the present invention applied to a NAND flash memory device will be described with reference to the drawings. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 shows an equivalent circuit of a part of a memory cell array in a NAND flash memory device. As shown in FIG. 1, NAND cell units UC are arranged in a matrix in the memory cell array Ar of the NAND flash memory device 1. In this NAND cell unit UC, two (a plurality of) select gate transistors Trs1, Trs2 and adjacent ones located between the two select gate transistors Trs1, Trs2 share a source / drain region in series. A plurality of (for example, 32) memory cell transistors Trm are connected.

  In FIG. 1, the memory cell transistors Trm arranged in the X direction (word line direction, channel width direction) are commonly connected by a word line (control gate line) WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a common select gate line SGL1. Further, the selection gate transistors Trs2 are commonly connected by a common selection gate line SGL2.

  FIG. 2 shows a partial layout pattern of the memory cell region. As shown in FIG. 2, the plurality of NAND cell units UC are formed in an active area Sa separated from each other by an element isolation region Sb having an STI (Shallow Trench Isolation) structure extending in the Y direction. A selection gate electrode SGD is formed in a planar intersection region between the selection gate line SGL1 and the active region Sa. A selection gate electrode SGS is formed in a planar intersection region between the selection gate line SGL2 and the active region Sa. A memory cell gate electrode MG is formed in a planar intersection region between the word line WL and the active region Sa. The X direction and the Y direction are directions orthogonal to each other within the surface of the semiconductor substrate 2.

  FIG. 3 schematically shows a longitudinal sectional view taken along line AA of FIG. As shown in FIG. 3, a well (not shown) is formed on the surface layer of a semiconductor substrate 2 (for example, a p-type silicon substrate), and a gate insulating film 5 is formed on the upper surface of the semiconductor substrate 2. . On the upper surface of the gate insulating film 5, two (plural) gate electrodes SGD and SGS are formed apart from each other. In FIG. 3, the gate electrode SGS is not shown. In addition, between the two select gate electrodes SGD-SGS, a gate insulating film 5 is formed on the upper surface of the semiconductor substrate 2, and a plurality (for example, 32 pieces) of the gate insulating film 5 are separated from each other on the upper surface of the gate insulating film 5. , 64) memory cell gate electrodes MG are formed. The semiconductor substrate 2 may be an n-type silicon substrate.

  The memory cell gate electrode MG is configured by stacking a floating gate electrode FG as a charge storage layer, an inter-gate insulating film 7, and a control electrode CG. The selection gate electrodes SGD and SGS are substantially the same structure and made of the same material as that of the memory cell gate electrode MG, but an opening is formed in the center of the inter-gate insulating film 7. The floating gate electrode FG and the control electrode CG are configured as a gate electrode integrally formed.

  The floating gate electrode FG is composed of, for example, the polycrystalline silicon layer 6 and functions as a charge storage layer. The inter-gate insulating film 7 is formed of, for example, an ONO film (silicon oxide film-silicon nitride film-silicon oxide film). Even if the NONO film (silicon nitride film-silicon oxide film-silicon nitride film-silicon oxide film-silicon nitride film) is formed by performing radical nitriding treatment before and / or after the ONO film is formed. It may be formed by a film containing alumina. The control electrode CG includes, for example, a polycrystalline silicon layer 8 and a silicide layer in which the upper portion of the polycrystalline silicon layer 8 is silicided with any one kind of metal such as cobalt (Co), nickel (Ni), tungsten (W), and the like. 9 is laminated. Note that the control electrode CG may be applied to a poly gate or a metal gate.

  These memory cell gate electrode MG and select gate electrodes SGD, SGS are configured by dividing the layers 6 to 9 into a plurality in the Y direction. Between the gate electrodes MG and MG and between the SGD and MG, the silicon oxide film 10 is formed along the side surfaces of the layers 6 to 9, and the silicon oxide film 11 is formed along the inner side surface of the silicon oxide film 10. Is formed. The silicon oxide film 11 is formed along the upper surface of the semiconductor substrate 2 between the gate electrodes MG-MG and between the SGD-MG.

  On the bit line contact CBb side, the silicon oxide film 10 is formed along the side surface of the selection gate electrode SGD, and the silicon oxide film 11 is formed along the outer surface of the silicon oxide film 10. This silicon oxide film 11 is formed over the bit line contact CBb formation region and its peripheral region. A spacer silicon oxide film 12 is formed along the outer surface of the silicon oxide film 11. The silicon oxide film 12 is a spacer film for forming an LDD structure for forming a contact region in the formation region of the bit line contact CBb. A silicon nitride film 13 is formed along the outer surface of the silicon oxide film 12 and the upper surface of the silicon oxide film 11. The silicon nitride film 13 functions as a barrier film for suppressing the passage of impurities. A BPSG (Boro-phosphosilicate glass) film 14 is formed inside the silicon nitride film 13.

  The cavity 15 is provided inside the silicon oxide film 11 between the gate electrodes MG-MG and between the SGD-MG. The cavity 15 is an air gap and can suppress parasitic capacitance generated between the floating gate electrodes FG-FG adjacent in the Y direction as much as possible. The cavity 15 is located below the upper surface between the floating gate electrodes FG-FG between the memory cell gate electrodes MG-MG and has a lower end. The cavity 15 is above the upper surface of the inter-gate insulating film 7 and is connected to the word line WL. It is formed so as to be located below the upper end.

  A silicon oxide film 16 is formed on the top surfaces of the gate electrodes MG and SGD, the silicon oxide films 10 to 12, the silicon nitride film 13, and the BPSG film 14. This silicon oxide film 16 is formed so as to cover the cavity 15.

  Source / drain regions 2 a are formed on the surface layer of the semiconductor substrate 2 on both sides in the Y direction of the gate electrodes MG, SGD, and SGS. These source / drain regions 2a indicate regions where impurities of the second conductivity type (N type) are introduced and diffused. A region between adjacent source / drain regions 2a-2a is configured as a channel region 2b. The active region Sa is a region including the source / drain region 2a and the channel region 2b.

  A bit line contact CBb is formed in contact with the source / drain region 2a formed in the surface layer of the semiconductor substrate 2 through the silicon oxide film 16, the BPSG film 14, the silicon nitride film 13, and the silicon oxide film 11. . Although not shown, the structure of the bit line BL is formed along the Y direction on the upper surface of the bit line contact CBb.

  FIG. 4 schematically shows a cross section taken along line BB in FIG. As shown in FIG. 4, an element isolation groove 3 is formed in the semiconductor substrate 2, and an element isolation insulating film 4 is formed inside the element isolation groove 3. The element isolation insulating film 4 includes a silicon oxide film 4a made of HTO (High Temperature Oxide) and an SOG film 4b formed inside the silicon oxide film 4a. The element isolation insulating film 4 is embedded in the element isolation groove 3 formed in the semiconductor substrate 2 and has an upper portion protruding upward from the surface of the semiconductor substrate 2.

  On the upper surface of the SOG film 4b, a polycrystalline silicon layer 8 and a silicide layer 9 are stacked as word lines WL via an inter-gate insulating film 7. A trench 18 is formed so that the side surfaces of the intergate insulating film 7, the polycrystalline silicon layer 8, and the silicide layer 9 are flush with each other. The groove 18 is also formed on the SOG film 4b.

  The silicon oxide film 11 is formed along the inner surface of the groove 18, and the cavity 15 is provided inside the silicon oxide film 11. The hollow portion 15 includes a bulging portion that swells in the Y direction at the bottom. The bulging portion is provided so as to protrude below the side edge of the adjacent word line WL. The bulge is formed between a predetermined floating gate electrode FG and the active region Sa facing the X direction and the lower synthetic direction from the position where the floating gate electrode FG is disposed. An air gap can be formed between the floating gate electrode FG and the active region Sa, and the coupling capacitance can be suppressed. The cavity 15 shown in FIG. 3 extends in the X direction and communicates with the cavity 15 shown in FIG.

  The cavity 15 is provided along the X direction in the vicinity of the center in the Y direction between the word lines WL-WL along the X direction, as shown in the planar formation region R in FIG. 2, and in the element isolation region Sb. Are partially overhanging in the region directly below the Y direction side edge of the word line WL. Therefore, the floating gate electrodes FGb facing each predetermined floating gate electrode FGa spaced apart in the Y direction, X direction, and the combined direction of the X direction and the Y direction, respectively, as shown in FIG. , FGc, and FGd, the cavity 15 has a formation region R provided between the floating gate electrodes FGa-FGb, between FGa-FGd, between FGc-FGb, and between FGc-FGd.

  Note that the formation region R shown in FIG. 2 is shown between some word lines WL-WL and between word lines WL-select gate lines SGL1, but between other word lines WL-WL, select gates. Although the illustration between the line SGL2 and the word line WL is omitted, actually, the formation region R of the cavity 15 is also provided in these regions.

  Hereinafter, the manufacturing method of the said structure is demonstrated. In addition, the characteristic part which concerns on this embodiment is mainly demonstrated, and description of the process before and behind is abbreviate | omitted. If the problem of the present invention can be solved, it may be added as long as it is a general process, may be omitted as necessary, and the process may be replaced as necessary.

  As shown in FIG. 5, after ion implantation for forming wells and channels in the semiconductor substrate 2, for example, a silicon oxide film is formed as a gate insulating film 5 on the semiconductor substrate 2 by thermal oxidation treatment. Next, as shown in FIG. 6, amorphous silicon for the floating gate electrode FG is deposited on the gate insulating film 5 by the LP-CVD method. Since amorphous silicon for the floating gate electrode FG is polycrystallized by a subsequent heat treatment, the reference numerals are given as the polycrystal silicon layer 6 in the drawings subsequent to FIG. The silicon layer 6 will be described.

  Next, as shown in FIG. 7, a mask material (not shown) is formed on the polycrystalline silicon layer 6 and patterned by a lithography technique, and as shown in FIG. An element isolation groove 3 is formed, and an element isolation insulating film 4 is embedded in the element isolation groove 3. The element isolation insulating film 4 is formed such that its upper surface is located below the upper surface of the polycrystalline silicon layer 6 and above the upper surface of the gate insulating film 5.

  Next, as shown in FIG. 8, an intergate insulating film 7 made of an ONO film (a laminated film of silicon oxide film-silicon nitride film-silicon oxide film), amorphous silicon for the control gate electrode CG, and gate processing A silicon nitride film 17 is sequentially deposited as a mask material. Since amorphous silicon for the control gate electrode CG is polycrystallized by a subsequent heat treatment, the drawings after FIG. 8 are labeled as the polycrystal silicon layer 8, and in the following description The crystal silicon layer 8 will be described. Further, the inter-gate insulating film 7 may be formed as a NONON film by performing radical nitriding before and after the ONO film is formed, or may be formed of a film containing alumina. FIG. 9 schematically shows a perspective view in this manufacturing stage.

  10 (a), 12 (a) to 14 (a), and 16 (a) to 17 (a) show one manufacturing stage of the memory cell gate electrode MG and its peripheral structure (AA in FIG. 2). 18 (a) to FIG. 24 (a) schematically show cross sections along the line AA in FIG. 2, and FIG. b), FIG. 12B to FIG. 14B, and FIG. 16B to FIG. 24B show one manufacturing stage of the element isolation insulating film 4 and its upper structure on the line BB in FIG. It is shown schematically along.

  After the structure shown in FIG. 9 is formed, a resist (not shown) is patterned on the silicon nitride film 17, and the silicon nitride film is formed by RIE as shown in FIGS. 10 (a) and 10 (b). 17, the layers 6 to 8 constituting the memory cell gate electrode MG are formed by subjecting the polycrystalline silicon layer 8, the intergate insulating film 7, the polycrystalline silicon layer 6, and the gate insulating film 5 to anisotropic etching by the RIE method sequentially. Divide into multiple pieces. At the same time, as shown in FIG. 10B, the upper portion of the element isolation insulating film 4 is also removed.

  FIG. 11 schematically shows a perspective view of the main part in this manufacturing stage. As shown in FIG. 11, the element isolation insulating film 4 is removed so that the upper surface is located below the upper surface of the semiconductor substrate 2 in the divided region where the layers 6 to 8 are divided, so that the groove 4c is formed. become.

  Next, as shown in FIGS. 12A and 12B, the side surface of the polycrystalline silicon layer 6, the side surface of the intergate insulating film 7, the side surface of the polycrystalline silicon layer 8, the side surface of the silicon nitride film 17, and A silicon oxide film 10 is formed isotropically by a predetermined film thickness (for example, 10 nm) by LP-CVD so as to cover the upper surface and the groove 4c of the element isolation insulating film 4.

Next, as shown in FIGS. 13A and 13B, the silicon oxide film 10 is processed into a spacer shape by performing an anisotropic etching process by the RIE method.
Next, as shown in FIGS. 14A and 14B, the groove 4c formed in the SOG film 4b is isotropically wet-etched. At this time, the bottom of the groove 4c of the SOG film 4b isotropically wet-etched using dilute hydrofluoric acid, thereby causing erosion of the etching process on the SOG film 4b on the lower side of the polycrystalline silicon layer 8. At the same time, the processing also proceeds on the exposed side surface of the silicon oxide film 10.

  By performing this process, the groove 18 is formed in a spherical shape at the bottom of the groove 4c. Since the SOG film 4b generally has higher etching selectivity than the silicon oxide film 10 made of HTO, the etching process speed of the SOG film 4b proceeds faster than the etching process speed of the silicon oxide film 10. It is preferable that the etching processing amount is as much as the side film thickness of the silicon oxide film 10 formed along the side surface 8.

  FIG. 15A shows a groove formation region R by a schematic plan view, and FIG. 15B shows a state after processing by a schematic perspective view. As shown in FIGS. 15 (a) and 15 (b), the SOG film 4b is isotropically etched with its outer surface covered by the silicon oxide films 10 and 4a. 18 is provided such that the groove 4c expands in the Y direction and the downward direction.

  Next, as shown in FIGS. 16A and 16B, the silicon oxide film 11 is formed in a liner shape. As shown in FIG. 16A, the silicon oxide film 11 is formed on the upper surface of the semiconductor substrate 2, on the outer surface of the silicon oxide film 10, and on the upper surface and upper surface of the silicon nitride film 17. It is formed along the inner surface of the groove 18 as shown in FIG.

  Next, as shown in FIGS. 17A and 17B, an SOG film 19 is formed on the silicon oxide film 11 by a coating technique. Next, as shown in FIGS. 18A and 18B, the SOG film 19 is planarized by CMP.

  Next, as shown in FIGS. 19A and 19B, a resist 20 is applied, and the resist 20 is patterned so as to open the formation region of the bit line contact CB. Next, as shown in FIGS. 20A and 20B, the exposed SOG film 19 is selectively removed using a diluted hydrofluoric acid treatment or the like.

  Next, as shown in FIGS. 21A and 21B, the silicon oxide film 12 is formed as a spacer along the outside of the layers 6 to 9, and then a silicon nitride film is formed on the silicon oxide film 12. 13 is formed as a barrier film, a BPSG film 14 is further deposited, and planarization is performed by CMP using the silicon nitride film 13 as a stopper.

  Next, as shown in FIGS. 22A and 22B, the silicon nitride films 13 and 17 formed on and around the upper surface of the polycrystalline silicon layer 8 are removed by RIE or the like. . Next, a metal film is formed by sputtering, and a silicide layer 9 is formed by heat treatment, and unreacted metal is peeled off.

  Next, as shown in FIGS. 23A and 23B, a resist 21 is applied and left in the formation region of the bit line contacts CBa and CBb and the periphery thereof, and between the word lines WL and WL (memory cells). The resist 21 is patterned so that the formation region of the gate electrode MG and the upper surface of the SOG film 19 between the gate electrodes MG and MG and between the SGD and MG are opened and exposed.

  Next, as shown in FIGS. 24A and 24B, the SOG film 19 filled between the gate electrodes MG and MG and between the SGD and MG is removed by treatment with dilute hydrofluoric acid or the like. Thus, the cavity 15 is formed. The cavity 15 is provided inside the silicon oxide film 11 formed along the inner surface of the groove 18 and is also provided inside the SOG film 4b as shown in FIG. Although the cavity 15 is provided between the word lines WL-WL, the lower end of the cavity 15 is provided below the side end of the inter-gate insulating film 7.

  Next, as shown in FIGS. 3 and 4, a silicon oxide film 16 is formed so as to cover the cavity 15 by using a plasma CVD method under a relatively poor coverage condition. At this time, as shown in FIG. 3, the cavity 15 is not embedded between the adjacent word lines WL-WL and between the floating gate electrodes FG-FG, and the parasitic capacitance between the adjacent floating gate electrodes FG-FG is reduced. Can be suppressed. Further, as shown in FIG. 4, the cavity 15 is not embedded between the adjacent word lines WL-WL and between the floating gate electrodes FG-FG, and is also provided inside the groove 18 of the SOG film 4b. The coupling capacitance between the floating gate electrode FG and the active region Sa sandwiching the cavity 15 can be suppressed.

  Next, the bit line contact CBb is formed so as to penetrate the silicon oxide film 16, the BPSG film 14, the silicon nitride film 13, and the silicon oxide film 12, and the structure of the bit line BL is formed thereon along the Y direction. However, details of this manufacturing method are omitted.

  According to the present embodiment, the cavity 15 of the element isolation insulating film 4 is provided in a region facing the floating gate electrode FGa and the active region Sa located immediately below the floating gate electrodes FGc and FGd. Therefore, the coupling capacitance value between the floating gate electrode FGa and the active region Sa facing each other with the element isolation insulating film 4 interposed therebetween can be reduced, and interference between adjacent memory cells can be suppressed. The same effect can be obtained by the relationship between the floating gate electrode FGb and the active region Sa located immediately below the floating gate electrodes FGc and FGd.

  In addition, since the floating gate electrode FGc and the active region Sa located immediately below the floating gate electrodes FGa and FGb are provided in a region facing each other, the floating gate electrode FGc and the element isolation insulating film 4 are sandwiched therebetween. The coupling capacitance value between the opposing active regions Sa can be reduced, and interference between adjacent memory cells can be suppressed. The same effect can be obtained by the relationship between the floating gate electrode FGd and the active region Sa located immediately below the floating gate electrodes FGa and FGb.

  The cavity 15 in the element isolation insulating film 4 is formed between the floating gate electrodes FGa and FGd facing each other, between the floating gate electrodes FGb and FGc facing each other, between the floating gate electrode FGa and the active region Sa under the floating gate electrode FGd, and the floating gate. It is formed between the active region Sa under the electrode FGd and the floating gate electrode FGa, between the floating gate electrode FGb and the active region Sa under the floating gate electrode FGc, and between the floating gate electrode FGc and the active region Sa under the floating gate electrode FGb. The floating gate electrodes FGa-FGd and FGa-FGc communicate with each other. Thereby, there exists an effect similar to the above-mentioned.

  A polycrystalline silicon layer 6 is formed on the semiconductor substrate 2 via a gate insulating film 5, and an element isolation trench 3 is formed along the Y direction on the polycrystalline silicon layer 6, the gate insulating film 5, and the semiconductor substrate 2. Then, the element isolation insulating film 4 is formed in the element isolation groove 3, and the bottom of the groove 18 in the element isolation insulating film 4 extends along the X direction with respect to the polycrystalline silicon layer 6 and the element isolation insulating film 4. Since the groove 18 is formed so as to be located below the upper surface of the silicon oxide film 2 and the silicon oxide film 16 is formed so as to cover the groove 18, the cavity 15 in the groove 18 can act as an air gap. The coupling capacitance between adjacent memory cells can be suppressed. Further, since the bottom of the groove 18 is formed by isotropically removing the SOG film 18 by wet etching, the cavity 15 in the groove 18 is opposed to the combined direction of the X direction and the downward direction. It can be made to act as an air gap between the active region Sa and the floating gate electrode FG, and the same effect can be obtained.

  After forming the groove 18, an SOG film 19 is formed as a sacrificial layer in the groove 18, and after forming the silicide layer 9, the SOG film 19 is removed to form a cavity 15 to cover the cavity 15. As described above, since the silicon oxide film 16 is formed by the plasma CVD method, the same effect as described above can be obtained.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Although applied to the flash memory device 1, it can be applied to other nonvolatile semiconductor memory devices such as a NOR type flash memory device.
Although the embodiment in which the polycrystalline silicon layer 6 is applied to the floating gate electrode FG has been described, a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure in which a silicon nitride film is applied as a charge storage layer in place of the floating gate electrode FG, A SONOS structure (Silicon-Oxide-Nitride-Oxide-Silicon) may be applied.

  Although the SOG film 19 is applied as the sacrificial layer, another material film (for example, polysilicon) that can be removed by wet etching or the like after the formation of the silicide layer 9 may be applied instead. With such a material film, the cavity 15 can be formed satisfactorily. The control electrode CG may be applied to a poly gate or a metal gate.

Electrical configuration diagram showing an embodiment of the present invention A plan view schematically showing the structure in the memory cell region Cutaway view schematically showing the main part (Part 1) Cutaway view schematically showing the main part (Part 2) Cutaway view schematically showing one manufacturing stage (Part 1) Cutaway view schematically showing one manufacturing stage (Part 2) Cutaway view schematically showing one manufacturing stage (Part 3) Cutaway view schematically showing one manufacturing stage (Part 4) Perspective view schematically showing one manufacturing stage (Part 1) Cutaway view schematically showing one manufacturing stage (Part 5) Perspective view schematically showing one manufacturing stage (No. 2) Cutaway view schematically showing one manufacturing stage (Part 6) Cutaway view schematically showing one manufacturing stage (Part 7) Sectional view schematically showing one manufacturing stage (No. 8) Plan view and perspective view schematically showing one manufacturing stage Sectional view schematically showing one manufacturing stage (No. 9) Cutaway view schematically showing one manufacturing stage (No. 10) Sectional view schematically showing one manufacturing stage (Part 11) Cutaway view schematically showing one manufacturing stage (No. 12) Cutaway view schematically showing one manufacturing stage (No. 13) Cutaway view schematically showing one manufacturing stage (No. 14) Cutaway view schematically showing one manufacturing stage (No. 15) Sectional view schematically showing one manufacturing stage (No. 16) Cutaway view schematically showing one manufacturing stage (No. 17)

Explanation of symbols

  In the drawings, 1 is a flash memory device (nonvolatile semiconductor memory device), 2 is a semiconductor substrate, 3 is an element isolation trench, 4 is an element isolation insulating film, 5 is a gate insulating film, 15 is a cavity, FG, FGa, FGb , FGc and FGd are floating gate electrodes (charge storage layers), and Sa is an active region.

Claims (5)

An element isolation groove is formed on the surface along a predetermined first direction in the surface, and the first active region and the second active region are perpendicular to the first direction by the element isolation groove. A semiconductor substrate partitioned into a plurality of two directions;
A charge storage layer formed on a first active region of the semiconductor substrate via a gate insulating film, the first and second charge storage layers arranged in parallel in the first direction;
A charge storage layer formed on a second active region of the semiconductor substrate via a gate insulating film, the third charge storage layer arranged in parallel with the first charge storage layer in a second direction;
A charge storage layer formed on a second active region of the semiconductor substrate via a gate insulating film, the fourth charge storage layer arranged in parallel with the second charge storage layer in a second direction;
An element isolation insulating film comprising a lower part embedded in the element isolation trench and an upper part protruding from the surface of the semiconductor substrate, the height from the upper surface of the semiconductor substrate being the first to fourth charge storage layers And an element isolation insulating film having an upper surface portion lower than the height of the upper surface of
In the element isolation insulating film, between the first charge storage layer and the second active region facing each other in the second direction and the third direction orthogonal to the surface of the semiconductor substrate, Between the second charge storage layer and the second active region, between the third charge storage layer and the first active region, between the fourth charge storage layer and the first active region. A non-volatile semiconductor memory device, characterized in that a cavity is formed from the lower part to the upper part between at least one of them. The element isolation insulating film has a cavity portion opposed to the synthesis direction in which the oblique direction along the surface of the semiconductor substrate obtained by synthesizing the first direction and the second direction and the third direction are synthesized. Between the charge storage layer and the second active region, between the second charge storage layer and the second active region, between the third charge storage layer and the first active region, Provided between the fourth charge storage layer and the first active region;
Between the first charge storage layer and the third charge storage layer, between the first charge storage layer and the fourth charge storage layer, and between the second charge storage layer and the fourth charge storage layer. 2. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is formed in communication with the non-volatile semiconductor memory device.   3. The nonvolatile semiconductor memory device according to claim 1, wherein each of the first to fourth charge storage layers includes a floating gate electrode. Forming a charge storage layer on a semiconductor substrate via a gate insulating film;
Forming a first trench along a first direction on the charge storage layer, the gate insulating film, and the semiconductor substrate;
Forming an element isolation insulating film along the first direction in the first trench so that the upper surface is located below the upper surface of the charge storage layer and above the upper surface of the gate insulating film;
Forming a second groove along a second direction orthogonal to the first direction for the charge storage layer and the element isolation insulating film, wherein a bottom of the second groove formed in the element isolation insulating film is Forming a second groove so as to be positioned below the upper surface of the semiconductor substrate;
And a step of forming an interlayer insulating film so as to cover the second groove.   5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the step of forming the second groove includes a step of isotropically etching the bottom of the second groove.

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