JP2013065775A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent collapse and the like of a pattern in a word line lead-out region by decreasing an aspect ratio.SOLUTION: A semiconductor device of an embodiment comprises: a semiconductor substrate; a memory cell region provided on the semiconductor substrate; a word line lead-out region provided on the semiconductor substrate; a gate electrode formed on the memory cell region via a gate insulation film by lamination of a floating gate electrode film, an interelectrode insulation film and a control gate electrode film to be word lines; and an electrode film structure formed on the word line lead-out region via the gate insulation film by lamination of the floating gate electrode film, the interelectrode insulation film and the control gate electrode film to be the word lines. In the word line lead-out region, a word line lead-out part is processed on the control gate electrode film and the floating gate electrode film includes a part where a pattern of the word line lead-out part is not processed.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the semiconductor device.

  In the NAND flash memory device, the aspect ratio at the time of processing the gate and after the processing has been increased with the miniaturization. The reason why the aspect ratio becomes high is that while the miniaturization in the horizontal direction is being promoted, the film thickness of the insulating film is not shrunk from the viewpoint of reliability, and thus the vertical shrinkage does not proceed. In addition, from the viewpoint of the write characteristics of the memory cell, it is necessary to secure a surface area that is in contact with the floating gate electrode and the control gate electrode, and the film thickness of the floating gate electrode is not shrunk. is there.

  When the aspect ratio becomes high in this way, there is a high possibility that pattern clogging or twisting occurs during and after the gate processing. For example, there is a high possibility that pattern clogging or the like occurs during drying such as a WET process after the gate is processed. In addition, after the gate is processed, a number of implantation steps are performed to determine the threshold value of the transistor, which increases the risk of pattern collapse.

  In particular, in a lead region provided with a lead portion for a word line (control gate electrode film CG), there is a high risk of pattern collapse or the like. The reason why such a risk is high is that the margin of the lithography pattern formation is deteriorated because the word line extraction region is a portion where a change occurs from a continuous pattern. In addition, the silicon substrate (active region) underlying the lead region is different from the memory cell region in that it has a solid structure without a pattern, and therefore there is a difference in the pattern structure of the silicon substrate.

JP 2007-299959 A

  Accordingly, a semiconductor device and a method for manufacturing the semiconductor device are provided that can prevent a pattern from collapsing by reducing an aspect ratio in a word line extraction region.

  The semiconductor device according to the present embodiment includes a semiconductor substrate, a memory cell region provided on the semiconductor substrate and formed with a large number of memory cells, and a word line provided on the semiconductor substrate adjacent to the memory cell region. A drawer area. A gate electrode formed on the memory cell region with a gate insulating film interposed therebetween, wherein a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film as a word line are stacked; And an electrode film structure in which a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film as a word line are stacked. Further, in the lead-out region, a word line lead-out portion is processed in the control gate electrode film, a portion in which the lead-out pattern is not processed is provided in the floating gate electrode film, and the semiconductor substrate It is characterized in that the element isolation trench pattern is not formed.

  The method for manufacturing a semiconductor device of this embodiment includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a floating gate electrode film on the gate insulating film, and a step of forming the floating gate electrode film. Forming a silicon nitride film on the floating gate electrode film; processing the silicon nitride film, the floating gate electrode film, the gate insulating film, and the semiconductor substrate to form an element isolation trench; A step of forming an element isolation insulating film by embedding and planarizing a silicon oxide film in the element isolation trench and leaving the silicon nitride film to have a set thickness, and the silicon in the word line drawing region Etching the element isolation insulating film with the nitride film masked with a resist, and removing the silicon nitride film on the floating gate electrode film in the memory cell region; Forming an interelectrode insulating film on an upper surface of the element isolation insulating film, a sidewall portion of the floating gate electrode film, an upper surface of the floating gate electrode film, and an upper surface of the silicon nitride film; and a word on the interelectrode insulating film Forming a control gate electrode film as a line; processing the control gate electrode film to expose the interelectrode insulating film; and memory with the interelectrode insulating film in the extraction region masked with a resist The method includes a step of processing the inter-electrode insulating film in the cell region, the floating gate electrode film, and the gate insulating film, and a step of removing the resist in the extraction region.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device according to a first embodiment; Schematic plan view showing a partial layout pattern of the memory cell region and the lead-out region (A) is typical sectional drawing shown along the AA line in FIG. 2, (b) is typical sectional drawing shown along the BB line in FIG. (A) is typical sectional drawing shown along the CC line in FIG. 2, (b) is typical sectional drawing shown along the DD line in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during manufacture (part 1), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2 during manufacture (part 1). ) And (c) are cross-sectional views taken along the line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 in the middle of manufacture (part 2), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. ) And (c) are cross-sectional views taken along line DD in FIG. 2A is a cross-sectional view taken along line AA in FIG. 2 in the middle of manufacture (part 3), and FIG. 2B is a cross-sectional view taken along line BB in FIG. 2 during manufacture (part 3). ), (C) is a cross-sectional view taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during production (part 4), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2 during production (part 4). ) And (c) are cross-sectional views taken along the line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 in the middle of manufacture (part 5), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. ), (C) is a cross-sectional view taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during manufacture (part 6), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2 during manufacture (part 6). ), (C) is a cross-sectional view taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during manufacture (part 7), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2 during manufacture (part 7). ), (C) is a cross-sectional view taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 in the middle of manufacture (part 8), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. ), (C) is a cross-sectional view taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during manufacture (No. 9), and FIG. 5B is a cross-sectional view taken along the line BB in FIG. 2 during manufacture (Part 9). ) And (c) are cross-sectional views taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during manufacture (part 10), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2 during manufacture (part 10). ), (C) is a cross-sectional view taken along line DD in FIG. 2A is a cross-sectional view taken along the line AA in FIG. 2 during manufacture (part 11), and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2 during manufacture (part 11). ), (C) is a cross-sectional view taken along line DD in FIG. FIG. 2 equivalent view showing the second embodiment (A) is a schematic cross-sectional view shown along the line EE in FIG. 16, and (b) is a schematic cross-sectional view shown along the line FF in FIG. FIG. 17 equivalent diagram showing the third embodiment. FIG. 9 equivalent view showing the fourth embodiment Fig. 10 equivalent 11 equivalent figure Figure equivalent to FIG. Figure 13 equivalent 14 equivalent diagram Figure 15 equivalent

  Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, substantially the same components are assigned the same reference numerals, and description thereof is omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

(First embodiment)
First, FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in the memory cell region of the NAND type flash memory device of the first embodiment. As shown in FIG. 1, the memory cell array of the NAND flash memory device includes two select gate transistors Trs1 and Trs2, and a plurality (for example, 64) connected in series between the select gate transistors Trs1 and Trs2. ) Memory cell transistors Trm are formed in a matrix. In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region and the word line lead-out region. First, in the memory cell region, a plurality of STIs (shallow trench isolation) 2 as element isolation regions extending along the Y direction in FIG. 2 are formed at predetermined intervals in the X direction in FIG. 2 on a silicon substrate 1 as a semiconductor substrate. Has been. Thus, the active regions 3 extending along the Y direction in FIG. 2 are separately formed in the X direction in FIG. The word lines WL of the memory cell transistors are formed so as to extend along a direction (X direction in FIG. 2) orthogonal to the active region 3, and a plurality of word lines WL are formed at predetermined intervals in the Y direction in FIG.

  Further, the selection gate line SGL1 of the pair of selection gate transistors is formed so as to extend along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1.

  In the word line lead-out region, the word line WL lead-out part WLa is formed so as to extend in the X direction in FIG. 2, and the right end of the upper group of word line WL lead-out parts WLa in FIG. 2 is bent into a shape as shown in FIG. 2, and a pad portion WLb is formed at the tip thereof. Note that a pad portion WLb (not shown) of a group of word lines WL below in FIG. 2 is formed in a word line lead-out region (not shown) provided on the left side in FIG. In the case of the present embodiment, the pad portion WLb of the group of word lines WL includes a word line lead region provided on the right side in FIG. 2 and a word line lead region provided on the left side in FIG. And are alternately formed. In the present embodiment, the active region 3 (silicon substrate 1) in the word line lead-out region has a solid structure without a pattern unlike the active region 3 in the line pattern in the memory cell region. .

  Next, the gate electrode structure in the memory cell region of this embodiment will be described with reference to FIG. 3A is a diagram schematically showing a cross section taken along line AA (word line direction, X direction) in FIG. 2, and FIG. 3B is a diagram showing a line BB in FIG. It is a figure which shows typically the cross section which follows a linear direction and a Y direction.

  As shown in FIGS. 3A and 3B, a plurality of element isolation grooves 4 are formed in the upper portion of the p-type silicon substrate 1 so as to be separated in the X direction. These element isolation trenches 4 isolate the active region 3 in the X direction in FIG. An element isolation insulating film 5 is formed in the element isolation trench 4 and functions as an element isolation region (STI) 2.

  The memory cell transistor includes an n-type diffusion layer 6 formed on the silicon substrate 1, a gate insulating film 7 formed on the silicon substrate 1, and a gate electrode MG provided on the gate insulating film 7. Composed. The gate electrode MG includes a floating gate electrode film FG serving as a charge storage layer, an interelectrode insulating film 9 formed on the floating gate electrode film FG, and a control gate electrode film CG formed on the interelectrode insulating film 9. Have The diffusion layer 6 is formed on both sides of the gate electrode MG of the memory cell transistor in the surface layer of the silicon substrate 1 and functions as a source / drain region of the memory cell transistor.

  The gate insulating film 7 is formed on the silicon substrate 1 (active region 3). As the gate insulating film 7, for example, a silicon oxynitride film is used. As the floating gate electrode film FG, for example, a polycrystalline silicon layer (conductive layer) 8 doped with an impurity such as phosphorus is used. The interelectrode insulating film 9 is formed along the upper surface of the element isolation insulating film 5, the upper side surface of the floating gate electrode film FG, and the upper surface of the floating gate electrode film FG. It functions as an insulating film between the electrodes. As the interelectrode insulating film 9, for example, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film (each film thickness is 3 nm to 10 nm, for example), that is, a so-called ONO film is used. Yes.

  The control gate electrode film CG includes a conductive layer 10 that functions as the word line WL of the memory cell transistor. The conductive layer 10 is made of, for example, a polycrystalline silicon layer 10a doped with an impurity such as phosphorus, and any of tungsten (W), cobalt (Co), nickel (Ni), etc. formed immediately above the polycrystalline silicon layer 10a. It has a laminated structure with a silicide layer 10b silicided with such a metal. In this embodiment, for example, nickel silicide (NiSi) is used for the silicide layer 10b. Note that the silicide layer 10b (that is, a silicide layer alone) may be used for all the conductive layers 10.

  As shown in FIG. 3B, the gate electrodes MG of the memory cell transistors are juxtaposed in the Y direction, and the gate electrodes MG are electrically separated from each other by the electrode separation grooves 14. . An inter-memory cell insulating film 11 is formed in the groove 14. As the inter-memory cell insulating film 11, for example, a silicon oxide film or a low dielectric constant insulating film using TEOS (tetraethyl orthosilicate) is used.

  A liner insulating film 12 using, for example, a silicon nitride film is formed on the upper surface of the inter-memory cell insulating film 11 and the side surfaces and upper surface of the control gate electrode film CG. On the liner insulating film 12, an interlayer insulating film 13 using, for example, a silicon oxide film is formed. The liner insulating film 12 prevents the oxidant from reaching the control gate electrode film CG when forming the interlayer insulating film 13 using a silicon oxide film, and in particular prevents the resistance of the word line WL from being increased due to oxidation of the silicide layer 10b. It has a function.

  In addition, a cross-sectional structure in the word line extraction region of the present embodiment (a structure corresponding to the gate electrode structure in the memory cell region) will be described with reference to FIG. FIG. 4A is a diagram schematically showing a cross section taken along the line C-C (word line direction, X direction) in FIG. 2, and corresponds to the cross-sectional structure in FIG. FIG. 4B is a diagram schematically showing a cross section taken along the line DD (bit line direction, Y direction) of FIG. 2, and corresponds to the cross-sectional structure of FIG.

  As shown in FIGS. 4A and 4B, on the silicon substrate 1, a gate insulating film 7, a floating gate electrode film FG (8), a silicon nitride film 15, an interelectrode insulating film 9, and a control are provided. A gate electrode film CG (10), a liner insulating film 12, and an interlayer insulating film 13 are stacked. In this case, the pattern of the element isolation trench 4 is not formed on the upper portion of the silicon substrate 1 in the word line lead-out region, and has a solid structure. The film thickness of the gate insulating film 7 in the word line extraction region is formed to be larger than the film thickness of the gate insulating film 7 in the memory cell region.

  Further, the silicon nitride film 15 is formed by leaving a part of the silicon nitride film 15 used as a hard mask without removing it when the element isolation trench 4 is processed, which will be described in detail later. In the case of this configuration (in the word line extraction region), the silicon nitride film 15 and the interelectrode insulating film 9 function as an interelectrode insulating film. That is, the interelectrode insulating film has two or more stacked insulating films 9 and 15, and the lowermost insulating film of the interelectrode insulating film is the silicon nitride film 15.

  In the word line lead-out region, as shown in FIG. 4B, in the floating gate electrode film FG (8), the silicon nitride film 15, and the interelectrode insulating film 9, an electrode isolation groove 14 is formed. Is not formed, and the processing of the groove 14 stops on the interelectrode insulating film 9.

  Next, an example of a method for manufacturing the NAND flash memory device according to the present embodiment will be described with reference to process cross-sectional views shown in FIGS. 5A to 15A schematically show the manufacturing stage of the cross-sectional structure corresponding to FIG. 3A, and FIGS. 5B to 15B are shown in FIG. FIGS. 5C to 15C schematically show the manufacturing steps of the cross-sectional structure corresponding to FIG. 4B. FIGS.

  First, as shown in FIG. 5, for example, a silicon oxynitride film is formed as a gate insulating film 7 on the surface of a p-type silicon substrate 1 by combining a known thermal oxidation method and thermal nitridation method. The film thickness of the gate insulating film 7 in the word line drawing region (see FIG. 5C) is larger than the film thickness of the gate insulating film 7 in the memory cell region (see FIGS. 5A and 5B). It is formed by a known process so as to be thick. Thereafter, for example, a doped polycrystalline silicon layer 8 to be the floating gate electrode FG is formed by low pressure chemical vapor deposition. For example, phosphorus (P) is used as the impurity of the doped polycrystalline silicon layer 8.

  Next, as shown in FIG. 5, a silicon nitride film 15 is formed on the doped polycrystalline silicon layer 8 by chemical vapor deposition, and then silicon is deposited on the silicon nitride film 15 by chemical vapor deposition. An oxide film 16 is formed. Thereafter, a photoresist (not shown) is applied onto the silicon oxide film 16, the resist is patterned by exposure and development, and the silicon oxide film 16 is etched by the RIE method using the resist as a mask. After the etching, the photoresist is removed, the silicon nitride film 15 is etched using the silicon oxide film 16 as a mask, and then the doped polycrystalline silicon layer 8 (floating gate electrode film FG), the gate insulating film 7 and the silicon substrate 1 are removed. By etching, a groove 4 for element isolation is formed (see FIG. 6A).

  Next, for example, a silicon oxide film 5 is embedded in the processed groove 4 by using a chemical vapor deposition method or a coating technique, and then the silicon nitride film 15 is used by CMP (chemical mechanical polishing) as shown in FIG. The element isolation insulating film 5 is formed by performing planarization until is exposed. In this case, as shown in FIG. 7C, a silicon nitride film 15 having a thickness of, for example, about 5 nm is left on the polycrystalline silicon layer 8 (floating gate electrode film FG) in the word line extraction region. Like that. As shown in FIGS. 7A and 7B, in the memory cell region, a silicon nitride film having a film thickness thinner than about 5 nm is formed on the polycrystalline silicon layer 8 (floating gate electrode film FG). 15 remains.

  Next, as shown in FIG. 8, a resist 17 is applied on the silicon nitride film 15 and the element isolation insulating film 5, and an opening is formed in a region corresponding to the memory cell region of the resist 17 by exposure and development. Expose. That is, the silicon nitride film 15 in the word line drawing region (and peripheral circuit region) is covered with the resist 17. Thereafter, the element isolation insulating film (silicon oxide film) 5 in the memory cell region is selectively etched by RIE using the resist 17 as a mask, so that the floating gate electrode film FG (polycrystalline silicon layer 8) is separated. The element isolation insulating film 5 is dropped. Subsequently, the silicon nitride film 15 remaining on the polycrystalline silicon layer 8 in the memory cell region is removed by WET etching using a chemical solution. Further, the resist 17 in the word line drawing region is removed. Thereby, a configuration as shown in FIG. 9 is obtained.

  Thereafter, as shown in FIG. 10, an interelectrode insulating film 9 is formed on the exposed surfaces of the polycrystalline silicon layer 8, the element isolation insulating film 5 and the silicon nitride film 15. As the interelectrode insulating film 9, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film, that is, a so-called ONO film is formed by a known process. The interelectrode insulating film 9 is a single high dielectric constant insulating film, or a film having a laminated structure of silicon oxide film / high dielectric constant insulating film / silicon oxide film, or silicon nitride film / silicon oxide film / silicon. A film having a laminated structure of nitride film / silicon oxide film / silicon nitride film may be formed.

  Next, as shown in FIG. 11, a doped polycrystalline silicon layer to be the conductive layer 10 (control gate electrode film CG) is formed on the interelectrode insulating film 9 by chemical vapor deposition. For example, phosphorus (P) is used as the impurity of the doped polycrystalline silicon layer 10. A silicon nitride film 18 and a silicon oxide film 19 are laminated on the polycrystalline silicon layer 10 by chemical vapor deposition.

  Next, gate processing is performed (electrode separation trench 14 (see FIG. 3B) is formed) to separate and form the gate electrode MG of the memory cell transistor or another gate electrode. Here, first, a photoresist (not shown) is applied to the upper surface of the silicon oxide film 19, the resist is patterned by exposure and development, and the silicon oxide film 19 is etched by the RIE method using the resist as a mask. After the etching, the resist is removed, the silicon nitride film 18 is etched using the silicon oxide film 19 as a mask, and then the polycrystalline silicon layer 10 is etched using the etched silicon nitride film 18 as a mask, as shown in FIG. Get the configuration. In this case, the etching process is stopped on the interelectrode insulating film 9.

  Thereafter, as shown in FIG. 13, a resist 20 is applied on the silicon nitride film 18, the polycrystalline silicon layer 10, and the interelectrode insulating film 9, and an area corresponding to a memory cell area in the resist 20 by exposure and development. An opening is formed in and exposed. That is, the silicon nitride film 18, the polycrystalline silicon layer 10, and the interelectrode insulating film 9 in the word line lead region (and peripheral circuit region) are covered with the resist 20. Thereafter, using the resist 20 as a mask, the interelectrode insulating film 9, the polycrystalline silicon film 8, and the gate insulating film 7 are sequentially etched to form an electrode separation groove 14, thereby forming a gate electrode MG. Thereby, a configuration as shown in FIG. 14 is obtained. Thereafter, the resist 20 in the word line drawing region is removed. Further, the silicon nitride film 18 remaining on the polycrystalline silicon layer 10 is peeled off by WET etching with a chemical solution, thereby obtaining a configuration as shown in FIG.

  Next, an impurity is doped into the surface of the silicon substrate 1 at the inner bottom portion of the groove 14 by using an ion implantation method to form a diffusion layer 6. Next, the inter-memory cell insulating film 11 is formed in the trench 14 as an inter-cell gate insulating film, and then planarized and dropped. Furthermore, after forming a nickel silicide (NiSi) layer 10b on the polycrystalline silicon layer (conductive layer) 10, a liner insulating film 12 and an interlayer insulating film 13 are formed as shown in FIGS. Further, although not shown, a NAND flash memory device chip is formed through processes such as contact formation and wiring layer formation.

  According to the present embodiment having such a configuration, in the word line extraction region, the control gate electrode film CG (conductive layer 10) is processed with the extraction portion WLa of the word line WL, and the floating gate electrode film FG (polycrystalline). The silicon layer 8) has a configuration in which the pattern of the leading portion WLa of the word line WL is not processed (that is, a solid structure), and further, a configuration in which the pattern of the element isolation trench 4 is not formed in the semiconductor substrate (that is, the silicon layer 8). Solid structure). As a result, since the aspect ratio is low in the word line lead-out region, it is possible to prevent the pattern from collapsing.

  Here, when the floating gate electrode film FG (polycrystalline silicon layer 8) has a solid structure as described above in the word line extraction region, the insulation between the control gate electrode film CG and the floating gate electrode film FG is reduced. Since only the interelectrode insulating film 9 is provided, the floating gate electrode film FG portion having a solid structure is sufficient when a high voltage (for example, about 25 V) is applied to the word line WL (control gate electrode film CG) at the time of writing. There is a possibility that the inter-electrode insulating film 9 is destroyed without being boosted, and the control gate electrode film CG and the floating gate electrode film FG become conductive. In the case where the pattern of the lead-out portion WLa of the word line WL is processed on the floating gate electrode film FG, the interelectrode insulating film 9 is destroyed and the control gate electrode film CG and the floating gate electrode film FG are made conductive. Even so, there is no problem because the word lines WL are independent of each other. However, when the floating gate electrode film FG has a solid structure as in the present embodiment, it interferes with other word lines WL.

  Therefore, in this embodiment, the silicon nitride film 15 for the hard mask is left below the interelectrode insulating film 9 having a normal film structure, and the silicon nitride film 15 and the interelectrode insulating film 9 function as an interelectrode insulating film. To do. That is, the interelectrode insulating film has a structure having two or more laminated insulating films, and the lowermost insulating film after the interelectrode insulating film is the silicon nitride film 15. According to the present embodiment, when a high voltage is applied to the word line WL at the time of writing or the like, it is possible to prevent the inter-electrode insulating film 9 from being broken and the control gate electrode film CG and the floating gate electrode film FG from becoming conductive. .

(Second Embodiment)
16 and 17 show a second embodiment. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. FIG. 17A is a diagram schematically showing a cross section taken along line EE (bit line direction, Y direction) in FIG. 16, and FIG. 17B is a cross-sectional view taken along line FF in FIG. It is a figure which shows typically the cross section which follows a linear direction and a Y direction.

  In the first embodiment, the floating gate electrode film FG is left in a solid structure in the word line extraction region, but in the second embodiment, the hatched region P in FIG. 16 of the floating gate electrode film FG is shown. In the region indicated by, the floating gate electrode film FG (polycrystalline silicon layer 8) is processed and further processed to about half the film thickness of the gate insulating film 7 to form the trench 21. The width of the groove 21 in the left-right direction (word line direction) in FIG. 16 is about 100 to 200 nm, and the vertical direction (bit line direction) in FIG. 16 of the electrode isolation groove 14 in the memory cell region. It is wider than the width dimension of about 20 nm.

  As a manufacturing method for forming the groove 21, in the step shown in FIG. 8 of the first embodiment, after the resist 17 is applied, a portion corresponding to the memory cell region of the resist 17 is opened by exposure and development. In addition, a portion corresponding to the area indicated by the hatched area P in FIG. 16 is also opened. As a result, when the element isolation trench 4 is formed (processed), a portion of the silicon nitride film 15 left on the polycrystalline silicon layer 8 corresponding to the region indicated by the hatched region P in FIG. 16 is opened. Let In the step shown in FIG. 13 of the first embodiment, after applying the resist 20, when a portion corresponding to the memory cell region of the resist 20 is opened by exposure and development, the hatched region P in FIG. A portion corresponding to the region indicated by is also opened. What is necessary is just to comprise the manufacturing process other than this similarly to the manufacturing method of 1st Embodiment.

  The configuration of the second embodiment other than that described above is the same as that of the first embodiment. Therefore, in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, according to the second embodiment, since the trench 21 reaching the gate insulating film 7 is formed in the area indicated by the hatched area P in FIG. 16 in the floating gate electrode film FG, the floating gate electrode film FG is uneven. Therefore, the strength of the word line lead-out region as a structure can be increased.

(Third embodiment)
FIG. 18 shows a third embodiment. In addition, the same code | symbol is attached | subjected to the same structure as 2nd Embodiment. In the second embodiment, when the element isolation trench 4 is formed (processed), the silicon nitride film 15 left on the polycrystalline silicon layer 8 corresponds to the region indicated by the hatched region P in FIG. In the third embodiment, the hatched region P in FIG. 16 of the silicon nitride film 15 left on the polycrystalline silicon layer 8 when the element isolation trench 4 is formed is formed in the third embodiment. The portion corresponding to the region indicated by is not opened. That is, in the step shown in FIG. 8 of the first embodiment, after the resist 17 is applied, a portion corresponding to the memory cell region of the resist 17 is opened by exposure and development, and the region indicated by the hatched region P in FIG. The portion corresponding to is not opened.

  The configuration of the third embodiment other than that described above is the same as that of the second embodiment. Therefore, in the third embodiment, substantially the same operational effects as in the second embodiment can be obtained. In particular, according to the third embodiment, the trench 21 formed in the region indicated by the hatched region P in FIG. 16 in the floating gate electrode film FG is formed in the floating gate electrode film FG (polycrystalline silicon layer 8). It is possible to form the groove 21 that reaches the lower half portion. Also in the case of the second embodiment, since the floating gate electrode film FG has an uneven structure, the strength of the word line extraction region as a structure can be increased.

(Fourth embodiment)
19 to 25 show a fourth embodiment. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the first embodiment, as shown in FIG. 9, the silicon nitride film 15 is left on the polycrystalline silicon layer 8 in the word line extraction region, and the silicon nitride film is formed on the polycrystalline silicon layer 8 in the memory cell region. In the fourth embodiment, as shown in FIG. 19, the silicon nitride film 15 is also left on the polycrystalline silicon layer 8 in the memory cell region. In this case, the film thickness of the silicon nitride film 15 left on the polycrystalline silicon layer 8 in the memory cell region is the film thickness of the recon nitride film 15 left on the polycrystalline silicon layer 8 in the word line drawing region. It is thinner than the thickness (about 5 nm).

  Specifically, after each step shown in FIGS. 5 to 7 of the first embodiment is performed, the resist 17 is not applied (without performing the step shown in FIG. 8 of the first embodiment). As shown in FIG. 19, element isolation between the floating gate electrode film FG (polycrystalline silicon layer 8) is performed by selectively etching the element isolation insulating film (silicon oxide film) 5 in the memory cell region using the RIE method. Insulating film 5 is dropped. In this case, etching is performed under conditions that allow an etching selectivity to the silicon oxide film 5 so that the silicon nitride film 15 remains.

  Thereafter, as shown in FIG. 20, the inter-electrode insulation is formed on the side wall portion of the polycrystalline silicon layer 8, the upper surface of the silicon nitride film 15, and the upper surface of the element isolation insulating film 5 without peeling off the silicon nitride film 15. A film 9 is formed. As the interelectrode insulating film 9, a so-called ONO film is formed by a known process.

  Next, as shown in FIG. 21, a doped polycrystalline silicon layer to be the conductive layer 10 (control gate electrode film CG) is formed on the interelectrode insulating film 9 by chemical vapor deposition. For example, phosphorus (P) is used as the impurity of the doped polycrystalline silicon layer 10. A silicon nitride film 18 and a silicon oxide film 19 are laminated on the polycrystalline silicon layer 10 by chemical vapor deposition.

  Next, gate processing is performed (electrode separation trench 14 (see FIG. 3B) is formed) to separate and form the gate electrode MG of the memory cell transistor or another gate electrode. Here, first, a photoresist (not shown) is applied to the upper surface of the silicon oxide film 19, the resist is patterned by exposure and development, and the silicon oxide film 19 is etched by the RIE method using the resist as a mask. After the etching, the resist is removed, the silicon nitride film 18 is etched using the silicon oxide film 19 as a mask, and then the polycrystalline silicon layer 10 is etched using the etched silicon nitride film 18 as a mask, as shown in FIG. Get the configuration. In this case, the etching process is stopped on the interelectrode insulating film 9.

  Thereafter, a resist 20 is applied on the silicon nitride film 18, the polycrystalline silicon layer 10, and the interelectrode insulating film 9, and an opening is formed in a region corresponding to the memory cell region of the resist 20 by exposure and development. Expose. That is, the silicon nitride film 18, the polycrystalline silicon layer 10, and the interelectrode insulating film 9 in the word line lead region (and peripheral circuit region) are covered with the resist 20. Thereafter, using the resist 20 as a mask, the interelectrode insulating film 9, the silicon nitride film 15, the polycrystalline silicon layer 8, and the gate insulating film 7 are sequentially etched to form an electrode separation groove 14, thereby forming a gate electrode MG. . Thereby, a configuration as shown in FIG. 24 is obtained. Thereafter, the resist 20 is removed, and the silicon nitride film 18 is peeled off to obtain a configuration as shown in FIG.

  The configuration of the fourth embodiment other than that described above is the same as that of the first embodiment. Therefore, also in the fourth embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, according to the fourth embodiment, in the memory cell region, the silicon nitride film 15 is left below the interelectrode insulating film 9, and the interelectrode insulating film is configured using the silicon nitride film 15 and the interelectrode insulating film 9. Therefore, the leakage current of the interelectrode insulating film, which becomes a problem with miniaturization, can be suppressed. Since the floating gate electrode film FG in the memory cell region has a sharp shape with miniaturization, the leakage current of the interelectrode insulating film due to electric field concentration increases, so that the write saturation characteristic of the memory cell deteriorates, There may be a case where a threshold drop occurs from a memory cell once written.

  On the other hand, according to the fourth embodiment, since the silicon nitride film 15 is formed on the floating gate electrode film FG of the memory cell, the effective oxide film thickness of the interelectrode insulating film is increased, and the electron And the leakage current can be suppressed, and the write saturation characteristic can be improved. Further, in the fourth embodiment, compared to the first embodiment, the application of the resist 17 and the exposure / development treatment are not required, and therefore the number of steps can be reduced.

(Other embodiments)
In addition to the plurality of embodiments described above, the following configurations may be adopted.
In each of the above-described embodiments, the silicon substrate 1 in the word line extraction region has a solid structure. Alternatively, a line-and-space pattern groove may be formed in the silicon substrate 1 in the word line extraction region. good.

  In the first embodiment, after the element isolation insulating film (silicon oxide film) 5 of the STI 2 in the memory cell region is etched back, the peeling process of the silicon nitride film 15 on the polycrystalline silicon layer 8 is performed. Thus, the etch back of the element isolation insulating film (silicon oxide film) 5 and the peeling process of the silicon nitride film 15 may be performed simultaneously.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  In the drawings, 1 is a silicon substrate, 2 is an STI, 3 is an active region, 4 is an element isolation trench, 5 is an element isolation insulating film, 7 is a gate insulating film, 8 is a polycrystalline silicon layer, 9 is an interelectrode insulating film, 10 is a conductive layer, 14 is a groove, 15 is a silicon nitride film, 17 is a resist, 20 is a resist, and 21 is a groove.

Claims (6)

A semiconductor substrate;
A memory cell region provided on the semiconductor substrate and formed with a large number of memory cells;
A word line extraction region provided adjacent to the memory cell region on the semiconductor substrate;
A gate electrode formed on the memory cell region through a gate insulating film, and a stacked gate electrode film, a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film as a word line;
An electrode film structure formed on the lead-out region via a gate insulating film, in which a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film as a word line are stacked;
In the lead-out region, a word line lead-out portion is processed in the control gate electrode film, a portion in which the pattern of the lead-out portion is not processed is provided in the floating gate electrode film, and element isolation is provided in the semiconductor substrate. No groove pattern is formed, and
In the lead region, the interelectrode insulating film has a laminated insulating film of two or more layers, and the lowermost insulating film after the interelectrode insulating film is a silicon nitride film, and
In the memory cell region, the interelectrode insulating film has a laminated insulating film of two or more layers, and further, the lowermost insulating film among the interelectrode insulating films on the upper surface of the floating gate electrode film Is a silicon nitride film. A semiconductor substrate;
A memory cell region provided on the semiconductor substrate and formed with a large number of memory cells;
A word line extraction region provided adjacent to the memory cell region on the semiconductor substrate;
A gate electrode formed on the memory cell region through a gate insulating film, and a stacked gate electrode film, a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film as a word line;
An electrode film structure formed on the lead-out region via a gate insulating film, in which a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film as a word line are stacked;
In the lead-out region, a word line lead-out portion is processed in the control gate electrode film, a portion in which the pattern of the lead-out portion is not processed is provided in the floating gate electrode film, and element isolation is provided in the semiconductor substrate. A semiconductor device, wherein a groove pattern is not formed.   In the lead-out region, the interelectrode insulating film includes two or more stacked insulating films, and the lowermost insulating film after the interelectrode insulating film is a silicon nitride film The semiconductor device according to claim 2.   In the memory cell region, the interelectrode insulating film has a laminated insulating film of two or more layers, and further, the lowermost insulating film among the interelectrode insulating films on the upper surface of the floating gate electrode film 4. The semiconductor device according to claim 2, wherein is a silicon nitride film. Forming a gate insulating film on the semiconductor substrate;
Forming a floating gate electrode film on the gate insulating film;
Forming the floating gate electrode film;
Forming a silicon nitride film on the floating gate electrode film;
Processing the silicon nitride film, the floating gate electrode film, the gate insulating film, and the semiconductor substrate to form an element isolation trench;
A step of embedding a silicon oxide film in the element isolation trench and planarizing to leave a film thickness of the silicon nitride film to be a set film thickness, and forming an element isolation insulating film;
With the silicon nitride film in the word line extraction region masked with a resist, the element isolation insulating film in the memory cell region is etched back, and the silicon nitride film on the floating gate electrode film in the memory cell region is removed. Process,
Forming an interelectrode insulating film on the upper surface of the element isolation insulating film, the side wall of the floating gate electrode film, the upper surface of the floating gate electrode film, and the upper surface of the silicon nitride film;
Forming a control gate electrode film as a word line on the interelectrode insulating film;
Processing the control gate electrode film to expose the interelectrode insulating film;
Processing the interelectrode insulating film in the memory cell region, the floating gate electrode film, and the gate insulating film in a state where the interelectrode insulating film in the extraction region is masked with a resist;
And a step of removing the resist in the lead-out region.   In the step of etching back the element isolation insulating film in the memory cell region, after etching back the element isolation insulating film without masking the silicon nitride film in the extraction region with a resist, the memory cell region and the extraction 6. The method of manufacturing a semiconductor device according to claim 5, wherein the silicon nitride film on the floating gate electrode film in a region is left.

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