JP2001068643A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device which can increase the access speed to the memory cell of the memory cell section of a DRAM by reducing the resistance of the bit line or capacity connection of the memory cell section by siliciding the diffusion layer of a logic circuit section in a chip in which the memory cell section and the logic section of a peripheral circuit integrally coexist. SOLUTION: After the MOS Tr of a memory cell section and the MOS Tr of a logic circuit section and interlayer SiO2 films 110 which cover the MOS Trs are formed on a semiconductor substrate 101, connecting holes which are connected to the diffusion layers 108 of the MOS Trs of the memory cell section are opened and poly-Si pads 112 are formed by filling up the connecting holes with poly-Si. In addition, after the S- and D-diffusion layers 115 and 116 of a P-type MOS Tr and an N-type MOS Tr are formed by introducing P- and N-type impurities to the logic circuit section, a metal silicate 117 is formed on the layers 115 and 116 by coating the layers 115 and 116 with a metal and heat-treating the metal. Moreover, bit lines 121 are formed on the pad Si and wiring 122 connected to the silicate 117 on the diffusion layers 115 and 116 and a capacity 131 connected to the pad Si are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM logic mixed chip in which a memory cell portion of a DRAM and a logic circuit portion of a peripheral circuit are mounted on the same semiconductor substrate, and in particular, to a high speed operation in the logic circuit portion. The present invention also relates to a method of manufacturing a semiconductor integrated circuit device which achieves high integration and improves an access speed in a memory cell section.

[0002]

2. Description of the Related Art In a DRAM logic mixed chip having a DRAM memory cell portion and a logic circuit portion as a peripheral circuit, a diffusion layer of the logic circuit portion is provided in order to achieve high speed and high integration in the logic circuit portion. , Especially the sauce,
A technique of forming the drain diffusion layer into a metal silicide is employed. In this way, the resistance of the source / drain diffusion layer is reduced, and the number of contacts connected to the source / drain diffusion layer can be reduced, so that the wiring can be formed densely and high integration can be achieved. become. As such a manufacturing method, Japanese Patent Application Laid-Open No. 10-256
No. 511, IEDM 96P. 59
The technique described in No. 7 is available. FIG. 6 shows a manufacturing method based on these prior arts. First, as shown in FIG. 6A, an element isolation is formed on a silicon substrate 101 by a trench isolation 102, and then a gate oxide film 103 is formed. , Polysilicon is deposited and patterned to form a gate electrode 1
04 is formed. Subsequently, phosphorus ions are implanted into the entire surface using the gate electrode 104 as a mask to form an N ^- diffusion layer 108. Thereafter, a silicon oxide film is deposited, etched back, and a side wall 1 of the silicon oxide film is formed on the side surface of the gate electrode.
14 is formed. Furthermore, in the logic circuit portion, As and BF2 are selectively ion-implanted using the side walls 114 to selectively form N ⁺ diffusion layers 115 and P ⁺ diffusion layers 116 including source / drain diffusion layers. I do.

Subsequently, as shown in FIG. 6B, a silicon nitride film 109 is thinly deposited on the entire surface, and then the silicon nitride film 109 in the logic circuit portion is removed, and diffusion layers 115 and 116 are formed.
Is exposed. Subsequently, by performing heat treatment after sputtering titanium, the diffusion layers 115 and 1 in the logic circuit portion are formed.
A titanium silicide layer 117 is formed over the gate electrode 16 and the gate electrode 104. Thereafter, the titanium that has not been silicided is removed by immersing it in an aqueous ammonia solution. Thus, the titanium silicide 1 is formed only on the diffusion layers 115 and 116 and the gate electrode 104 in the logic circuit portion.
17 are formed. Subsequently, as shown in FIG. 6C, an interlayer oxide film 110 is deposited on the entire surface, and a contact hole 111 is opened in a region where a capacity contact and a bit line contact are formed in the memory cell portion. Thereafter, polysilicon is deposited on the entire surface and etched back to form pad polysilicon 112. Thereafter, as shown in FIG. 6D, an interlayer oxide film 118 is formed, a bit line 121 is formed of tungsten through contacts 120 and 125 opened in the interlayer oxide film 118, and the capacitor lower electrode 12 is formed.
8, a capacitor insulating film 129 and a capacitor upper electrode 130
A RAM capacitor 131 is formed, and a wiring 122 is formed via a contact 119. Further, the interlayer oxide film 12
3, 126 and 132 are formed, and an aluminum metal wiring 134 is formed through the contact 133.
An M logic mixed chip is formed.

[0004] In such a conventional DRAM logic mixed chip, since titanium silicide 117 is formed in P ⁺ and N ⁺ diffusion layers 115 and 116 such as a source / drain diffusion layer in a logic circuit portion, the resistance is low and the on-current is low. Becomes larger. However, in the manufacturing process sequence, after the diffusion layers 115 and 116 in the logic circuit portion are made to be titanium silicide, the pad polysilicon 112 is added to the memory cell portion.
Is formed. Here, the titanium silicide 117 is vulnerable to heat, and the resistance increases when the heat treatment is excessive. Therefore, the temperature and time of the heat treatment are limited when the pad polysilicon 112 is formed, but if the heat treatment is small, the resistance of the pad polysilicon 112 itself and the pad polysilicon 1
12 and the N ^- increases the contact resistance between the diffusion layer 108, bit line contact resistance at the memory cell portion, the capacitor contact resistance is large, a problem that the access speed is low in the memory cell area occurs.

As a method of overcoming such an increase in bit line contact resistance in the memory cell portion, there is a technique disclosed in Japanese Patent Application Laid-Open No. 9-181269. In this technique, as in the conventional example of FIG. 6, first, FIG.
As shown in FIG.
At 02, an element isolation is formed, a gate oxide film 103 is formed, polysilicon is deposited and patterned to form a gate electrode 104. Subsequently, phosphorus ions are implanted into the entire surface using the gate electrode 104 as a mask to form an N ^- diffusion layer 108. Thereafter, a silicon oxide film is deposited and etched back to form sidewalls 114 on the side surfaces of the gate electrode. Subsequently, as shown in FIG. 7B, an interlayer film 110 is formed on the entire surface with a silicon oxide film or the like, and a bit line contact hole in the memory cell portion is opened. Then, polysilicon is deposited on the entire surface to fill the bit line contact hole with the polysilicon, and subsequently, the polysilicon is patterned to form a bit line 121.

Subsequently, as shown in FIG. 7 (c), the interlayer film 110 in the logic circuit portion is removed, and ions of impurities are implanted into the N ⁺ diffusion layer 11 including the source / drain diffusion layers.
5 and P ⁺ diffusion layer 116 are formed. Thereafter, annealing is performed in a nitrogen atmosphere to activate impurities in each diffusion layer. At this time, the bit line contact portion of the memory cell portion is also activated simultaneously, and the contact resistance decreases.
Subsequently, heat treatment is performed by sputtering titanium, so that the bit line 121 in the memory cell portion and the diffusion layer 11 in the logic circuit portion are formed.
5, 116, a titanium silicide 117 is formed on the gate electrode 104. Thereafter, the titanium that has not been silicided is removed by immersing it in an aqueous ammonia solution.

Subsequently, as shown in FIG. 8A, an interlayer oxide film 123 is deposited on the entire surface, and a capacitor contact hole is opened in the memory cell portion to a depth reaching the N ⁻ diffusion layer 108. Thereafter, TiN is deposited on the entire surface by a sputtering method, and then tungsten is grown by a CVD method or the like, and the contact holes are buried to form capacitor contacts 125. Further, an interlayer oxide film 126 is formed, an opening is formed on the capacitor contact 125, the lower electrode 128 of the memory cell capacitor 131 is made of tungsten, the capacitor insulating film 129 is made of Ta ₂ O ₅ , and the upper electrode 1 is formed.
30 is formed of TiN. After that, the interlayer oxide film 1
32, and the contact 13 is formed as shown in FIG.
3 and the wiring 122, and the through hole 135 and the wiring 13
4 are formed.

As described above, according to the improved manufacturing method, after the pad polysilicon 112 is formed by burying polysilicon in the bit line contact, the contact resistance is lowered by annealing, and then the diffusion layer 11 of the logic circuit portion is formed.
5, 116, the gate electrode 104 and the bit line 121 are made of titanium silicide, so that the titanium silicide 117 is not damaged by heat, the resistance of the contact 120 of the bit line 121 is reduced, and the access speed of the memory cell is increased. Can be realized.

[0009]

However, in this manufacturing method, since the capacitor contact 125 on the N ⁻ diffusion layer 108 in the memory cell portion is formed by burying TiN and tungsten in the contact hole, the capacitor contact 125 is formed. There is a problem that leakage between the silicon substrate 101 and the silicon substrate 125 increases. That is, if the TiN at the bottom of the capacitor contact 125 is in direct contact with the N ⁻ diffusion layer 108, a defect occurs at the contact portion, and the defect occurs in the N ⁻ diffusion layer 10.
8 and the PN junction of the silicon substrate 101,
This causes an increase in leakage current. In the above-described example, the capacitor contact 125 is formed of TiN and tungsten. However, according to the current technology, even if the capacitor contact 125 is embedded with another conductive material other than silicon, particularly a metal, the leakage between the capacitor contact 125 and the silicon substrate 101 is large. Become. When the leakage of the capacitor contact 125 is large, the retention time of the charge (data) in the memory cell is shortened, and the reliability of the DRAM is reduced.

Further, the above-mentioned manufacturing method has a problem that the number of wiring layers is large and the manufacturing cost is high. This is because the number of wiring layers can be reduced by one if the conductive layer forming the bit line 121 can be used as wiring in the logic circuit portion. However, in the above-described conventional method, the logic circuit portion is formed after the bit line 121 is formed by patterning. Is etched until it becomes possible to form source / drain diffusion layers on the surface of the silicon substrate 101, so that it is impossible to form a wiring of the same layer as the bit line 121 in the logic circuit portion. This is because

An object of the present invention is to provide a method of manufacturing a DRAM logic mixed chip which satisfies the following three conditions at the same time. The first is to increase the speed of access to the memory cell by lowering the resistance of the bit line contact and the capacitance contact of the memory cell portion of the DRAM while siliciding the diffusion layer of the logic circuit portion to increase the speed and increase the integration. is there. Second, the leakage current between the capacitor contact and the semiconductor substrate is reduced to improve the charge retention characteristics in the DRAM memory cell. Third, by forming wiring in the same layer as the bit line in the logic circuit portion, the number of wiring layers is reduced, and the manufacturing cost is reduced.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a DRAM logic mixed chip in which a memory cell portion of a DRAM and a logic portion as a peripheral circuit are mounted on one semiconductor substrate. Forming pad polysilicon on a bit line and a capacitor contact forming portion connected to the diffusion layer of the cell portion; and forming metal on at least the surface of the source / drain diffusion layer of the MOS transistor of the logic portion after forming the pad polysilicon. Forming a silicide. Further, in the present invention, a step of simultaneously forming a bit line connected to a part of the pad polysilicon and a wiring connected to the source / drain diffusion layer; And forming a capacitor to be connected. Here, the bit line and the wiring are formed first,
The capacitor is formed on the upper layer. Alternatively, the capacitor is formed first, and the bit line and the wiring are formed thereon.

As a preferred embodiment of the present invention, a step of forming a MOS transistor forming a memory cell portion of a DRAM and a MOS transistor forming a logic portion on a semiconductor substrate, and forming an interlayer film covering each of the MOS transistors. Forming a contact hole in the interlayer film corresponding to the diffusion layer of the MOS transistor in the memory cell portion, forming pad polysilicon by burying polysilicon in the contact hole; Forming the source / drain diffusion layers of the PMOS transistor and the NMOS transistor by introducing a P-type impurity and an N-type impurity, respectively, and depositing a metal on the entire surface and performing a heat treatment. Forming a metal silicide on the pad polysilicon and the source / drain diffusion layers Forming an interlayer insulating film covering the memory cell portion and the logic portion, forming a bit line connected to a metal silicide on a part of the pad polysilicon, and simultaneously forming a metal on the source / drain diffusion layer. Forming a wiring connected to silicide; and forming a capacitor connected to metal silicide on another part of the pad polysilicon.

According to another preferred embodiment of the present invention, there is provided an M-type memory cell for a DRAM on a semiconductor substrate.
Forming an OS transistor and a MOS transistor forming a logic portion; forming an interlayer film covering each of the MOS transistors;
Forming a contact hole in the interlayer film corresponding to the diffusion layer of the OS transistor, forming a pad polysilicon by burying polysilicon in the contact hole, and forming a part of the interlayer film in the logic part; Forming a source / drain diffusion layer of a PMOS transistor and an NMOS transistor by introducing a P-type impurity or an N-type impurity by using the mask, respectively; Forming a metal silicide on each of the source / drain diffusion layers by depositing a metal on the drain diffusion layer and performing a heat treatment, and forming an interlayer insulating film covering the memory cell portion and the logic portion; Forming a bit line connected to the pad polysilicon at the same time as connecting to the metal silicide of the source / drain diffusion layer And forming a wiring, and forming a capacitor connected to the pad polysilicon portion of another.

In the present invention, the pad polysilicon in the memory cell portion is formed first, and then the metal silicide is formed. Therefore, after the pad polysilicon is formed, a sufficient heat treatment is performed so that the resistance of the pad polysilicon and the pad polysilicon are formed. Even if the contact resistance between silicon and the diffusion layer is reduced, the metal silicide will not be damaged by heat. Access speed can be increased. Further, by forming the capacitance contact with polysilicon, it is possible to reduce the leak current between the contact and the semiconductor substrate and improve the charge retention characteristics in the memory cell of the DRAM. Further, by forming wirings in the same layer as the bit lines also in the logic circuit portion, the number of wiring layers can be reduced and the manufacturing cost can be reduced.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a method of manufacturing a DRAM logic mixed chip according to a first embodiment of the present invention. First, as shown in FIG.
First, a trench is formed in the element isolation region on 1 and the trench is filled with an insulating film to form a trench isolation 102. continue,
As shown in FIG. 1B, a gate oxide film 103 is formed by performing a gate oxidation, and further a polysilicon 104 is formed thereon.
And a tungsten silicide 105 are deposited thereon, and a silicon nitride film 106 is further deposited thereon, followed by patterning by photolithography and anisotropic etching techniques to form a gate electrode 107. Subsequently, phosphorus is ion-implanted at 2E13 / cm ² using the gate electrode 107 as a mask to form an N ⁻ diffusion layer 108. Thereafter, a silicon nitride film 109 is deposited on the entire surface to a thickness of 80 nm.

Subsequently, as shown in FIG. 1C, a silicon oxide film 110 serving as an interlayer film is deposited on the entire surface, and is contacted to the capacitor contact portion and the bit line contact portion of the memory cell portion by using a photolithography technique. A hole 111 is opened. This opening is first formed in the silicon nitride film 109.
After the silicon oxide film 110 is anisotropically etched using this as a stopper, only the silicon nitride film 109 is anisotropically etched under the condition that the silicon oxide film 110 is not etched. Then, phosphorus is 2E20
/ Cm ³ doped polysilicon is deposited on the entire surface and etched back to fill the contact hole 111 with the phosphorus-doped polysilicon, and form the pad polysilicon 112 with the buried polysilicon.

Subsequently, as shown in FIG. 1D, a resist mask 113 is formed so as to cover the memory cell portion and open the logic circuit portion, and anisotropic etching is performed using the resist mask 113 as a mask. In this etching, first, the silicon oxide film 110 as an interlayer film is etched under the condition that the silicon nitride film 109 is not etched, and then the silicon nitride film 109 is etched under the condition that the silicon oxide film 110 and the silicon substrate 101 are not etched. During the etching of the silicon nitride film 109, a sidewall 114 is formed of the silicon nitride film 109 on the side wall of the gate electrode 107 in the logic circuit portion. Thereafter, although not shown in detail, a silicon oxide film is deposited on the entire surface to a thickness of 10 nm. Then, a resist mask in which the NMOS portion of the logic circuit portion is opened is formed by a photolithography technique, and As is ion-implanted at 3E15 / cm ² to perform NMO.
An N ⁺ diffusion layer 115 including an S source / drain diffusion layer is formed. Then, PMOS portion to form a P ⁺ diffusion layer 116 having a source-drain diffusion layers of the PMOS and implanting BF2 to form a resist mask having an opening at 1E15 / cm ^2. Then, in a nitrogen atmosphere, 1000
Perform lamp annealing at 30 ° C. for 30 seconds. By this lamp annealing, the resistance of the pad polysilicon 112 in the memory cell portion is reduced including the contact portion with the N ⁻ diffusion layer 108. In addition, the source / drain diffusion layer 1 of the logic circuit portion
The activation of the impurities 15 and 116 proceeds, and the layer resistance decreases.

Subsequently, the silicon oxide film having a thickness of 10 nm is removed to form the N ⁺ and P ⁺ diffusion layers 1 of the logic portion.
15 and 116 and the upper portions of the pad polysilicon 112 in the memory cell portion are exposed. Then, titanium is deposited to a thickness of 40 nm and annealed at about 650 ° C. in a nitrogen atmosphere to form titanium silicide 11 on each diffusion layer in the logic circuit portion and on the pad polysilicon in the memory cell portion.
7 is formed. Thereafter, unreacted titanium is removed by etching with hydrofluoric acid, and heat treatment is again performed at about 800 ° C. in a nitrogen atmosphere to cause a layer transition of titanium silicide to lower the resistance. As described above, the result is as shown in FIG.

Subsequently, as shown in FIG. 2A, an interlayer oxide film 118 such as a silicon oxide film is deposited on the entire surface and planarized by CMP. After that, a contact hole is opened in the bit line contact portion and the logic circuit portion of the memory cell,
Titanium, titanium nitride, and tungsten are deposited, and this is etched back to bury the contact holes.
19 and 120 are formed. Subsequently, tungsten is deposited,
By patterning, a bit line 121 and a wiring 122 of a peripheral circuit portion are formed. Further, as shown in FIG. 2B, an interlayer oxide film 123 is formed, a capacitor contact hole 124 is opened, titanium, titanium nitride, and tungsten are deposited, and this is etched back to fill the contact hole 124.
A capacitance contact 125 is formed. Subsequently, an interlayer oxide film 126 covering the capacitor contact 125 is formed, an opening 127 is provided on the capacitor contact 125, a capacitor lower electrode 128 is formed in the opening in tungsten, and a capacitor insulating film 129 is formed of Ta ₂ O. ₅ , the capacitor upper electrode 130 is set to T
The capacitor 131 is formed using iN. Thereafter, a layer interlayer oxide film 132 is deposited, and a contact 133 and an aluminum wiring 134 are formed as shown in FIG.
A RAM logic mixed chip is manufactured.

In this embodiment, as in the conventional example, the source / drain diffusion layers 115 and 116 of the logic circuit portion are silicided by titanium silicide 117, so that the logic circuit portion achieves high speed and high integration. . In the DRAM memory cell portion, the capacity contact 125,
Pad polysilicon 112 of bit line contact 120
In this case, the pad polysilicon 112 is reduced in resistance including the contact resistance with the N ⁻ diffusion layer 108 because of high-temperature lamp annealing. Since the bit line contact 120 and the capacitor contact 125 formed on the pad polysilicon 112 are formed of tungsten, the resistance is low, and there is an advantage that the access speed of the DRAM is high. Also, the capacitance contact 125
Since the pad polysilicon 112 comes into contact with the N ⁻ diffusion layer 108, the leakage current between the pad polysilicon 112 and the silicon substrate 101 is reduced, and the retention characteristics of the DRAM are improved. Since the contact portion of the capacitor contact 125 between the titanium, titanium nitride, and tungsten and the pad polysilicon 112 is apart from the PN junction, the leakage current does not increase at this portion. Further, in the logic circuit portion, the bit line 12
Since the wiring 122 is formed in the same layer as the wiring layer 1, the number of wiring layers can be reduced, and the manufacturing cost is reduced.

In this embodiment, the source and drain diffusion layers 115 and 116 in the logic circuit portion and the pad polysilicon 112 in the memory cell portion are made into titanium silicide. A simple silicide, for example, cobalt silicide may be used.

In the first embodiment, the present invention is applied to DRA
The M part is applied to a DRAM logic mixed chip of COB (Capacitor Over Bitline: structure in which DRAM capacity is formed on a bit line), but the DRAM part is CUB (Capacitor Over Bitline).
tor Under Bit line: a structure in which a DRAM capacity is formed below a bit line). The second embodiment uses such a C
This is a manufacturing method of a DRAM logic mixed chip to which UB is applied. FIG. 3 is a cross-sectional view of the manufacturing process, in which parts equivalent to those in the first embodiment are denoted by the same reference numerals. First,
Source / drain diffusion layers 115 and 11 in logic circuit section
1 and the process until the upper portion of the pad polysilicon 112 in the memory cell portion is made into titanium silicide,
The steps up to (e) are the same as in the first embodiment. Thereafter, as shown in FIG. 3A, an interlayer oxide film 118 such as a silicon oxide film is deposited on the entire surface, and is planarized by CMP. further,
The interlayer oxide film 118 of the capacitor forming portion is formed by using the pad polysilicon 1 by photolithography and anisotropic etching techniques.
12 until the titanium silicide 117 on the substrate 12 is reached. Subsequently, the capacitor lower electrode 128 is formed of tungsten, the capacitor insulating film 129 is formed of Ta ₂ O ₅ , and the capacitor upper electrode 130 is formed of TiN.

Next, as shown in FIG. 3B, an interlayer oxide film 123 such as a silicon oxide film is deposited, and a bit line contact 120 in a memory cell portion and a contact 119 in a logic circuit portion are formed of tungsten. The bit line 121 and the logic part wiring 122 are formed by wiring. Thereafter, an interlayer oxide film 132 is deposited to open a through-hole 135, and a second-layer metal wiring 134 is formed of aluminum to manufacture a DRAM.

In the DRAM logic mixed chip according to the present embodiment, the advantages of the first embodiment are obtained, and since the bit line is formed on the upper layer after the capacitor is formed, the area for passing the capacitor contact is reduced. Since the size of the bit line can be increased as much as it is not necessary to secure it, and the degree of freedom of arrangement can be increased, the resistance of the bit line decreases,
The advantage that the access speed of the DRAM section is improved is also obtained.

Next, in the third embodiment, etching of the interlayer film of the logic circuit portion is performed by using a mask for ion implantation of the source / drain diffusion layers. Hereinafter, the manufacturing method according to the third embodiment will be described. Note that parts equivalent to those in the first and second embodiments are denoted by the same reference numerals. FIG.
1A, the gate electrode is patterned in the same manner as in the first embodiment shown in FIGS. 1A to 1C, and thereafter, the entire surface is subjected to a thermal oxidation treatment (not shown in FIG. 2 shows a state in which a silicon oxide film having a thickness of 3 nm is formed, a silicon nitride film 109 and a silicon oxide film 110 are formed thereon, and further a pad polysilicon 112 is formed. Thereafter, as shown in FIG. 4A, a silicon nitride film 140 is deposited over the entire surface by 500.degree. Subsequently, as shown in FIG. 4B, a resist mask 141 is formed by photolithography so as to open an NMOS formation region other than the memory cell portion. Next, using this as a mask, the interlayer film 110 is etched until a silicon oxide film having a thickness of 10 nm (not shown) on the silicon substrate 101 is exposed. In this etching, first, the silicon nitride film 140 is anisotropically etched, then the silicon oxide film 110 is anisotropically etched using the silicon nitride film 109 as a stopper, and then the silicon oxide film 110 is not etched.
Only the silicon nitride film 109 is anisotropically etched. By this etching, sidewalls 114 are formed on the sidewalls of the gate electrode 107. Subsequently, arsenic is ion-implanted at 3E15 / cm ² while the resist mask 141 is left, and the N ⁺ diffusion layer 115 including the source / drain diffusion layer is implanted.
To form After that, the resist mask 171 is removed.

Next, as shown in FIG.
A resist mask 142 is formed so as to open the formation region, and the interlayer film 110 is etched using the resist mask as a mask until the 10 nm thick silicon oxide film on the silicon substrate 101 is exposed in the same manner as the NMOS formation region. Subsequently, BF2 is applied to 1E15 while the resist mask 142 is left.
/ Cm ² ions are implanted to form a P ⁺ diffusion layer 116 including source / drain diffusion layers. After that, the resist mask 142 is removed. After that, 100 minutes in a nitrogen atmosphere.
Perform lamp annealing at 0 ° C. for 30 seconds. By this lamp annealing, the pad polysilicon 112 in the memory cell portion is
Is reduced including the contact portion with the N ⁻ diffusion layer 108. Further, the activation of the impurities in each of the diffusion layers 115 and 116 in the logic circuit portion proceeds, and the layer resistance decreases.

Subsequently, as shown in FIG. 4D, the silicon oxide film having a thickness of 10 nm in the opening is etched to expose the diffusion layers 115 and 116, and titanium is sputtered to a thickness of 40 nm. Anneal in a nitrogen atmosphere at about 650 ° C. As a result, the diffusion layers 115 and 11 of the logic circuit portion are formed.
6, a titanium silicide 117 is formed. After this,
Unreacted titanium is removed by etching with hydrofluoric acid, and heat treatment is again performed at about 800 ° C. in a nitrogen atmosphere to cause a layer transition of titanium silicide to lower the resistance. In this embodiment, since the pad polysilicon 112 in the memory cell portion is covered with the silicon nitride film 140, it is not turned into titanium silicide.

Subsequently, as shown in FIG. 5A, a silicon oxide film 143 is deposited on the entire surface, and the silicon oxide film 143 is formed by CMP using the silicon nitride film 140 as a stopper.
Flattening. Subsequently, as shown in FIG. 5B, an interlayer oxide film 118 is formed, and the capacitor lower electrode 128, the capacitor insulating film 129, and the capacitor upper electrode 130 are formed as in the second embodiment.
To form a DRAM capacitor 131. Thereafter, as shown in FIG. 5C, an interlayer oxide film 123 is deposited, a bit line contact 120 in the memory cell portion and a contact 119 in the logic circuit portion are formed of tungsten, and the bit line 121 and the logic are formed by tungsten wiring. The internal wiring 122 is formed, an interlayer oxide film 132 is formed thereon, and the through-hole 135 and the aluminum wiring 13
4 to form a DRAM logic mixed chip.

In this embodiment, as in the first embodiment, since the titanium silicide 117 is formed in the diffusion layers 115 and 116 of the logic circuit portion, the logic circuit is high speed and highly integrated. In addition, since the pad polysilicon 112 is formed on the capacitor 131 and the bit line contact 120 in the DRAM memory cell portion and high-temperature lamp annealing is performed, there is an advantage that the access speed of the DRAM is high and the retention characteristics are good. Further, as in the second embodiment, the bit line 121 can be formed without being restricted by the metal wiring, and the size of the bit line can be increased.
1 has the advantage of lowering the resistance and improving the access speed of the memory cells of the DRAM. Further, in this embodiment, the resist masks 141 and 142 for etching the interlayer film 110 in the NMOS region and the PMOS region other than the memory cell portion may be used as ion implantation masks for the N ⁺ diffusion layer 115 and the P ⁺ diffusion layer 116. Since it is used, there are advantages that the number of photolithography steps is small and the manufacturing cost is low.

[0031]

As described above, the present invention relates to a DRAM.
In the manufacture of a DRAM logic mixed chip in which the memory cell part and the logic part are mounted on one semiconductor substrate,
Since the pad polysilicon in the memory cell portion is formed first, and then the metal silicide is formed, a sufficient heat treatment is performed after the pad polysilicon is formed, so that the resistance of the pad polysilicon and the contact resistance between the pad polysilicon and the diffusion layer are formed. Even if the temperature is lowered, the metal silicide will not be damaged by heat, and the diffusion layer in the logic circuit section will be silicided to increase the speed and integration while increasing the access speed to the memory cells in the memory cell section. Becomes possible.
In addition, by forming the capacitance contact for storing the charge of the memory cell with polysilicon, it is possible to reduce the leak current between the contact and the semiconductor substrate and to improve the charge retention characteristics in the DRAM memory cell. . further,
By forming wiring in the same layer as the bit lines in the memory cell section also in the logic circuit section, the number of wiring layers can be reduced and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a second sectional view showing the first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing a part of a manufacturing process according to a second embodiment of the present invention.

FIG. 4 is a first sectional view showing a third embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a second sectional view showing the third embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a cross-sectional view showing an example of a conventional manufacturing method in the order of manufacturing steps.

FIG. 7 is a first sectional view showing a conventional improved manufacturing method in the order of manufacturing steps.

FIG. 8 is a second sectional view showing a conventional improved manufacturing method in the order of manufacturing steps.

[Explanation of symbols]

Reference Signs List 101 silicon substrate 104 polysilicon 109 silicon nitride film 110 interlayer film (silicon oxide film) 112 pad polysilicon 114 sidewall 115 N ⁺ diffusion layer 116 P ⁺ diffusion layer 117 titanium silicide 120 bit line contact 121 bit line 122 wiring 128 capacity lower part Electrode 129 Capacitance insulating film 130 Capacitance upper electrode 131 Capacitance 133 Contact 134 Metal wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 481 F term (Reference) 5F048 AB01 AC03 BA01 BB08 BF03 BG13 BG14 DA27 5F083 AD24 AD48 GA02 GA27 JA06 JA35 JA39 JA40 KA05 MA06 MA17 NA01 PR36 PR39 PR40 ZA05 ZA06 ZA12

Claims (6)

[Claims] 1. A method of manufacturing a DRAM logic mixed chip in which a memory cell portion of a DRAM and a logic portion as a peripheral circuit are mounted on one semiconductor substrate, wherein the chip is connected to a diffusion layer of the memory cell portion. Forming pad polysilicon in a bit line and a capacitor contact forming portion;
Forming a metal silicide on at least the surface of the source / drain diffusion layer of the MOS transistor in the logic portion after forming the pad polysilicon. 2. A step of simultaneously forming a bit line connected to a part of said pad polysilicon and a wiring connected to said source / drain diffusion layer, and connecting to another part of said pad polysilicon. And forming a capacitor to be formed. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: 3. The method according to claim 2, wherein the bit line and the wiring are formed first, and the capacitor is formed thereon.
3. The method for manufacturing a semiconductor integrated circuit device according to 1. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the capacitor is formed first, and the bit line and the wiring are formed thereon. 5. A step of forming a MOS transistor forming a memory cell part of a DRAM and a MOS transistor forming a logic part on a semiconductor substrate, a step of forming an interlayer film covering each of the MOS transistors, Opening a contact hole in the interlayer film corresponding to the diffusion layer of the MOS transistor in the portion, forming a pad polysilicon by burying polysilicon in the contact hole, and forming a pad polysilicon in the logic portion. Removing and introducing a P-type impurity and an N-type impurity to form source / drain diffusion layers of the PMOS transistor and the NMOS transistor, respectively; And each source
Forming a metal silicide on the drain diffusion layer;
Forming an interlayer insulating film covering the memory cell portion and the logic portion, forming a bit line connected to a metal silicide on a part of the pad polysilicon, and simultaneously connecting to a metal silicide on the source / drain diffusion layer; And forming a capacitor connected to a metal silicide on another part of the pad polysilicon. A method for manufacturing a semiconductor integrated circuit device, comprising: 6. A step of forming a MOS transistor forming a memory cell portion of a DRAM and a MOS transistor forming a logic portion on a semiconductor substrate, a step of forming an interlayer film covering each of the MOS transistors, Opening a contact hole in the interlayer film corresponding to the diffusion layer of the MOS transistor in the portion, forming a pad polysilicon by burying polysilicon in the contact hole, and forming a pad polysilicon in the logic portion. Forming a source / drain diffusion layer of each of a PMOS transistor and an NMOS transistor by removing a part using a mask and introducing a P-type impurity or an N-type impurity using the mask; A metal is deposited on each of the source / drain diffusion layers, and heat treatment is performed. Forming a metal silicide on a layer, forming an interlayer insulating film covering the memory cell part and the logic part, forming bit lines connected to some of the pad polysilicon, and simultaneously forming the source / drain diffusion layers Forming a wiring connected to said metal silicide, and forming a capacitor connected to another part of said pad polysilicon.