JP4439429B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a cell structure of, for example, a dynamic RAM (hereinafter referred to as DRAM), and in particular, an STC (Stacked Capacitor) type semiconductor in which a memory cell capacitor is formed above a bit line in a self-aligned manner with respect to the bit line. the method of manufacturing a semiconductor equipment to be applied to the storage device about.

  Recently, semiconductor memory devices, especially DRAMs, have been integrated on a large scale. Accordingly, the proportion of unit memory elements tends to be further reduced, and in order to obtain a sufficient capacity for reading and writing (20 fF or more), it is essential to make the memory cell capacitor and the memory cell transistor three-dimensional. For this reason, a cell structure using a trench type capacitor and an STC type capacitor is generalized.

  Further, for further large-scale integration, in a cell using an STC type capacitor, a technique for forming a memory cell capacitor in a self-aligned manner with respect to a bit line is important. A memory cell in which a conventional method for manufacturing an STC capacitor is described has been proposed (for example, see Non-Patent Document 1). FIG. 21 and FIG. 23 show such examples.

  FIG. 21 shows a plan view of the memory cell. In FIG. 21, 201 is a channel region, 202 is a gate electrode pattern, 203 is a bit line contact, 204 is a bit line pattern, 205 is a storage node contact pattern, and 206 is a storage node electrode pattern.

  FIG. 22 shows a manufacturing process of a sectional view taken along the line 22-22 in FIG. As shown in FIG. 22A, on the semiconductor substrate 51, an element isolation oxide film 52, a data transfer MOS transistor (not shown), a first interlayer insulating film 53, a bit line contact (not shown), a bit line 54, A second interlayer insulating film 55 made of a BPSG film is formed. Next, a storage node contact 56 reaching the semiconductor substrate 51 is formed in the first and second interlayer insulating films 53 and 55 positioned between the bit lines 54 by a known lithography method and RIE (Reactive Ion Etching) method. Is done.

Next, as shown in FIG. 22B, an HTO (High Temperature Oxide) film 57 is deposited on the entire surface, and the entire surface is etched back by the RIE method. As shown in FIG. Sidewall spacers 58 made of HTO film 57 are formed inside 56.
M. Fukumoto et al., "Stacked capacitor cell technology for 16M DRAM using double self aligned contacts", ESSDERC 90, pp.461-464, 1990

  When the storage node contact pattern 205 shown in FIG. 21 is misaligned with the bit line pattern 204, the following problem occurs. That is, as shown in FIG. 23A, when the storage node contact 56 is formed, the bit line 54 is exposed from the first and second interlayer insulating films 53 and 55. In this state, as shown in FIG. 23B, an HTO film 57 is deposited on the entire surface, and the entire surface is etched back by the RIE method. As shown in FIG. Sidewall spacers 58 are formed from the HTO film 57. Then, sidewall spacers 58 are formed on the bit lines 54 and on the sidewalls of the second interlayer insulating film 55. However, since a part of the bit line 54 is exposed from the gap between the sidewall spacers 58, a problem arises that a storage node (not shown) and the bit line 54 to be formed later are short-circuited.

  Further, when the entire surface of the HTO film 57 is etched back, since the HTO film 57 and the second interlayer insulating film 55 are made of the same silicon oxide, a sufficient selection ratio cannot be obtained. There is a problem that it is difficult to control the thickness of the interlayer insulating film 55.

  Further, when the storage node contact 56 is formed, there is a problem that it is difficult to form a resist pattern itself because both the contact opening and the contact interval are minute. Further, since the storage node contact 56 does not have a square shape as shown in the pattern, but has a circular shape with a minimum dimension inscribed in the square pattern as a diameter, as shown by a broken line in FIG. 21, the contact area is reduced and the contact resistance is reduced. Has the problem of increasing. Further, since the storage node contact 56 reaches the semiconductor substrate 51, the aspect ratio is increased, the yield of the contact opening is poor, and it is difficult to embed the storage node.

The present invention solves the above-mentioned problems, and the object of the present invention is to prevent a short circuit between the contact and the wiring, and to form the contact in a self-aligning manner, and to be formed on the wiring. with the film thickness of the film can be reliably controlled that, fine contact can be formed, high yield of the contact opening, in which the buried contact is to provide a manufacturing method of easily semiconductor equipment.

The method of manufacturing a semiconductor device of this invention includes the steps of forming a first insulating film on a semiconductor substrate, forming a first conductive film on the first insulating film, the first conductive film A step of forming a protective film, a step of locally etching the protective film and the first conductor film to form a plurality of wirings adjacent to each other at a predetermined interval, and forming a second insulating film on the entire surface, The step of planarizing the second insulating film using the protective film as a stopper to form a second insulating film between the plurality of wirings, the protective film on the plurality of wirings, and the second insulating film on the second insulating film A step of forming a photoresist using a line / space contact pattern orthogonal to a plurality of wirings at a predetermined interval, and using the photoresist and the protective film as a mask, the second insulating film and the first insulating film The film is etched to Forming a step of forming a plurality of contact holes, a third insulating film on the sidewall and the sidewall of the first insulating film of said plurality of contact holes inside at least the first conductive film between, on the entire surface A step of depositing a second conductor film, and a step of planarizing the second conductor film using the protective film as a stopper and forming plugs in the plurality of contact holes.

According to the present invention, a short circuit between a contact and a wiring can be prevented, the contact can be formed in a self-aligning manner, and the film thickness of a film formed on the wiring can be reliably controlled, and a minute Contacts can be formed, high yield of the contact opening, the embedding of the contact can be provided a method of manufacturing easily semiconductor equipment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a first embodiment of the present invention. As shown in FIG. 1A, a conductive film 2 such as tungsten (W), a second insulating film 3 made of silicon oxide, and a nitrided film are formed on a first insulating film 1 made of silicon oxide formed on a semiconductor substrate 11. A silicon-based third insulating film 4 is sequentially formed. Thereafter, the third insulating film 4, the second insulating film 3, and the conductive film 2 are patterned using a predetermined wiring pattern to form the wiring L.

  Next, as shown in FIG. 1B, a silicon oxide-based fourth insulating film 5 is deposited, and the surface is flattened using a CMP (Chemical Mechanical Polishing) method. Next, as shown in FIG. 1C, a photoresist 6 is formed using a predetermined contact hole pattern, and etching conditions having a high selectivity with respect to the photoresist 6 and the third insulating film 4 are used. Then, the fourth and first insulating films 5 and 1 are etched by the RIE method to form contact holes CH.

  Next, the resist 6 is removed, a fifth insulating film 7 is deposited on the entire surface, and this is etched back by the RIE method. As shown in FIG. 1D, the fifth insulating film 7 is formed in the contact hole CH. A side wall spacer 7a is formed. The sidewall spacers 7 a are formed on the side walls of the first insulating film 1, the conductive film 2, the second insulating film 3, the third insulating film 4, and the fourth insulating film 5.

  As described above, since the conductive film 2 is protected by the third insulating film 4, the conductive film 2 is not exposed even when the mask is misaligned when etching is performed by the RIE method. Therefore, even if a conductive layer is subsequently formed in the contact hole CH, a short circuit between the conductive film 2 and the conductive layer can be prevented.

  FIG. 2 shows a second embodiment of the present invention, and the same parts as those in FIG. The process until the predetermined wiring L is formed is the same as that in the first embodiment. After the wiring L is formed, a silicon oxide-based fourth insulating film 5 is deposited on the entire surface, and the surface of the fourth insulating film 5 is flattened by CMP as shown in FIG. At this time, the fourth insulating film 5 is planarized according to the upper surface of the third insulating film 4 by using the third insulating film 4 as a CMP stopper.

  Next, a photoresist 6 is formed using a predetermined contact hole pattern, and etching conditions having a high selection ratio with respect to the photoresist 6 and the third insulating film 4 are used, as shown in FIG. The fourth and first insulating films 5 and 1 are etched by the RIE method to form contact holes CH.

  Next, after removing the resist 6, a fifth insulating film 7 is deposited on the entire surface, and the entire surface is etched back using the RIE method, so that the fifth hole is formed in the contact hole as shown in FIG. Sidewall spacers 7a made of the insulating film 7 are formed.

  Also in this embodiment, since the conductive film 2 is protected by the third insulating film 4, the conductive film 2 is not exposed even when the mask is misaligned when etching is performed by the RIE method. Therefore, even if a conductive layer is subsequently formed in the contact hole CH, a short circuit between the conductive film 2 and the conductive layer can be prevented. Furthermore, since the film thickness of the insulating film on the conductive film 2 is defined by the film thicknesses of the second and third insulating films, it has an advantage of good controllability.

  In the first and second embodiments, the material of the fifth insulating film 7 is, for example, any one of a silicon oxide film and a composite film of a silicon nitride film and a silicon oxide film. The dielectric constant is set smaller than that of a silicon-based film.

  3 and 4 show a third embodiment of the present invention. The same reference numerals are given to the same parts as those in the first and second embodiments. Using the stripe-shaped wiring pattern 8 shown in FIG. 3, as shown in FIG. 1A, the process is the same as in the first and second embodiments until the wiring L is formed. Thereafter, a silicon oxide-based fourth insulating film 5 is deposited on the entire surface, and the surface of the fourth insulating film 5 is flattened in accordance with the upper surface of the third insulating film 4 by CMP, as shown in FIG. Turn into. In FIG. 4, the semiconductor substrate is omitted.

  Next, as shown in FIG. 3, a photoresist 6 as shown in FIG. 4B is formed using a line / space contact hole pattern 9 orthogonal to the wiring pattern 8. Thereafter, the etching conditions having a high selectivity with respect to the photoresist 6 and the third insulating film 4 are used to etch the fourth and first insulating films 5 and 1 by the RIE method. Form.

  Next, after removing the resist 6 and depositing a fifth insulating film 7 on the entire surface, this is etched back by the RIE method, thereby forming a sidewall spacer in the contact hole CH as shown in FIG. 7a is formed. The widths of the wiring pattern 8 and the contact hole pattern 9 are the minimum dimensions determined by the design rule.

  Also in this embodiment, since the conductive film 2 is protected by the third insulating film 4, the conductive film 2 is not exposed even when the mask is misaligned when etching is performed by the RIE method. Therefore, even if a conductive layer is subsequently formed in the contact hole CH, a short circuit between the conductive film 2 and the conductive layer can be prevented. Moreover, since the film thickness of the insulating film on the conductive film 2 is defined by the film thicknesses of the second and third insulating films, it has an advantage of good controllability. Furthermore, since the contact hole pattern 9 has a line / space shape, the contact hole can be easily formed. In addition, by using a line / space-shaped contact hole pattern, the contact hole becomes a square having one side as a minimum dimension determined by the design rule. Therefore, since the contact hole does not become a circle inscribed in a square having a minimum dimension as one side as in the prior art, the contact area can be increased and the contact resistance can be reduced.

  Next, a fourth embodiment of the present invention will be described with reference to FIGS. The fourth embodiment relates to a manufacturing method when the present invention is applied to an STC type DRAM cell.

  Here, FIG. 5 is a plan view showing a mask pattern applied to the fourth embodiment.

  FIGS. 6A and 6C are cross-sectional views taken along lines aa and cc in FIG. 5 and show a first step of the fourth embodiment.

  FIGS. 7A and 7C are cross-sectional views taken along lines aa and cc in FIG. 5 and show a second step following FIG.

  8A and 8C are cross-sectional views taken along the lines aa and cc in FIG. 5 and show a third step following FIG.

  FIGS. 9A and 9C are cross-sectional views taken along lines aa and cc in FIG. 5 and show a fourth step following FIG.

  FIGS. 10A and 10C are cross-sectional views taken along lines aa and cc in FIG. 5 and show a fifth step following FIG.

  FIGS. 11B and 11C are cross-sectional views taken along lines bb and cc in FIG. 5 and show a sixth step following FIG.

  12B and 12C are cross-sectional views taken along lines bb and cc in FIG. 5 and show a seventh step following FIG.

  FIGS. 13A and 13D are cross-sectional views taken along lines aa and dd in FIG. 5 and show an eighth step following FIG.

  14A and 14D are cross-sectional views taken along the lines aa and dd in FIG. 5 and show a ninth step following FIG.

  FIGS. 15A and 15D are cross-sectional views taken along lines aa and dd in FIG. 5 and show a tenth step following FIG.

  FIGS. 16A and 16D are cross-sectional views taken along lines aa and dd in FIG. 5 and show an eleventh step following FIG.

  FIGS. 17A and 17D are cross-sectional views taken along lines aa and dd in FIG. 5 and show a twelfth step following FIG.

  In FIG. 5, 101 is an element isolation pattern for forming element isolation, 102 is a gate electrode pattern for forming a gate electrode, 103 is a plug pattern for forming a plug, and 104 is for forming a bit line contact. , 105 is a bit line pattern for forming a bit line, 106 is a storage node contact pattern for forming a storage node contact, and 107 is a storage node electrode pattern for forming a storage node electrode. .

  As shown in FIG. 6, an element isolation oxide film 12 is formed on a semiconductor substrate 11 using an STI (Shallow Trench Isolation) technique and using the element isolation pattern 101 shown in FIG. 5 as a mask.

  Next, a gate oxide film (not shown) is formed on the semiconductor substrate 11, and an N-type polysilicon film 13, a tungsten silicide film 14, and a silicon nitride film 15 are sequentially deposited thereon as shown in FIG. 7 (a). To do. Thereafter, the gate electrode pattern 102 shown in FIG. 5 is used to pattern the silicon nitride film 15, the tungsten silicide film 14, and the N-type polysilicon film 13, thereby forming the gate electrode G of the MOSFET. Next, N-type impurities such as As are ion-implanted to form the source / drain diffusion layer 16. Thereafter, a silicon nitride film 17 is deposited on the entire surface and etched back to form side wall spacers 17a made of a silicon nitride film on the side walls of the gate electrode G.

  Next, as shown in FIG. 8, a BPSG film 18 is deposited on the entire surface, and the surface of the BPSG film 18 is planarized by CMP using the silicon nitride film 15 as a stopper. Next, as shown in FIG. 9, a resist 19 is applied to the entire surface, and an etching mask 19a is formed by lithography using the plug pattern 103 shown in FIG. Next, the BPSG film 18 is etched by the RIE method using the etching mask 19a and the silicon nitride film 15 as a mask under the etching conditions in which the selectivity between the BPSG film 18 and the silicon nitride film 15 is high. By this step, the contact hole 20 is formed in a self-aligned manner with respect to the gate electrode G.

  Next, after removing the resist 19, as shown in FIG. 10, an N-type polysilicon film 21 is deposited on the entire surface, and using the silicon nitride film 15 and the BPSG film 18 as a stopper, an N-type polysilicon film is formed by CMP. At the same time as planarizing the surface of the film 21, the contact hole 20 is buried, and a plug 21 a is formed by the N-type polysilicon film 21.

  Next, as shown in FIG. 11, a BPSG film 22 is deposited on the entire surface, and a contact hole 23 is formed using the bit line contact pattern 104 shown in FIG. Next, a tungsten film 24 is selectively grown on the exposed N-type polysilicon film 21, and the contact hole 23 is filled with the tungsten film 24.

  Next, a glue layer (not shown) is formed on the entire surface, and a tungsten film 25, a silicon oxide film 26, and a silicon nitride film 27 are sequentially deposited thereon as shown in FIG. 12, and the bit line pattern 105 shown in FIG. The bit line BL connected to the plug 21 is formed by patterning the silicon nitride film 27, the silicon oxide film 26, the tungsten film 25, and the glue layer.

  Next, as shown in FIG. 13, a silicon oxide film 28 is deposited on the entire surface, and the silicon oxide film 28 is planarized by CMP using the silicon nitride film 27 as a stopper. Next, as shown in FIG. 14, a resist 29 is applied to the entire surface, and an etching mask 29a is formed by lithography using the storage node contact pattern 106 shown in FIG. Thereafter, the silicon oxide film 28 is etched by the RIE method using the etching mask 29a and the silicon nitride film 27 as a mask under etching conditions in which the selection ratio between the silicon oxide film 28 and the silicon nitride film 27 is high. By this step, the contact hole 30 is formed in a self-aligned manner with respect to the bit line BL.

  Next, after removing the resist 29, a silicon oxide film 31 is deposited on the entire surface as shown in FIG. Thereafter, a sidewall spacer 31a made of a silicon oxide film 31 is formed on the inner wall of the contact hole 30 by using an etch back method. Next, as shown in FIG. 16, an N-type polysilicon film 32 is deposited on the entire surface, and the surface of the N-type polysilicon film 32 is planarized by CMP using the silicon nitride film 27 and the silicon oxide film 28 as stoppers. At the same time, the contact hole 30 is filled with the N-type polysilicon film 32 to form a plug 32a.

  Next, as shown in FIG. 17, a ruthenium film 33 is deposited on the entire surface by sputtering and patterned using the storage node electrode pattern 107 shown in FIG. Thereafter, a high dielectric film such as a BST film 34 and a ruthenium film 35 are sequentially deposited on the entire surface to form a storage capacitor. Subsequently, a wiring layer (not shown) is formed by a well-known method, and the DRAM is completed.

  According to the fourth embodiment, in the STC type DRAM cell, since the bit line is protected by the silicon nitride insulating film, the storage node contact pattern is misaligned with the bit line pattern. In this case, the bit line can be prevented from being exposed during the etching. Further, since the insulating film on the bit line is defined by the film thickness, the controllability is good.

  Furthermore, since the storage node contact pattern has a line / space shape, it is possible to prevent the storage node contact from being rounded and to form a square having a minimum dimension as one side. Therefore, the contact area can be increased and the contact resistance can be reduced.

  Further, since the storage node contact does not reach the substrate and is connected to the source / drain region via the conductor plug, the aspect ratio can be reduced. Therefore, it is easy to embed a storage node, and the yield of contact openings can be improved.

  Further, by using a silicon oxide insulating film as the sidewall spacer, an increase in the bit line capacitance can be prevented, and the operation speed can be increased and the current consumption can be reduced.

  FIG. 18 shows a fifth embodiment of the present invention. The same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and only different parts will be described. In the second to third embodiments, the second insulating film 3 and the third insulating film 4 (silicon oxide film 26 and silicon nitride film 27 in the fourth embodiment) are provided on the conductive layer 2. Yes. The material of the third insulating film 4 (the silicon nitride film 27 in the fourth embodiment) has the following conditions.

    (1) When performing RIE of a silicon oxide film, it is a film having a large selection ratio with respect to a silicon oxide film.

    (2) When performing CMP of the silicon oxide film, it is a film having a large selection ratio with respect to the silicon oxide film.

    (3) A film having a large selectivity with respect to the plug when CMP of the plug is performed.

    (4) An insulating film.

  However, as described above, the third insulating film 4 (film 27 in the fourth embodiment) is composed of a silicon nitride film. This silicon nitride film has a large capacity, and it is desirable to remove it because it causes a delay of a signal propagating in the wiring.

  Therefore, in the fifth embodiment, first, when the fifth insulating film 7 is etched back, the etching time is slightly lengthened and formed on the side wall of the third insulating film 4 as shown in FIG. The fifth insulating film 7 is removed. Thereafter, the third insulating film 4 is removed by treatment with hot phosphoric acid, for example, as shown in FIG. According to this embodiment, the same effects as those of the first to fourth embodiments can be obtained, and the delay of the signal propagating through the wiring can be prevented. Thus, by removing the third insulating film, the conditions (3) and (4) are not necessary. Although the case of the silicon nitride film has been described in the above embodiment, a conductive film such as polysilicon may be used.

  FIG. 19 shows a sixth embodiment of the present invention. In the first to fifth embodiments, the third insulating film 4 is provided on the second insulating film 3. However, if the above conditions (1) and (2) are satisfied, the second insulating film 3 is formed. It is also possible to provide a conductive film. In the sixth embodiment, a polysilicon film 41 is provided on the second insulating film 3. Since the polysilicon film 41 has a large selection ratio with respect to the silicon oxide film, the wiring can be protected when the silicon oxide film 5 is etched as in the first to fourth embodiments. However, since the polysilicon film 41 has conductivity, it needs to be removed to avoid short circuit with other films.

  Therefore, first, as shown in FIG. 19A, the fifth insulating film 7 formed on the side wall of the polysilicon film 41 is removed in the same manner as in the fifth embodiment. Next, as shown in FIG. 19B, for example, a polysilicon film 42 is deposited on the entire surface. After that, as shown in FIG. 19C, the polysilicon films 41 and 42 are removed by the CMP method, and the contact holes are filled with the polysilicon film 42. At this time, the silicon oxide film 3 functions as a stopper. According to this embodiment, the same effect as that of the fifth embodiment can be obtained.

  FIG. 20 shows a seventh embodiment of the present invention and shows a modification of the sixth embodiment. In this embodiment, for example, a ruthenium film 43 is formed on the second insulating film 3, and then a ruthenium film 44 is deposited on the entire surface. Next, in order to process the electrode, the ruthenium film 44 is etched using a predetermined pattern, and the ruthenium film 43 is removed together with the etching.

  Both the film on the second insulating film 3 and the film deposited on the entire surface are ruthenium. For this reason, when processing the electrode, no problem occurs even if the pattern is slightly shifted as shown in FIG.

  Further, the material of the film on the second insulating film 3 is not limited to ruthenium, but satisfies the above conditions (1) and (2), and is made of, for example, a metallic material having the same quality as the film 44 deposited on the entire surface. Any film may be used.

  Of course, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows the 1st Example of this invention. Sectional drawing which shows the 2nd Example of this invention. The top view which shows the mask pattern applied to 3rd Example of this invention. FIG. 4 shows a third embodiment of the present invention and is a cross-sectional view taken along line 4-4 of FIG. A plan view showing a mask pattern applied to the fourth embodiment of the present invention. It is sectional drawing along the aa line of FIG. 5, and cc line | wire, and has shown the 1st process of the 4th Example. FIG. 6 is a cross-sectional view taken along lines aa and cc in FIG. 5, showing a second step following FIG. 6. FIG. 10 is a cross-sectional view taken along the lines aa and cc in FIG. 5, showing a third step following FIG. 7. FIG. 10 is a cross-sectional view taken along lines aa and cc in FIG. 5 and shows a fourth step following FIG. 8. FIG. 10 is a cross-sectional view taken along lines aa and cc in FIG. 5, showing a fifth step subsequent to FIG. 9. FIG. 10 is a cross-sectional view taken along line bb and line cc of FIG. 5 and shows a sixth step following FIG. 10. FIG. 10 is a cross-sectional view taken along line bb and line cc of FIG. 5 and shows a seventh step following FIG. 11. FIG. 13 is a cross-sectional view taken along line aa and dd in FIG. 5 and shows an eighth step following FIG. 12. FIG. 14 is a cross-sectional view taken along line aa and dd in FIG. 5 and shows a ninth step following FIG. 13. FIG. 15 is a cross-sectional view taken along line aa and dd in FIG. 5 and shows a tenth step following FIG. 14. FIG. 16 is a cross-sectional view taken along line aa and dd in FIG. 5 and shows an eleventh step following FIG. 15. FIG. 16 is a cross-sectional view taken along the lines aa and dd in FIG. 5 and shows a twelfth step following FIG. 16. Sectional drawing which shows 5th Example of this invention. Sectional drawing which shows the 6th Example of this invention. Sectional drawing which shows the 7th Example of this invention. The top view which shows the conventional memory cell. FIG. 22 is a cross-sectional view taken along line 22-22 in FIG. Sectional drawing which shows the problem of the conventional memory cell.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 2 ... Conductive film, 3 ... 2nd insulating film, 4 ... 3rd insulating film, 5 ... 4th insulating film, 7 ... 5th insulating film, 7a ... Side wall spacer, CH ... Contact hole, 8 DESCRIPTION OF SYMBOLS ... Wiring pattern, 9 ... Contact hole pattern, 13 ... N type polysilicon film, 14 ... Tungsten silicide film, 15 ... Silicon nitride film, 16 ... Source / drain diffused layer, 17 ... Silicon nitride film, 17a ... Side wall spacer, 21 ... N-type polysilicon film, 21a ... plug, 30 ... contact hole, 31 ... silicon oxide film, 31a ... sidewall spacer, 32 ... N-type polysilicon film, 32a ... plug, 33 ... ruthenium film, 34 ... BST film 35 ... ruthenium film 101 ... element isolation pattern 102 ... gate electrode pattern 103 ... plug pattern 104 ... bi DOO line contact pattern, 105 ... bit line pattern, 106 ... storage node contact pattern, 107 ... storage node electrode pattern, G ... gate electrode, BL ... bit lines, L ... wiring.

Claims (3)

Forming a first insulating film on the semiconductor substrate;
Forming a first conductor film on the first insulating film;
Forming a protective film on the first conductor film;
Etching the protective film and the first conductor film locally to form a plurality of wirings adjacent at a predetermined interval;
Forming a second insulating film on the entire surface, planarizing the second insulating film using the protective film as a stopper, and forming a second insulating film between the plurality of wirings;
A step of forming a photoresist using a contact pattern in a line / space form, the protective film on the plurality of wirings, and disposed on the second insulating film at a predetermined interval orthogonal to the plurality of wirings;
Etching the second insulating film and the first insulating film using the photoresist and the protective film as a mask to form a plurality of contact holes between the plurality of wirings;
Forming a third insulating film on at least a side wall of the first conductor film and a side wall of the first insulating film inside the plurality of contact holes;
Depositing a second conductor film on the entire surface;
Flattening the second conductor film using the protective film as a stopper and forming a plug in the plurality of contact holes. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the protective film is formed of a silicon nitride film, and the silicon nitride film is removed after the third insulating film is formed. The protective film is composed of one of a third conductor film and a metal-based film, and one of the third conductor film and the metal-based film is removed after forming the third insulating film. The method of manufacturing a semiconductor device according to claim 1.

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