JPH1022385A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent defective wirings such as short circuits at contact parts by forming an impurity-doped silicon oxide film on contact forming parts and removing this film by the vapor phase HF treatment to form contact holes. SOLUTION: An impurity-doped silicon oxide film 44 is formed on contact forming parts and undoped silicon oxide films 42, 43, 45 are formed on other parts. The doped film 44 is removed by the vapor phase HF treatment to form contact holes and conductive material is buried in the contact holes to form contacts. The doped silicon oxide film is formed e.g. by the ordinary pressure BPSG CVD. This self-alignedly forms the contact holes and hence at a high accuracy enough to avoid short circuits between the contact and other wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a contact connecting upper and lower layers and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, for example, demand for semiconductor storage devices has been rapidly expanding due to remarkable development and spread of information devices such as computers. Functionally, a device having a large storage capacity is required. Along with this, technology development for higher integration and higher reliability of semiconductor memory devices is being promoted. Among semiconductor memory devices, a DRAM is well known as a device capable of randomly inputting and outputting stored information. Generally, a DRAM includes a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input and output with the outside.

FIG. 10 is a block diagram showing a configuration of a general DRAM. In FIG. 1, a DRAM 1 includes a memory cell array 2 for storing data signals of storage information,
A row and column address buffer 3 externally receiving an address signal for selecting a memory cell constituting a storage circuit; a row decoder 4 and a column decoder 5 for specifying a memory cell by decoding the address signal; A sense refresh amplifier 6 for amplifying and reading the signal accumulated in the memory cell, a data-in buffer 7 and a data-out buffer 8 for inputting / outputting data, and a clock generator 9 for generating a clock signal.

In a memory cell array 2 occupying a large area on a semiconductor chip, a plurality of memory cells for storing stored information are arranged in a matrix. FIG. 11 is an equivalent circuit diagram showing four bits of the memory cells constituting the memory cell array. The illustrated memory cell is a so-called one-transistor one-capacitor type memory cell in which one MOS transistor 11 and one capacitor 12 connected thereto constitute one bit. The gate of the MOS transistor 11 is connected to a word line 13, one of a source and a drain is connected to a bit line 14, and the other is connected to a capacitor 12. This type of memory cell has a simple structure,
It is easy to improve the degree of integration of the memory cell array, and is often used in DRAMs requiring a large capacity.

FIGS. 12 to 15 are cross-sectional views showing steps of manufacturing a conventional typical memory cell having a stacked capacitor, showing two bits. First, referring to FIG. 12, after forming an isolation oxide film 22 on a silicon substrate 21, a gate oxide insulating film 23, a polysilicon film 24 doped with phosphorus and the like, and a silicon oxide film 25 are formed. 24, the word line 13 is patterned on the silicon oxide film 25. Then, an impurity such as phosphorus is ion-implanted to form the source / drain region 26. The transfer gate transistor (TG) is a word line 1 formed on a silicon substrate 21 with a gate oxide insulating film 23 interposed therebetween.
3 and a pair of source / drain regions 26 formed on the silicon substrate 21 on both sides thereof.

Next, a silicon oxide film is deposited on the entire surface of the silicon substrate 21 and anisotropically etched to form side walls 27 on the side walls of the word lines 13. And
After depositing a silicon oxide film 28 on the silicon substrate 21 and further applying a photoresist 29 thereon, patterning for the first contact hole 30 for connecting the bit line and the source / drain region 26 is performed by the photoresist. Then, anisotropic dry etching is performed using the photoresist 29 as a mask to form a first contact hole 30 as shown in FIG. 12, and the photoresist 29 is removed.

Next, referring to FIG. 13, a polysilicon film doped with phosphorus or the like is deposited to form a first contact 31, which is then patterned to form a bit line 14. Next, referring to FIG.
Is deposited, a second contact hole 33 for connecting the storage node to the source / drain region 26 is formed.
Is formed in the same manner as the first contact hole 30. Next, referring to FIG. 15, a second contact 34 is formed by depositing a polysilicon film, and is patterned to form storage node 15. Subsequently, a capacitor insulating film 35 and a cell plate electrode 16 are formed, and the capacitor 12 is constituted by these.

[0008]

In the future, in order to further increase the integration and capacity of the DRAM, the size of the memory cell must be reduced. Therefore, if the prior art is employed as it is, the first contact 31 and the word line 13
And the margin between the second contact 34 and the word line 13 and bit line 14 must be strict. Therefore, a defect occurs due to a short circuit between the first and second contacts 31 and 34, the word line 13 and the bit line 14. If the diameter of the contact hole is reduced in order to prevent this, the resolution of the resist becomes severe, and a defective opening of the contact hole occurs.

In order to solve the above problems, for example, there is a manufacturing method disclosed in Japanese Patent Application Laid-Open No. 3-183162, in which a silicon nitride film is used as an interlayer film. Since the silicon nitride film has a large stress, cracks and gaps are apt to occur in the interlayer film, which hinders the manufacturing process. In the dry etching of the contact hole, the selectivity of the silicon oxide film / nitride film including the inclined portion of the film is 10 or less, the controllability is severe, and the wiring is likely to be short-circuited.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of preventing a wiring defect such as a short circuit at a contact portion and a method of manufacturing the same.

[0011]

In a method of manufacturing a semiconductor device according to the present invention, a step of forming a silicon oxide film doped with an impurity in a contact formation portion and a step of forming a silicon oxide film not doped with an impurity in other portions are performed. A step of forming a film, a step of forming a contact hole by removing the impurity-doped silicon oxide film by a gas phase HF treatment, and a step of forming a contact by burying a conductive material in the contact hole. It is a thing.

Further, a gate oxide film on a silicon substrate,
A first conductive film and a first silicon oxide film not doped with an impurity are sequentially formed to pattern a word line, and a source / drain region is formed on both sides of the word line, and an impurity is formed on a side wall of the word line. Forming a first sidewall with an undoped silicon oxide film, depositing a second silicon oxide film doped with an impurity, and forming a second silicon oxide film in a portion other than the first and second contact formation portions And a third step of not doping impurities.
After depositing the silicon oxide film, etching back until the second silicon oxide film is exposed, applying a photoresist, and removing the photoresist on the first contact formation portion; Removing the second silicon oxide film in the contact formation portion by vapor phase HF processing to form a first contact hole, removing the photoresist, and depositing a second conductive film to form the first contact hole Is formed, a first contact is formed, and a fourth silicon oxide film not doped with impurities is deposited thereon,
Patterning a bit line to form a second sidewall with a silicon oxide film not doped with an impurity on a side wall; and removing the second silicon oxide film in a second contact formation portion by a gas phase HF process. The method includes a step of forming a second contact hole and a step of depositing a third conductive film and filling the second contact hole to form a second contact.

Further, the first and second silicon oxide films and the first sidewall are of the same film type having the same characteristics.

Further, the semiconductor device according to the present invention has the first
Conductive film, an insulating film formed thereon, a second conductive film formed thereon, a sidewall formed on a side wall of the first conductive film, and a side surface of the first conductive film A semiconductor device having a contact formed between the second conductive film and the lower conductive portion through a sidewall, the insulating film and the sidewall are formed of a silicon oxide film not doped with impurities, and And a step formed in a portion where the insulating film is in contact with the second conductive film.

Further, the insulating film and the side wall are of the same film type having the same characteristics. Further, the first conductive film is a word line, the second conductive film is a bit line, and the conductive portion is a source / drain region DRAM.
It is what it was. The first conductive film is a word line, the second conductive film is a bit line and a storage node insulated from each other, and the conductive portion is a DRAM which is two source / drain regions.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 6 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
The case where the present invention is applied to M memory cells will be described. The figure shows two bits. First, referring to FIG.
After an isolation oxide film 41 not doped with impurities is formed on 1 by selective oxidation, a gate oxide insulating film 23, a first polysilicon film 24 doped with phosphorus or the like as a first conductive film, and no impurities are doped. First silicon oxide film 42
Are sequentially formed. The first silicon oxide film 42 not doped with impurities is formed by low-pressure TEOS CVD (third and fourth silicon oxide films, and first and second sidewalls described later are also formed by the same method). The word line 13 (see FIG. 11) is patterned on the first polysilicon film 24 and the first silicon oxide film 42. Then, an impurity such as phosphorus is ion-implanted, and the source / drain region 26 is formed on both sides of the word line 13 (in the figure, since there are two word lines 13,
(The middle and both ends). Next, the silicon substrate 21
After a silicon oxide film not doped with impurities is deposited on the entire surface of these, anisotropic etching is performed to
A first side wall 43 is formed on the side wall of No. 3.

Subsequently, referring to FIG.
A second silicon oxide film 44 doped with impurities is deposited on the entire upper surface of the first silicon oxide film 1, and the second silicon oxide film 44 other than the first and second contact formation portions described later is subjected to photolithography and etching. To remove. The second silicon oxide film 44 doped with impurities is deposited at normal pressure BPSG CV
Perform at D. In the etching in this step, it is not necessary to stop at the interface with the underlying first silicon oxide film 42, and the first polysilicon film 24 is sufficiently over-etched.
May be used as a stopper. When dry etching is performed on the second silicon oxide film 44, a selectivity with respect to the first polysilicon film 24 of 40 or more can be secured. In this case, the gate electrode is a single layer of the first polysilicon film 24. However, if a high melting point metal such as W or WSi, silicide, or polycide is used in place of the gate electrode, the selectivity becomes equal to that of the single layer of the polysilicon film. The above values can be secured. In this step, it is important to perform over-etching until the second silicon oxide film 44 remaining in each contact formation portion is separated and isolated from each other. At this time, the isolation oxide film 41 may be shaved and the silicon substrate 2
1 may be exposed.

Next, referring to FIG. 3, after depositing a third silicon oxide film 45 containing no impurity, an isolated second silicon oxide film 45 is formed.
Etch back until the entire upper surface of the island of silicon oxide film 44 is exposed. At this time, etch back may be performed by anisotropic dry etching, or CMP (Chemical M
Etchback may be performed using an echanical polishing method.

Next, referring to FIG.
After applying 6, the photoresist 46 on the formation portion of the first contact 47 (see FIG. 5) for connecting the bit line 14 (see FIG. 11) and the source / drain region 26 is removed. At this time, the mask and the mask alignment are not particularly required since the second silicon oxide film 44 other than the portion where the first contact 47 is formed is not exposed. And
Second silicon oxide film 44 at the portion where photoresist 46 is removed
Is removed by a gas phase HF process to form a first contact hole 48, as shown in FIG. 4, and the remaining photoresist 46 is removed. As described in JP-A-6-196649, in the gas phase HF treatment, the etching rate of the silicon oxide film doped with impurities is about 1000 times faster than the oxide film not doped with impurities.
The second silicon oxide film 44 in the first contact 47 forming portion can be selectively removed, and the first contact hole 48 is formed.

Next, referring to FIG. 5, after depositing a second polysilicon film 49 as a second conductive film and a fourth silicon oxide film 50 not doped with impurities, patterning of bit lines 14 is performed. I do. Second polysilicon film 4
9 fills the first contact hole 48 to form a first contact 47. The bit line 14 is connected to the source / drain region 26 by the first contact 47. Subsequently, a silicon oxide film not doped with impurities is deposited on these entire surfaces, and the entire surface is etched back by anisotropic dry etching until the second silicon oxide film 44 is exposed, thereby forming a second sidewall 51. As shown in FIG. As described above, when the first and third silicon oxide films 42 and 45 are formed, the step A is formed. In other words, the insulating film on the first polysilicon film 24 is
By adopting a structure in which the step portion A is formed in a portion in contact with the polysilicon film, the above-described steps can be applied.

Next, referring to FIG. 6, a second contact hole 52 is formed by selectively removing second silicon oxide film 44 by vapor phase HF treatment. At this time, unlike the case shown in FIG. 4, no photoresist is required. Subsequently, a polysilicon film is deposited, the second contact hole 52 is buried to form a second contact 53, and the storage node 15 is patterned by performing patterning.
(See FIG. 11). At this time, the first and third silicon oxide films 42 and 4 on the first polysilicon film 24 are also formed.
5 forms a step B. The second contact 53 connects the storage node 15 and the source / drain region 26. Capacitor insulating film 5 on storage node 15
4 and a cell plate electrode 16 (see FIG. 11) is further formed thereon. The storage node 15, the capacitor insulating film 54, and the cell plate electrode 16 form the capacitor 12 (see FIG. 11).

As described above, since the first and second contact holes 48 and 52 are formed in a self-aligning manner, the first and second contact holes 48 and 52 can be formed accurately and easily. It will be easier. In addition, it is possible to prevent a short circuit between the contact and another wiring without reducing the diameter of the contact hole. In this embodiment, since the first and third silicon oxide films and the first side wall are made of the same film type having the same characteristics, the dry etching, the wet etching or the heat treatment in the later step can be performed. It does not cause a change in shape due to a difference in etch rate or reflow temperature, and the amount of etching is easily controlled.

Embodiment 2 FIG. In the first embodiment, the contact hole formation by the gas phase HF process is applied to both the bit line contact hole (the first contact hole 48) and the storage node contact hole (the second contact hole 52). Here, an example in which the present invention is applied to only the bit line contact hole is shown. 7 to 9 are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the second embodiment.
The case of a DRAM memory cell is shown.

First, referring to FIG. 7, an isolation oxide film 41, a gate oxide insulating film 23, and a first conductive film as a first conductive film are formed on a silicon substrate 21 in the same manner as described in the first embodiment. Polysilicon film 24, first silicon oxide film 4
2. The source / drain region 26 and the first sidewall 43 are formed. Normal pressure BPSG C
Second silicon oxide film 6 doped with impurities by VD
Then, N ₂ annealing at 700 to 1000 ° C. is performed to flatten the second silicon oxide film 61 by reflow. Subsequently, in order to form a first contact hole 64 (see FIG. 8), a photoresist 62 is applied, photolithography is performed, and the photoresist 62 other than the portion where the first contact hole 64 is formed is removed. , As shown in FIG.

Next, referring to FIG.
After etching the second oxide film 61 using the mask 2 as a mask, the photoresist 62 is removed. Subsequently, the third silicon oxide film 63 not doped with an impurity is removed by a reduced pressure TEO.
After the deposition by SCVD, the film is etched back and becomes as shown in FIG. Subsequently, a gas phase HF process is performed to selectively remove the second silicon oxide film 61 to form a first contact hole 64.

Next, referring to FIG. 9, a second polysilicon film 65 as a second conductive film is deposited to fill the first contact hole 64 to form a first contact 66 and to pattern the same. To form the bit line 14. At this time, a step portion C is formed on the first polysilicon film 24 at a portion where the first and third silicon oxide films 42 and 63 are in contact with the second polysilicon film. The first contact 66 is formed between the bit line 14 and the source / drain region 26.
Connect.

Subsequently, after a fourth silicon oxide film 67 is deposited on the entire upper surface, a second contact hole 68 for connecting the storage node 15 to the source / drain region 26 is formed in an anisotropic manner with photolithography. It is formed by reactive dry etching. A polysilicon film is deposited thereon to form a second
Of the second contact 6
9 and patterning is performed to form a storage node 15. Thereafter, the capacitor insulation 54 cell plate electrode 16 is formed in the same manner as in the first embodiment to configure the capacitor 12 (see FIG. 11). As described above, the first contact hole 64 is formed in a self-aligned manner as in the first embodiment.

In the above embodiment, the first silicon oxide film 42, the third silicon oxide films 45 and 63,
Although the silicon oxide film 50, the first side wall 43, and the second side wall 51 are formed of a TEOS oxide film, any other oxide film may be used as long as the silicon oxide film is not doped with impurities. In the above, an example in which the present invention is applied to a DRAM has been described, but an SRAM, an EPROM, an EEP
The present invention can be applied to other devices such as a ROM and a logic device, and achieves the same effect.

[0029]

According to the method of manufacturing a semiconductor device according to the present invention, a silicon oxide film doped with an impurity is formed in a contact hole forming portion, and then the silicon oxide film doped with the impurity is removed by a gas phase HF treatment to make contact. Since the holes are formed, the contact holes can be formed in a self-aligned manner. Therefore, a contact hole can be formed accurately and easily, a short circuit between a contact and another wiring can be prevented, and high integration can be facilitated. Further, by using an oxide film used as a silicon oxide film not doped with an impurity with the same film type having the same characteristics, a change in shape in etching or heat treatment in a later step is prevented, and the control of the etching amount is facilitated.

The semiconductor device according to the present invention has a first
The insulating film and the sidewalls on the conductive film are formed of a silicon oxide film not doped with impurities, and a step is formed in the insulating film. By performing the gas phase HF treatment on the substrate, the contact hole can be formed in a self-aligned manner, and therefore, the contact hole can be formed accurately and easily, and a short circuit between the contact and another wiring can be prevented. Further, by using the same film type having the same characteristics for the insulating film and the side wall, a shape change in a later step can be prevented, and the control of the etching amount can be easily performed. Furthermore, by applying to DRAM, DRA
M can be highly integrated.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device in the second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a DRAM.

FIG. 11 is an equivalent circuit diagram of a memory cell.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 15 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

13 word lines, 14 bit lines, 24 first polysilicon film, 42 first silicon oxide film, 43 first sidewall, 44 second silicon oxide film, 45
Third silicon oxide film, 46 photoresist, 47
First contact, 48 first contact hole, 4
9 second polysilicon film, 50 fourth silicon oxide film, 51 second sidewall, 52 second contact hole, 53 second contact, 61 second silicon oxide film, 63 third silicon oxide Film, 64 first contact holes, 65 second polysilicon film,
66 First contact.

Claims (7)

[Claims] In a method of manufacturing a semiconductor device having a contact connecting upper and lower layers, a step of forming a silicon oxide film doped with an impurity in a contact formation portion, and a portion where the silicon oxide film doped with the impurity is formed Forming a silicon oxide film not doped with an impurity in portions other than the above, forming a contact hole by removing the silicon oxide film doped with the impurity by vapor phase HF treatment, and forming a conductive material in the contact hole. Forming a contact by embedding the semiconductor device. 2. A first contact for connecting a bit line to one of the source / drain regions, and a second contact for connecting a storage node to the other of the source / drain regions.
In a method of manufacturing a semiconductor device having a contact of
A gate oxide film, a first conductive film, and a first silicon oxide film not doped with impurities are sequentially formed on a silicon substrate to pattern a word line, and impurities are implanted into the silicon substrate on both sides of the word line. Forming a source / drain region and forming a first sidewall with a silicon oxide film not doped with an impurity on a side wall of the word line, and thereafter, depositing a second silicon oxide film doped with an impurity. Removing the second silicon oxide film in portions other than the first and second contact formation portions, and then depositing a third silicon oxide film not doped with impurities, and then removing the second silicon oxide film. A step of etching back until the oxide film is exposed, and then applying a photoresist and removing the photoresist on the first contact formation portion Extent and, then, after the second silicon oxide film of the first contact forming portion to form a first contact hole is removed by gas-phase HF treatment,
Removing the photoresist, and then depositing a second conductive film, filling the first contact hole to form a first contact, and a fourth silicon oxide film not doped with impurities thereon And then forming a second sidewall with a silicon oxide film not doped with impurities on the side wall, and then forming a second silicon oxide film of the second contact formation portion on the side wall. A step of forming a second contact hole by removing by a gas phase HF treatment, and then depositing a third conductive film and filling the second contact hole to form a second contact hole;
Forming a contact according to claim 1. The method for manufacturing a semiconductor device according to claim 1, further comprising: 3. The first and third silicon oxide films and the first and third silicon oxide films.
3. The method according to claim 2, wherein the sidewalls are of the same film type having the same characteristics. 4. A first conductive film, an insulating film formed on the first conductive film, a second conductive film formed on the insulating film, and formed on a side wall of the first conductive film. And a contact formed on the side of the first conductive film via the side wall and connecting the second conductive film to a conductive portion formed below. 2. The semiconductor device according to claim 1, wherein the insulating film and the side wall are formed of a silicon oxide film not doped with an impurity, and a step is formed at a portion where the insulating film is in contact with the second conductive film. 5. The semiconductor device according to claim 4, wherein both the insulating film and the sidewall are of the same film type having the same characteristics. 6. The semiconductor device according to claim 1, wherein the first conductive film is a word line, the second conductive film is a bit line, and the conductive portion is a DRAM having memory cells as source / drain regions. Item 6. The semiconductor device according to item 4 or 5. 7. The first conductive film is a word line, the second conductive film is a bit line and a storage node insulated from each other, the conductive portion is two source / drain regions,
Two contacts connect the bit line and one of the source / drain regions, and the storage node and the other of the source / drain region, respectively, and have an insulating film in contact with the bit line and with the storage node. 6. The semiconductor device according to claim 4, wherein a portion is formed.