JP2008227524A - Manufacturing method of semiconductor device and production method of dram - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a leakage current between a gate electrode having a side-wall insulating film and an ohmic electrode opposite the gate electrode. <P>SOLUTION: A manufacturing method of the semiconductor device comprises the steps of forming the gate electrode 3 on a substrate 1 via a gate insulating film 2B, forming a diffusion area 1B in the substrate, forming the side-wall insulating film on the side wall of the gate electrode, depositing the insulating film on the gate electrode, forming a contact hole 5A for exposing the diffusion area surface out of the insulating film, treating the exposed diffusion area surface with an HF solution, forming an electrode so as to fill the contact hole, forming a memory cell capacitor electrically connected to a storage electrode 8A via the diffusion area and the electrode, and forming a nitride film 9 between the side-wall insulating film surface and the gate electrode side-wall surface, wherein the side-wall insulating film, the nitride film and the insulating film are exposed out of the side-wall surface of the contact hole. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and more particularly to a miniaturized semiconductor memory device and a method for manufacturing the same.

  With the progress of element miniaturization technology, the integration density of semiconductor integrated circuit devices, particularly memory integrated circuit devices, has been increasing year by year. Today, so-called sub-half micron devices with a minimum line width of 0.3 μm or less are energetically active. Has been studied.

  In a DRAM in which information is stored in a capacitor in an element in the form of electric charges, the miniaturization of the element causes a reduction in the capacitance of the capacitor, so that the retention of information in the capacitor or the read / write operation tends to become unstable. For this reason, great efforts have been made to stabilize the operation of a DRAM having a miniaturized capacitor. Similar problems occur in so-called flash memories that store information in floating gates.

  14A to 15F show a conventional DRAM manufacturing process.

Referring to FIG. 14A, a field oxide film 2A made of SiO ₂ is typically formed on a p-type doped Si substrate 1, and a thermal oxide film 2B made of SiO ₂ is also formed. A covered active region is formed, and a word line WL made of polysilicon extends on the substrate 1 covered with the field oxide film 2A or the thermal oxide film 2B. The word line WL extends on the thermal oxide film 2B on the active region and forms a gate electrode of the memory cell transistor. Accordingly, the thermal oxide film 2B forms a gate insulating film of the memory cell transistor.

Further, in the step of FIG. 14A, ion implantation of P ⁺ is performed using the gate electrode 3 as a self-aligned mask, and the diffusion regions 1A and 1B of the memory cell transistor are formed on both sides of the gate electrode 3 in the substrate 1. 1B is formed.

Next, in the step of FIG. 14B, an oxide film 4 made of SiO ₂ is deposited on the structure of FIG. 14A so as to cover the gate electrode 3 by a high temperature CVD method. In the step (C), anisotropic etching that acts on the oxide film 4 substantially perpendicularly to the main surface of the substrate 1 is performed by the RIE method, and sidewall oxidation that covers the sidewall of the gate electrode 3 is performed. Films 4A and 4B are formed. In the step of FIG. 14C, although not shown, P ⁺ ion implantation is further performed using the gate electrode 3 and the sidewall oxide films 4A and 4B as a self-aligned mask to form a so-called LDD (lightly doped drain) structure. It may be formed.

  Further, in the step of FIG. 15D, after depositing an interlayer insulating film 5 made of BPSG (borophosphosilicate) on the structure of FIG. 14C, a contact hole 5A exposing the diffusion region 1A is formed, Further, an electrode 6 is formed in contact with the diffusion region 1A through the contact hole 5A. However, the electrode 6 constitutes a part of the bit line.

  Further, in the step of FIG. 15E, another interlayer insulating film 7 made of BPSG is deposited on the structure of FIG. 15D, and the interlayer insulating films 7 and 5 are further penetrated to form the diffusion region. A contact hole 7A exposing 1B is formed.

  Finally, in the step of FIG. 15F, a storage electrode pattern 8A made of polysilicon is formed so as to fill the contact hole 7A, and an oxide film is formed on both sides of the SiN film on the storage electrode pattern 8A. A dielectric film 8B is formed. Further, a counter electrode 8C made of polysilicon is formed on the dielectric film 8B. The electrode pattern 8A, the dielectric film 8B, and the counter electrode 8C form a memory cell capacitor 8 that stores information in the form of electric charges.

  When miniaturization of an element is advanced in a DRAM having such a configuration, typically, a leakage current may flow between the storage electrode 8A and the gate electrode 3 when the minimum line width becomes 0.3 μm or less. It was discovered. Since the storage electrode 8A constitutes a part of the memory capacitor 8 that stores information in the form of electric charges as described above, the leakage current generated in the electrode 8A is serious in the operation of the DRAM, particularly in the data retention characteristics. Influence.

  FIG. 16A shows an enlarged part of the DRAM of FIG.

  Referring to FIG. 16A, the antireflection film 3A used in patterning the gate electrode 3 remains on the gate electrode 3, and the CVD is performed so as to cover the sidewall oxide films 4A and 4B. An oxide film 5B is formed between the interlayer insulating film 5. Further, the contact hole 5A is formed in a tapered shape whose diameter decreases from the top to the bottom in order to secure a distance from the gate electrode 3.

  However, in the DRAM having such a structure, the formation of the contact hole 5A in an ideal alignment state as shown in FIG. 16A is extremely miniaturized with a minimum line width of 0.3 μm or less. However, in reality, the position of the contact hole 5A often deviates from an ideal position as shown in FIG. 16B. In such a case, it is considered that the storage electrode 8A filling the contact hole 5A and the gate electrode 3 are close to each other, and a leak current flowing from the storage electrode 8A to the gate electrode 3 is generated. Details of the leakage current path are not well understood at present. As will be described later, the problem of this leakage current arises when etching with a buffered HF aqueous solution is performed in order to remove the natural oxide film from the surface of the diffusion region 1B, particularly when forming the storage electrode 8A. Become prominent.

  Accordingly, it is a general object of the present invention to provide a novel semiconductor device that solves the above-described problems and a method for manufacturing the same.

  A more specific object of the present invention is to provide a semiconductor device having a gate electrode and a method for manufacturing the semiconductor device capable of substantially removing a leakage current from the opposing electrode to the gate electrode. It is in.

  The present invention solves the above problems by forming a gate electrode on a substrate via a gate insulating film, forming a diffusion region in the substrate adjacent to the gate electrode, and sidewalls of the gate electrode. Forming a sidewall insulating film on the gate electrode; depositing an insulating film on the gate electrode on which the sidewall insulating film is formed; and exposing the diffusion region surface adjacent to the gate electrode on the insulating film. A step of forming a contact hole, a step of treating the surface of the diffusion region exposed to the contact hole with an HF solution, a step of forming an electrode so as to fill the contact hole, the diffusion region, and via the electrode Forming a memory cell capacitor electrically connected to the storage electrode, and forming a nitride film between the side wall insulating film surface and the gate electrode side wall surface It is solved by a method of manufacturing a semiconductor device according to claim in which the insulating film and the nitride film and the sidewall insulating film is exposed on the side wall surface of the contact hole.

  Further, the present invention has the above-described problems in that a step of forming a gate electrode on a substrate, a step of forming a pair of diffusion regions in contact with the gate electrode in the substrate, and a sidewall insulation on the sidewall surface of the gate electrode Forming a film; depositing an interlayer insulating film on the gate electrode on which the sidewall insulating film is formed; and a first contact hole exposing one of the pair of diffusion regions in the interlayer insulating film. A step of treating one surface of the pair of diffusion regions exposed to the first contact hole with an HF solution, a step of forming an electrode so as to fill the first contact hole, Forming a storage electrode of a memory cell capacitor electrically connected to one of the pair of diffusion regions via an electrode filling the first contact hole on the interlayer insulating film. Forming a nitride film between the surface of the sidewall insulating film and the sidewall surface of the gate electrode at least on the side facing the first contact hole, the sidewall insulating film, the nitride film, and the interlayer The problem is solved by the DRAM manufacturing method, in which the insulating film is exposed on the side wall surface of the first contact hole.

[Action]
FIG. 1 is a diagram for explaining the principle of the present invention. However, in FIG. 1, the parts described above are denoted by corresponding reference numerals, and the description thereof is omitted.

  Referring to FIG. 1, in the present invention, a SiN film 9 is formed so as to cover the upper surface (more precisely, the antireflection film 3A) of the gate electrode 3 and the side wall surface of the gate electrode, and the side wall oxide film 4B. Is formed on the SiN film 9. Further, the SiN film 9 extends on the thermal oxide film formed on the extension of the gate insulating film 2B from the side wall surface of the gate electrode 3 toward the contact hole 5A.

  With this configuration, the leakage current between the storage electrode 8A filling the contact hole 5A and the gate electrode 3 is efficiently suppressed.

  FIG. 2A shows the result of an experiment on the leakage current of the capacitor formed on the Si substrate 11.

Referring to FIG. 2A, a thick SiO ₂ film 12 is formed on the Si substrate 11 by, for example, a wet oxidation method, and a first polysilicon electrode pattern 13 is formed on the SiO ₂ film 12. It is formed. Further, on the SiO ₂ film 12, the to cover the polysilicon electrode pattern 13, the SiO ₂ film 14 is a high temperature CVD method, is deposited to a thickness of 50 nm, further a second polysilicon electrode thereon A pattern 15 is deposited.

  FIG. 2B shows the result of examining the leakage current characteristics of the structure of FIG. In FIG. 2B, the horizontal axis indicates the leakage current, and the vertical axis indicates the ratio of the number of samples in each leakage current.

In FIG. 2B, ● represents the results when the _second polysilicon electrode pattern 15 was formed immediately after the deposition of the SiO ₂ film 14 in the structure of FIG. In the structure of 2 (A), the result when the SiO ₂ film 14 is treated with a buffered HF aqueous solution before the electrode pattern 15 is formed is shown.

Referring to FIG. 2B, when the electrode pattern 15 is formed immediately after the formation of the SiO ₂ film 14, the leakage current is 10 ⁻⁷ A or less in most samples, whereas the SiO ₂ film 14 Is treated with a buffered HF aqueous solution, the thickness of the SiO ₂ film is reduced only by 4% from 50 nm to 48 nm, but the proportion of samples exhibiting a leak current of 10 ⁻⁷ amperes or more greatly increases. I can see that

  In the structure shown in FIG. 16A, FIG. 16B or FIG. 1, the natural oxide film is removed from the surface of the diffusion region 1B exposed by the contact hole 5A prior to forming the storage electrode 8A. Therefore, in general, the surface of the diffusion region is treated with the buffered HF aqueous solution. However, when such a treatment is performed, the leakage current characteristics between the electrode 8A and the electrode 3 are inevitably deteriorated. This is also supported by the results of FIG.

On the other hand, in the structure of FIG. 3A, a laminate in which a SiO ₂ film 16 and a SiN film 17 formed by a high temperature CVD method are laminated between the SiO ₂ film 14 and the upper polysilicon electrode pattern 15. The structure is interposed. However, in the structure of FIG. 3A, an etching process using a buffered HF aqueous solution is performed after the formation of the SiN film 17 and before the formation of the polysilicon electrode pattern 15.

FIG. 3B shows the leakage current characteristics of the structure of FIG. However, in FIG. 3B, when the thickness of the SiO ₂ film 16 is 10 nm and the thickness of the SiN film 17 is 6 nm, + is the thickness of both the SiO ₂ film 16 and the SiN film 17 is 10 nm. Shows the case. Further, ◯ shows the result of piercing the structure of FIG. 2A when the SiO ₂ film 16 and the SiN film 17 are not provided.

Referring to FIG. 3B, it is apparent that the leakage current characteristic is remarkably improved by forming the SiN film 17 on the SiO ₂ film 12 as compared with the case where the SiN film 17 is not formed. is there.

  That is, the result of FIG. 3B shows that the leakage current between the electrode 8A and the electrode 3 is effectively suppressed by forming the SiN film 9 in the structure of FIG.

  FIG. 4 illustrates yet another principle of the present invention. However, in FIG. 4, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 4, in the structure shown in the figure, another sidewall oxide film 4C is formed outside the sidewall oxide film 4B in the structure of FIG. 16A or 16B. Sidewall oxide film 4C is formed of a high temperature CVD method so as an SiO ₂ layer as in the case of the side wall oxide film 4B covering the gate electrode 3 and the side wall oxide film 4B, the formed substrate main surface with respect to the SiO ₂ layer are formed by performing anisotropic etching acting substantially perpendicularly against, time, the surface of the sidewall oxide film 4B that prior to deposition of the SiO ₂ layer has been formed, the SiO ₂ The surface is treated with N ₂ O at substantially the same temperature as the layer deposition temperature to form an N-doped region on the surface, as indicated by the hatched lines in FIG.

  Thus, the leakage current between the electrode 8A and the electrode 3 can also be suppressed by forming the sidewall oxide film in a multilayer structure. Such a multilayer structure is not limited to the two-layer structure including the sidewall oxide films 4B and 4C, and a larger number of layers may be stacked.

According to a feature of the invention,
A substrate, a gate electrode formed on the substrate, a sidewall insulating film covering the side wall surface of the gate electrode, a diffusion region formed in the substrate adjacent to the gate electrode, and formed on the diffusion region In such a semiconductor device comprising an ohmic electrode, SiN or SiON or the like is provided so as to cover at least a portion of the gate electrode surface facing the ohmic electrode between the sidewall insulating film surface and the gate electrode sidewall surface. By forming the nitride film, the leakage current between the ohmic electrode and the gate electrode can be effectively suppressed, and the data retention characteristics of the DRAM or flash memory are improved.

[First embodiment]
5A to 6G show a method of manufacturing a DRAM according to the first embodiment of the present invention.

Referring to FIG. 5A, a field oxide film 22A made of SiO ₂ is typically formed on a p-type doped Si substrate 21, and a thermal oxide film 22B also made of SiO ₂ is formed. A covered active region is formed, and a word line WL made of polysilicon extends on the substrate 21 covered with the field oxide film 22A or the thermal oxide film 22B. The word line WL extends on the thermal oxide film 22B on the active region, and forms the gate electrode 23 of the memory cell transistor. Accordingly, the thermal oxide film 22B forms a gate insulating film of the memory cell transistor.

Further, in the step of FIG. 5A, ion implantation of P ⁺ is performed using the gate electrode 23 as a self-alignment mask, and diffusion regions 21A, 21B is formed.

Next, in the step of FIG. 5B, the SiN film 24 is typically formed on the structure of FIG. 5A so that the SiN film 24 covers the upper surface and the side wall surface of the gate electrode 23 by, eg, CVD. Specifically, a SiO ₂ film 25 is deposited by a high temperature CVD method so as to cover the SiN film 24 in the step of FIG.

Next, in the step of FIG. 5D, anisotropic etching is performed on the SiO ₂ film 25 substantially perpendicularly to the main surface of the substrate, so that the sidewall oxide films 25A and 25B are formed on the gate. It is formed on both side wall surfaces of the electrode 23 via the SiN film 24. Further, in the step of FIG. 5D, P ⁺ ion implantation is performed using the gate electrode 23 and the sidewall oxide films 25A and 25B as a mask so as to partially overlap the diffusion regions 21A and 21B. Deep diffusion regions 21C and 21D are formed, respectively. Diffusion regions 21A and 21C or diffusion regions 21B and 21D form a so-called LDD (lightly doped drain) structure.

  Next, in the step of FIG. 6E, an interlayer insulating film 26 made of BPSG is deposited on the structure of FIG. 6D by the CVD method, and the diffusion regions 21A and 21C are further formed in the interlayer insulating film 26. A contact hole 26A that exposes is formed. Further, after removing the natural oxide film from the surface of the diffusion region exposed by the buffered HF aqueous solution, an ohmic electrode 27 forming a part of the bit line BL is formed on the interlayer insulating film 26 so as to fill the contact hole 26A. To do.

  Further, in the step of FIG. 6F, a second interlayer insulating film 28 made of BPSG is deposited on the structure of FIG. 6E by the CVD method, and further penetrates the interlayer insulating films 26 and 28. Then, a contact hole 28A exposing the diffusion region 21B (and 21D) is formed.

Further, in the step of FIG. 6G, after the natural oxide film on the surface of the diffusion region exposed by the contact hole 28A is removed by etching with a buffered HF aqueous solution, the memory cell capacitor is accumulated so as to fill the contact hole 28A. A polysilicon electrode 29 constituting an electrode is formed in contact with the diffusion regions 21B and 21D, a capacitor dielectric film 30 made of SiN is further formed thereon, and a polysilicon electrode constituting a counter electrode is further formed thereon. 31 is formed. The capacitor dielectric film 30 preferably has a so-called ONO structure in which SiO ₂ films are formed on the upper and lower surfaces of a SiN film.

  In this structure, since the SiN film 24 is interposed between the polysilicon electrode 29 filling the contact hole 28A and the gate electrode 23, when the bit line electrode 27 or the storage electrode 29 is formed, the exposed diffusion region surface is exposed. Even when the natural oxide film is removed by etching with a buffered HF aqueous solution, the leakage current between the electrodes 29 and 23 is effectively suppressed. See the relationship in FIG. At this time, since the SiN film 24 is thin and extends on the thermal oxide film that forms the extension of the gate insulating film 22B, the diffusion region important for the operation of the semiconductor device is not distorted. The performance of the semiconductor device is not deteriorated by forming the SiN film.

  This embodiment is also effective for a DRAM having a so-called self-aligned contact structure in which the contact hole 28A is formed in a self-aligned manner by the side wall oxide films 25A and 25B (for example, see Japanese Patent Laid-Open No. 8-274278). is there.

[Second Embodiment]
FIGS. 7A to 8G show a flash memory manufacturing method according to the second embodiment of the present invention.

Referring to FIG. 7A, a field oxide film 42A made of SiO ₂ is typically formed on a p-type doped Si substrate 41, and a thermal oxide film 42B also made of SiO ₂ is formed. A covered active region is formed, and in the step of FIG. 7B, a polysilicon pattern 43 is formed on the thermal oxide film 42B so as to cover the active region. The thermal oxide film 42B functions as a tunnel oxide film of a flash memory to be formed, while the polysilicon pattern 43 constitutes a part of a floating gate.

  7C, a dielectric film 44 made of SiON is deposited so as to cover the upper surface and the side wall surface of the polysilicon pattern 43, and the polysilicon pattern 43 is further formed on the dielectric film. A polysilicon film 45 and a WSi film 46 are sequentially deposited so as to cover the substrate, and further patterned by the process of FIG. Gate electrode structures G1 and G2 are formed. However, in the gate electrode structures G1 and G2, the polysilicon layer 43 forms a floating gate electrode as described above, and the polysilicon layer 45 and the WSi layer 46 form a control electrode.

Further, in the step of FIG. 7C, P ⁺ or As ⁺ ions are implanted into the substrate 41 using the gate electrode structures G1 and G2 as a mask, thereby allowing diffusion regions 41A, 41B, 41C is formed.

Next, in the step of FIG. 8E, the SiO ₂ film 47 and the SiN film 48 are formed on the structure of FIG. 7D by a high temperature CVD method. However, the SiO ₂ film 47 and the SiN film 48 continuously cover the top surface and both side wall surfaces of the gate electrode structures G ₁ and G ₂ .

  Next, in the step of FIG. 7F, an interlayer insulating film 49 made of BPSG is deposited on the structure of FIG. 7E so as to fill the gate electrode structures G1 and G2, and the interlayer insulation is further formed. Contact holes 49A to 49C are formed in the film 49 to expose the diffusion regions 41A to 41C, respectively.

Further, after removing the natural oxide film from the surfaces of the diffusion regions 41A to 41C exposed by the contact holes 49A to 49C with a buffered HF aqueous solution, ohmic electrodes 50A to 50C are formed so as to fill the contact holes 49A to 49C. To do. The ohmic electrode 50A or 50C forms, for example, a part of the bit line BL, and the ohmic electrode 50B is connected to an erasing power source together with a corresponding ohmic electrode of another memory cell transistor. Further, the silicide layer 46 in the gate electrode structures G ₁ and G ₂ is connected to the word line as a part of the control electrode.

  In the flash memory having such a structure, since the gate electrode structures G1 and G2 are continuously covered with the SiN film 48, even if an ohmic electrode, for example, the electrode 50A is formed in the immediate vicinity of the floating gate electrode 43, the floating gate electrode 43 Therefore, no charge leaks to the electrode 50A, and stable information holding and writing / reading are possible.

[Modification]
FIGS. 9A and 9B show a modification of the embodiment in which the above-described SiN film is used for suppressing leakage current. However, in FIGS. 9A and 9B, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 9A shows a modification of the structure of FIG. 1, and instead of forming the SiN film 9 in contact with the sidewall surface of the gate electrode 3 as in the structure of FIG. 1, the sidewall oxide film 4B is formed. Formed on top. Also in this configuration, the SiN film 9 covers the side of the gate electrode 3 that faces the ohmic electrode 8A, and effectively suppresses the leakage current between the electrodes 8A and 8.

  9B, in the DRAM structure of FIG. 6G, instead of forming the SiN film 24 in contact with the sidewall surface of the gate electrode 23, the sidewall oxide films 25A and 25B are formed. Is formed to extend. Even in such a structure, the SiN film 24 covers the side of the gate electrode 23 that faces the storage electrode 29, and effectively suppresses the leakage current between the gate electrode 23 and the storage electrode 29.

[Third embodiment]
FIGS. 10A to 13I show a method of manufacturing a DRAM according to the third embodiment of the present invention.

Referring to FIG. 10A, a field oxide film 62A made of SiO ₂ is typically formed on a p-type doped Si substrate 61, and a thermal oxide film 62B also made of SiO ₂ is formed. A covered active region is formed, and a word line WL made of polysilicon extends on the substrate 61 covered with the field oxide film 62A or the thermal oxide film 62B. The word line WL extends on the thermal oxide film 62B on the active region, and forms the gate electrode 63 of the memory cell transistor. Accordingly, the thermal oxide film 62B forms a gate insulating film of the memory cell transistor.

Further, in the step of FIG. 10A, ion implantation of P ⁺ is performed using the gate electrode 63 as a self-aligned mask, and diffusion regions 61A and 61B of the memory cell transistor are formed on both sides of the gate electrode 63 in the substrate 1. 61B is formed.

Next, in the step of FIG. 10 (B), on the structure of Figure 10 (A), the SiO ₂ film 64 by a high temperature CVD method, as the SiO ₂ film 64 covers the upper surface and sidewall surfaces of the gate electrode 63 accumulate.

Next, in the step of FIG. 10C, anisotropic etching is performed on the SiO ₂ film 64 substantially perpendicularly to the main surface of the substrate, so that the sidewall oxide films 64A and 64B are formed on the gate. It is formed on both side walls of the electrode 63. Further, in the step of FIG. 10C, ion implantation of P + or As ⁺ is performed using the gate electrode 63 and the sidewall oxide films 64A to 64D as a mask so as to partially overlap the diffusion regions 61A and 61B. Then, deeper diffusion regions 61C and 61D are formed. Diffusion regions 61A and 61C or diffusion regions 61B and 61D form a so-called LDD (lightly doped drain) structure.

The anisotropic etching process of FIG. 10C is performed without taking out the substrate 61 outside the apparatus in the same deposition apparatus as that for depositing the SiO ₂ film 64, and further in the process of FIG. 11D. 10C is exposed to an N ₂ O atmosphere at the substrate temperature when the SiO ₂ film is formed by the high temperature CVD method in the deposition apparatus, and the surface of the sidewall oxide films 64A and 64B is doped with N. To do.

Further, in the step of FIG. 11E, a SiO ₂ film (not shown) is deposited on the structure of FIG. 11D by a high temperature CVD method, and this is further substantially formed on the main surface of the substrate 61. By performing anisotropic etching in a perpendicular direction, other side wall oxide films 64C and 64D are formed outside the side wall oxide films 64A and 64B, respectively.

In the step of FIG. 11E, P ⁺ or As ⁺ is further ion-implanted using the gate electrode 63 and the sidewall oxide films 64A, 64C, 64B, 64D as a mask so as to partially overlap the diffusion region 61A. Further, a deeper diffusion region 61D is formed so as to partially overlap the deeper diffusion region 61C and the diffusion region 61B.

  Next, in the step of FIG. 12F, an interlayer insulating film 65 made of, for example, BPSG is deposited on the structure of FIG. 11E by the CVD method, and the diffusion region 61A and the interlayer insulating film 65 are deposited in the interlayer insulating film 65. A contact hole 65A exposing 61C is formed. Further, after removing the natural oxide film from the surface of the diffusion region exposed by the buffered HF aqueous solution, an ohmic electrode 66 forming a part of the bit line BL is formed on the interlayer insulating film 65 so as to fill the contact hole 65A. To do.

  Next, in the step of FIG. 12G, a second interlayer insulating film 67 made of, for example, BPSG is deposited on the interlayer insulating film 65 of FIG. 11E so as to fill the ohmic electrode 66. A contact hole 67A is formed through the first and second interlayer insulating films 65 and 67 to expose the diffusion regions 61B and 61D.

In this embodiment, in the step shown in FIG. 13H, dry cleaning using hydrogen plasma is performed on the exposed surfaces of the diffusion regions 61B and 61D through the contact holes 67A, and natural oxidation is performed. Remove the membrane. The dry cleaning is preferably performed at a temperature of about 200 ° C. by generating plasma by high frequency excitation in a gas mixture containing, for example, H ₂ and oxygen atoms, for example, H ₂ O. For example, see JP-A-6-140368.

After the dry cleaning, in the step of FIG. 13I, a polysilicon electrode 68 constituting a storage electrode of the memory cell capacitor is formed in contact with the diffusion regions 61B and 61D so as to fill the contact hole 67A. Further, a capacitor dielectric film 69 made of SiN is formed thereon, and a polysilicon electrode 70 constituting a counter electrode is further formed thereon. The capacitor dielectric film 69 preferably has a so-called ONO structure in which SiO ₂ films are formed on the upper and lower surfaces of a SiN film.

In this embodiment, the sidewall oxide film of the gate electrode 63 has a multilayer structure including a first layer made of the layer 61A or 61B and a second layer made of the layer 61C or 61D. Leakage current between the electrodes 63 can be effectively suppressed without using a nitride film. As described above, the surface of the first layer (layer 61A or 61B) is used in the high-temperature CVD method of the SiO ₂ film in an N ₂ O atmosphere before the formation of the second layer (layer 61C or 61D). Annealing is performed at the same temperature as the substrate temperature.

  Further, in this embodiment, as described with reference to FIG. 13I, prior to the deposition of the storage electrode 68, the natural oxide film on the surface of the exposed diffusion region is not etched with a buffered HF aqueous solution but with hydrogen. It is executed by dry cleaning in plasma. For this reason, the deterioration of the leakage current characteristic as in the case of performing the buffered HF aqueous solution treatment is suppressed.

  In the present embodiment, the configuration of the sidewall oxide film is not limited to the first layer and the second layer, but may have a structure including more layers.

  The dry cleaning is applied to the surface of the substrate 61 exposed through the contact hole 65A prior to forming the bit line electrode 66 in the step of FIG. The natural oxide film may be removed from the surface.

  The preferred features of the present invention have been described above. However, the present invention is not limited to such embodiments, and various modifications and changes can be made within the scope of the present invention.

  As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.

It is FIG. (1) explaining the principle of this invention. (A), (B) is a figure (the 2) explaining the principle of this invention. (A), (B) is a figure (the 3) explaining the principle of this invention. It is FIG. (4) explaining the principle of this invention. (A)-(D) are figures (the 1) explaining the manufacturing process of DRAM by 1st Example of this invention. FIGS. 6E to 6G are views (No. 2) for explaining the manufacturing process of the DRAM according to the first embodiment of the invention; FIGS. (A)-(D) is a figure (the 1) explaining the manufacturing process of the flash memory by 2nd Example of this invention. (E)-(G) is a figure (the 2) explaining the manufacturing process of the flash memory by 2nd Example of this invention. (A), (B) is a figure which shows the modification of 1st Example of this invention. (A)-(C) are the figures (the 1) explaining the manufacturing process of DRAM by 3rd Example of this invention. (D), (E) is a figure (the 2) explaining the manufacturing process of DRAM by 3rd Example of this invention. (F) and (G) are views (No. 3) for explaining the manufacturing process of the DRAM according to the third embodiment of the present invention; (H), (I) is a figure (the 4) explaining the manufacturing process of DRAM by 3rd Example of this invention. (A)-(C) is a figure (the 1) explaining the manufacturing process of the conventional DRAM. (D)-(F) is a figure (the 2) explaining the manufacturing process of the conventional DRAM. (A), (B) is a figure explaining the problem in the conventional semiconductor device.

Explanation of symbols

1, 11, 21, 41, 61 Substrate 1A, 1B, 21A, 21B, 21C, 21D, 41A, 41B, 41C, 61A, 61B, 61C, 61D Diffusion region 2A, 22A, 42A, 62A Field oxide film 2B, 22B , 62B Gate insulation film 3, 23, 63 Gate electrode 4, 5B, 14, 16, 25, 47, 64 SiO ₂ film 4A, 4B, 25A, 25B, 64A, 64B, 64C, 64D Side wall oxide films 5, 7, 26, 28, 49, 65, 67 Interlayer insulating film 5A, 7A, 26A, 28A, 49A, 49B, 49C, 65A, 67A Contact hole 6, 27, 66 Bit line electrode 8A, 29, 68 Storage electrode 8B, 30, 69 capacitor insulating film 8C, 31,70 counter electrode 9,17,24,48 nitride film 12 SiO ₂ layer 13, 15 polysilicon Electrode 42B tunnel insulating film 42 of polysilicon layer 44 floating insulating film 45 a polysilicon layer 46 WSi control electrodes 50A, 50B, 50C ohmic electrodes G _1, G ₂ gate electrode structure

Claims (19)

Forming a gate electrode on the substrate via a gate insulating film;
Forming a diffusion region in the substrate adjacent to the gate electrode;
Forming a sidewall insulating film on the sidewall of the gate electrode;
Depositing an insulating film on the gate electrode on which the sidewall insulating film is formed;
Forming a contact hole in the insulating film to expose the surface of the diffusion region adjacent to the gate electrode;
Treating the surface of the diffusion region exposed in the contact hole with an HF solution;
Forming an electrode to fill the contact hole;
Forming the diffusion region and a memory cell capacitor electrically connected to the storage electrode through the electrode;
Forming a nitride film between the sidewall insulating film surface and the gate electrode sidewall surface;
The method of manufacturing a semiconductor device, wherein the sidewall insulating film, the nitride film, and the insulating film are exposed on a sidewall surface of the contact hole.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of depositing the nitride film is performed so that the nitride film is in contact with the side wall of the gate electrode prior to the step of depositing the sidewall insulating film. Method.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed by a CVD method.   The gate insulating film is outside the gate electrode and has an extension on the diffusion region, and the extension is exposed to the contact hole, and the nitride is formed on the extension 4. The method of manufacturing a semiconductor device according to claim 1, wherein a film is formed.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the extending portion of the gate insulating film is formed of a thermal oxide film.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film is made of a SiN film or a SiON film.   The method for manufacturing a semiconductor device according to claim 1, wherein the sidewall insulating film has an etching resistance different from that of the nitride film.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film has etching resistance different from that of the nitride film.   The method of manufacturing a semiconductor device according to claim 1, wherein the contact hole is formed to have a tapered shape.   The method for manufacturing a semiconductor device according to claim 1, wherein a width of the gate electrode is 0.3 μm or less.   11. The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film has a thickness of at least 5 nm. Forming a gate electrode on the substrate;
Forming a pair of diffusion regions in contact with the gate electrode in the substrate;
Forming a sidewall insulating film on the sidewall surface of the gate electrode;
Depositing an interlayer insulating film on the gate electrode on which the sidewall insulating film is formed;
Forming a first contact hole in the interlayer insulating film to expose one of the pair of diffusion regions;
Treating one surface of the pair of diffusion regions exposed in the first contact hole with an HF solution;
Forming an electrode to fill the first contact hole;
Forming a storage electrode of a memory cell capacitor electrically connected to one of the pair of diffusion regions via an electrode filling the first contact hole on the interlayer insulating film;
Forming a nitride film between the side wall insulating film surface and the gate electrode side wall surface at least on the side facing the first contact hole,
A method of manufacturing a DRAM, wherein the sidewall insulating film, the nitride film, and the interlayer insulating film are exposed on a sidewall surface of the first contact hole.   13. The method of manufacturing a DRAM according to claim 12, wherein the step of forming the nitride film is performed so that the nitride film is in contact with the side wall surface of the gate electrode prior to the step of forming the sidewall insulating film. Method.   13. The method of manufacturing a DRAM according to claim 12, wherein the nitride film is formed so as to cover both side walls and an upper surface of the gate electrode.   The gate insulating film is outside the gate electrode, has an extension on one of the pair of diffusion regions, and the extension is exposed to the first contact hole; 15. The method for manufacturing a DRAM according to claim 12, wherein the nitride film is formed on the extending portion. Forming a second contact hole in the interlayer insulating film to expose the other of the pair of diffusion regions;
Forming an electrode to fill the second contact hole;
16. The bit line electrically connected to the other of the pair of diffusion regions via an electrode filling the second contact hole is formed on the interlayer insulating film. A method of manufacturing a DRAM according to any one of the above.   The nitride film is further formed between a surface of the sidewall insulating film and a side wall surface of the gate electrode on a side facing the second contact hole. A method for manufacturing a DRAM according to any one of the preceding claims.   19. The method of manufacturing a DRAM according to claim 12, wherein the gate electrode has a width of 0.3 [mu] m or less.   The method of manufacturing a DRAM according to claim 12, wherein the nitride film has a thickness of at least 6 nm.

Images