JP2006278935A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a breakdown voltage between a contact formed in a self-alignment process and a gate electrode. <P>SOLUTION: A recess 11a is formed in a side of laminated pattern B in which a gate structure A including at least a gate (polysilicon 8a) for controlling, a metal electrode 9a, and a hard mask 10a on a silicon substrate 1; and a side wall 13 is formed in the side of laminated pattern B so that it may be embedded. This can make the breakdown voltage between a contact 19 and the gate structure A improve since a spacing between the contact 19 and the metal electrode 9a becomes large compared with the case having no recess 11a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  With the miniaturization of semiconductor devices, the dimensions of elements are reduced, and the distance between the gate electrode and the contact is also reduced. Therefore, a contact (SAC) that can be formed in a self-aligned manner with respect to the gate electrode is widely used.

Here, an example of forming the above SAC will be described.
First, polysilicon and metal electrodes as gate electrodes having the same width are stacked on a substrate, and then a hard mask is sequentially stacked thereon to form a stacked pattern having flat side surfaces. Next, using this as a mask, a diffusion layer (source or drain) is formed on the surface of the substrate. Then, a sidewall made of a silicon nitride film or the like is formed on the side surface of the laminated pattern.
Further, an interlayer insulating film made of a silicon oxide film or the like is formed on the entire surface of the laminated pattern and the sidewall, and then the interlayer insulating film is etched using the hard mask and the sidewall as an etching stopper to perform self-alignment. A contact hole is opened to expose the surface of the substrate. Then, a metal film or the like is embedded in the contact hole to form a contact that is electrically connected to the diffusion layer on the surface of the substrate.

At this time, the breakdown voltage between the contact and the gate electrode depends on these intervals, and the breakdown voltage decreases as the interval decreases.
On the other hand, for example, when writing and erasing a cell in a flash memory, a high voltage of about 10 to 30 V is applied between the contact and the gate electrode. For this reason, a high breakdown voltage is required between them.

Therefore, in order to ensure a sufficient withstand voltage even when the distance between the contact and the gate electrode is reduced, a sidewall in which a silicon oxide film, a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order on the side surface of the gate electrode is provided. Measures have been taken (see, for example, Patent Document 1).
JP 2003-264247 A

The laminated pattern described above has a flat side surface, and the width of the sidewall formed on the side surface decreases as the distance from the substrate increases. Therefore, the distance between the metal electrode stacked on the polysilicon and the contact is smaller than the distance between the polysilicon and the contact, and there is a problem that the breakdown voltage between the gate electrode and the contact is lowered.
Further, the side wall in which a plurality of films are stacked as in the above-described conventional semiconductor device has a problem that the process is complicated because it is necessary to form a plurality of films.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of ensuring a high breakdown voltage between a contact and a gate electrode without complicating the process and a method for manufacturing the same. To do.

  A semiconductor device according to the present invention includes a substrate, a gate structure formed with a predetermined width on the substrate, and a gate structure stacked with a width smaller than the width of the gate structure, and both side surfaces of the gate structure. A metal electrode formed so as to be located on the inner side of the side surface position, and laminated on the metal electrode with a width larger than the width of the metal electrode, so that both side surfaces are located outside the side surface position of the metal electrode. A hard mask formed on the substrate, the gate structure, the metal electrode, and a sidewall formed on a side surface of the hard mask; and formed on the substrate, the sidewall, and the hard mask. An interlayer insulating film, a contact hole penetrating the interlayer insulating film, exposing the substrate on a bottom surface, and exposing the sidewall on a side surface, and the contact Characterized in that it comprises a contact conductive film is embedded inside the hole.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a stacked pattern having a flat side surface in which a gate structure, a metal electrode, and a hard mask are sequentially stacked on a substrate with substantially the same width; Removing a part of the metal electrode from the side surface of the substrate to form a depression on the side surface of the laminated pattern, forming a sidewall on the side surface of the laminated pattern having the depression formed on the substrate, and the substrate Forming an interlayer insulating film on the sidewall and the hard mask; and forming a contact hole penetrating the interlayer insulating film, exposing the substrate on a bottom surface, and exposing the sidewall on a side surface And a step of forming a contact in which a conductive film is embedded in the contact hole.

Another method for manufacturing a semiconductor device according to the present invention includes a step of sequentially forming a first conductive film, a metal film, and a hard mask film on a substrate, and selectively etching the hard mask film to form a predetermined one. Forming a hard mask having a width; and isotropically etching the metal film, the width of the hard mask so that both side surfaces of the metal film are located at positions inside the side surface position of the hard mask. A step of forming a metal electrode having a smaller width and the first conductive film are selectively etched so that both side surfaces of the first conductive film are positioned outside the side surface position of the metal electrode. Forming a gate structure having a width larger than the width of the metal electrode, and forming a sidewall on the side surface of the gate structure, the metal electrode, and the hard mask on the substrate. A step of forming an interlayer insulating film on the substrate, the sidewall, and the hard mask; a contact that penetrates the interlayer insulating film, exposes the substrate on a bottom surface, and exposes the sidewall on a side surface A step of forming a hole; and a step of forming a contact in which a second conductive film is embedded in the contact hole.
Other features of the present invention are described in detail below.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can ensure the high proof pressure between a contact and a gate electrode, and its manufacturing method can be obtained, without complicating a process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a semiconductor device (flash memory) according to an embodiment of the present invention. Actually, vias, wirings, and the like are formed thereon, but are omitted because they are not related to the essence of the present invention.
As shown in FIG. 1, a first gate insulating film 2a is formed on a silicon substrate 1, and a floating gate 3a having a predetermined width is formed thereon. Further, a silicon oxide film 4a, a silicon nitride film 5a, and a silicon oxide film 6a are stacked thereon (hereinafter, the silicon oxide film 4a, the silicon nitride film 5a, and the silicon oxide film 6a are collectively referred to as “second gate insulation”. Called membrane 7a).
A polysilicon 8a having a predetermined width is formed on the second gate insulating film 7a (hereinafter, the floating gate 3a, the second gate insulating film 7a, and the polysilicon 8a are collectively referred to as “gate structure A”). This is a structure including at least polysilicon 8a which is a control gate.) That is, on the silicon substrate 1, a gate structure A including at least a control gate (polysilicon 8a) in which a floating gate 3a, a second gate insulating film 7a, and a polysilicon 8a are sequentially stacked is formed with a predetermined width. Yes.

The metal electrode 9a is formed on the gate structure A so as to be stacked with a width smaller than that of the gate structure A, and the both side surfaces are located inside the side surface position of the gate structure A, respectively. Further, a hard mask 10a is formed on the metal electrode 9a so as to be laminated with a width larger than that of the metal electrode 9a, and both side surfaces are located outside the side surface position of the metal electrode 9a (hereinafter referred to as gate). A pattern in which the structure A, the metal electrode 9a, and the hard mask 10a are laminated is referred to as “lamination pattern B” as a whole).
As described above, the gate structure A, the metal electrode 9a, and the hard mask 10a are stacked, so that a recess 11a is formed on the side surface of the stacked pattern B.
On the silicon substrate 1, sidewalls 13 are formed on the side surfaces of the gate structure A, the metal electrode 9a, and the hard mask 10a so as to fill the recess 11a. That is, the sidewall 13 is formed on the side surface of the laminated pattern B.
Further, an interlayer insulating film 14a is formed on the silicon substrate 1, the sidewall 13, and the hard mask 10a.
A contact hole 16 is formed in a self-aligned manner, penetrating through the interlayer insulating film 14a, with the silicon substrate 1 exposed at the bottom and the sidewall 13 exposed at the side. At this time, the hard mask 10 a may be exposed at a part of the side surface of the contact hole 16.
Further, a TiN / Ti laminated film 17a and a metal film 18a are embedded as a conductive film inside the contact hole 16, and the source electrode (or drain electrode) of the source electrode (or drain electrode) electrically connected to the diffusion layer 12 on the surface of the silicon substrate 1 is embedded. A contact 19 (hereinafter simply referred to as “contact 19”) is formed.

Next, a method for manufacturing the semiconductor device will be described.
2 to 10 are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.
First, as shown in FIG. 2, a first gate insulating film 2 is formed on a silicon substrate 1. For example, the silicon substrate 1 is thermally oxidized by rapid thermal processing in an oxygen-containing atmosphere to form a silicon oxide film having a thickness of about 5 nm to 15 nm.

Next, a polysilicon film 3 which finally becomes a floating gate 3a (see FIG. 1) is formed on the first gate insulating film 2 by a chemical vapor deposition (hereinafter referred to as “CVD”) method to a thickness of 50 nm. It is formed with a film thickness of about 150 nm.
Further, a second gate insulating film 7 is formed on the polysilicon film 3 by sequentially laminating a silicon oxide film 4, a silicon nitride film 5, and a silicon oxide film 6.
For example, the surface of the polysilicon film 3 is rapidly heat-treated in an oxygen atmosphere to form a silicon oxide film 4 having a thickness of about 2 nm to 6 nm. Next, the surface of the silicon oxide film 4 is nitrided to form a silicon nitride film 5 having a thickness of about 5 nm to 15 nm. Then, the surface of the silicon nitride film 5 is rapidly heat-treated in an oxygen atmosphere to form a silicon oxide film 6 having a thickness of about 5 nm to 15 nm.

Next, a polysilicon film 8 is formed on the second gate insulating film 7 with a film thickness of about 50 nm to 150 nm by a CVD method (hereinafter, the polysilicon film 3, the second gate insulating film 7, and the polysilicon film 8). Is called “gate film A” as a whole).
Here, the gate film A is a film including at least a conductive film (polysilicon film 8) for forming a control gate.
Further, in order to reduce the resistance, a metal film 9 such as tungsten, which finally becomes the metal electrode 9a (see FIG. 1), is formed on the polysilicon film 8 with a film thickness of about 50 nm.
Further, a hard mask film 10 which finally becomes a hard mask 10 a (see FIG. 1) is formed on the metal film 9. For example, a silicon nitride film is formed with a thickness of about 200 nm to 300 nm by a low pressure CVD method.

Next, a resist pattern (not shown) is formed on the hard mask film 10 shown in FIG. 2 by lithography. Next, using this as a mask, the hard mask film 10, the metal film 9, and the gate film A shown in FIG. 2 are sequentially etched to form the hard mask 10a, the metal electrode 9a, and the gate structure A as shown in FIG. Form.
In this way, on the silicon substrate 1, a laminate having a flat side surface in which the gate structure A including at least the control gate (polysilicon 8a), the metal electrode 9a, and the hard mask 10a are sequentially laminated with substantially the same width. Pattern B is formed.

  Next, a part of the metal electrode 9a is removed from the side surface of the metal electrode 9a shown in FIG. This step is performed by oxidizing the side surface of the metal electrode 9a to form a metal oxide and then removing the metal oxide.

For example, the side surface of the metal electrode 9a is oxidized using a resist ashing device or the like, and the metal oxide 11 is formed on the side surface of the metal electrode 9a as shown in FIG.
For example, the metal oxide 11 having a desired width is formed by performing treatment at a temperature of about 200 ° C. for 5 minutes to 10 minutes in an atmosphere containing oxygen and nitrogen. Further, as shown in FIG. 5, the metal oxide 11 (see FIG. 4) is removed by a wet process such as water washing to form a recess 11 a on the side surface of the laminated pattern B.
Thus, the metal oxide 11 having a desired width is formed using an ashing apparatus, and the recess 11a having a desired width can be formed by removing the metal oxide 11. Thereby, the withstand voltage between the contact of the source electrode (or drain electrode) finally formed and the metal electrode 9a can be improved.
Further, ion implantation is performed using the laminated pattern B as a mask, and heat treatment is performed to form the diffusion layer 12 on the surface of the silicon substrate 1.

  Next, a silicon nitride film (not shown) is formed on the entire surface of the silicon substrate 1 shown in FIG. 5 and etched back on the entire surface, thereby forming a depression on the silicon substrate 1 as shown in FIG. Sidewalls 13 are formed on the side surfaces of the laminated pattern B on which 11a is formed. The silicon nitride film is formed to a thickness of about 50 nm to 100 nm by, for example, a low pressure CVD method so as to fill the recess 11a.

  Next, as shown in FIG. 7, an interlayer insulating film 14 is formed on the entire surface of the silicon substrate 1, the sidewalls 13, and the hard mask 10 a to a thickness of about 500 to 1000 nm by atmospheric pressure CVD or the like. Further, a resist pattern 15 is formed on the interlayer insulating film 14 by lithography.

Next, the interlayer insulating film 14 is etched using the resist pattern 15 shown in FIG. 7 as a mask, and as shown in FIG. 8, the silicon substrate 1 is exposed on the bottom surface through the interlayer insulating film 14a, and the side surface is exposed on the side surface. A contact hole 16 in which the wall 13 is exposed is formed by a self-aligned contact (hereinafter referred to as “SAC”) method. As a result, the contact hole 16 is formed in a self-aligned manner between the adjacent sidewalls 13.
At this time, the hard mask 10 a may be exposed at a part of the side surface of the contact hole 16.

Next, as shown in FIG. 9, a TiN / Ti laminated film 17 and a metal film 18 such as tungsten are formed on the entire surface so as to fill the inner surface of the contact hole 16.
Further, the TiN film 17 and the metal film 18 formed outside the contact hole 16 are removed by chemical mechanical polishing or the like. As a result, as shown in FIG. 10, a contact 19 in which the TiN / Ti laminated film 17a and the metal film 18a are embedded as a conductive film is formed on the inner surface of the contact hole 16.

Here, when the depression 11 a is not formed in the laminated pattern B, the width of the sidewall 13 decreases as the distance from the silicon substrate 1 increases. At this time, the distance between the metal electrode 9 a and the contact 19 is smaller than the distance between the gate structure A and the contact 19. Therefore, the breakdown voltage between the contact 19 and the metal electrode 9a is reduced.
However, as shown in FIG. 10, by forming the depression 11a on the side surface of the laminated pattern B and forming the sidewall 13 so as to fill it, the interval between the metal electrode 9a and the contact 19 can be increased. it can. Therefore, the breakdown voltage between the contact 19 and the metal electrode 9a can be improved as compared with the case where the depression 11a is not formed on the side surface of the laminated pattern B.

  In the present embodiment, an example is shown in which the gate structure A is a structure in which the floating gate 3a, the second gate insulating film 7a, and the polysilicon 8a are sequentially stacked. However, the same effect can be obtained even with a structure in which an insulating film is not interposed, such as a gate electrode of a DRAM (Dynamic Random Access Memory) or the like.

As described above, the semiconductor device according to the present embodiment includes the silicon substrate 1, the gate structure A including at least the control gate (polysilicon 8a) on the silicon substrate 1, and formed with a predetermined width. The metal electrode 9a is formed so as to be laminated with a width smaller than that of the gate structure A and so that both side surfaces are located inside the side surface position of the gate structure A.
On top of this, a hard mask 10a is formed having a width larger than the width of the metal electrode 9a and both side surfaces are located outside the side surface position of the metal electrode 9a, and a gate structure A on the silicon substrate 1. The sidewalls 13 are formed on the side surfaces of the metal electrode 9a and the hard mask 10a.
Further, an interlayer insulating film 14a formed on the silicon substrate 1, the sidewall 13, and the hard mask 10a, a contact hole 16 penetrating therethrough and exposing the silicon substrate 1 on the bottom surface and exposing the sidewall 13 on the side surface. Then, the contact 19 in which the metal film 18a is embedded is formed.
With such a structure, the breakdown voltage between the contact 19 and the metal electrode 9a can be improved as compared with the case where the depression 11a is not formed on the side surface of the multilayer pattern B.

Further, in the method of manufacturing the semiconductor device according to the present embodiment, the gate structure A including at least the control gate (polysilicon 8a), the metal electrode 9a, and the hard mask 10a are sequentially formed with the same width on the silicon substrate 1. After forming the laminated pattern B having the laminated flat side surface, a part of the metal electrode 9a was removed from the side surface of the metal electrode 9a to form the depression 11a on the side surface of the laminated pattern B. Then, the sidewall 13 is formed on the side surface of the laminated pattern B in which the depression 11a is formed on the silicon substrate 1.
Further, an interlayer insulating film 14 is formed on the silicon substrate 1, the sidewall 13, and the hard mask 10 a, and a contact hole 16 that penetrates the silicon substrate 1 and exposes the sidewall 13 on the side surface is formed. I tried to do it. Then, the contact 19 in which the metal film 18a is embedded in the contact hole 16 is formed.
In this way, the depression 11a having a desired width can be formed on the side surface of the multilayer pattern B, and the distance between the contact 19 and the metal electrode 9a can be increased. Thereby, the withstand voltage between the contact 19 and the metal electrode 9a can be improved.

Embodiment 2. FIG.
11 and 12 are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.
In the first embodiment, after forming the metal oxide 11 by oxidizing the side surface of the metal electrode 9a with an ashing device, as shown in FIGS. An example of removing this has been described.
The manufacturing method of the semiconductor device according to the present embodiment is replaced with the above-described method. As shown in FIG. 11, the side surfaces of the metal electrode 9a and the gate structure A are oxidized, and the side surface of the metal electrode 9a is metal oxide. 11 and the silicon oxide film 20 are formed on the side surfaces of the gate structure A.
At this time, the entire metal electrode 9a is formed by using selective oxidation conditions in a mixed gas atmosphere such as hydrogen and oxygen in which the reduction action acts strongly on the metal electrode 9a and the oxidation action acts strongly on the gate structure A. The side surfaces of the metal electrode 9a are oxidized to such an extent that they are not sublimated.
After that, the metal oxide 11 shown in FIG. 11 is removed by wet treatment such as washing with water to form a recess 11a on the side surface of the laminated pattern B as shown in FIG.

By forming in this way, the recess 11a can be formed on the side surface of the laminated pattern B, as in the first embodiment.
Further, simultaneously with the step of forming the metal oxide 11 on the side surface of the metal electrode 9a, the silicon oxide film 20 can be formed on the side surface of the gate structure A. Thereby, when the damage recovery process on the silicon substrate 1 generated when the gate structure A is etched is necessary, the process can be performed simultaneously with the process of forming the metal oxide 11. It can be simplified.
Since other configurations are the same as those in the first embodiment, description thereof is omitted.

As described above, the method for manufacturing a semiconductor device according to the present embodiment oxidizes the metal electrode 9a and the side surface of the gate structure A in the step of forming a recess in the side surface of the stacked pattern B shown in the first embodiment. Then, the metal oxide 11 was formed on the side surface of the metal electrode 9a, and the silicon oxide film 20 was formed on the side surface of the gate structure A, and then the metal oxide 11 was removed.
Thereby, in addition to the effect of the first embodiment, when a damage recovery process on the silicon substrate 1 that occurs when the gate structure A is etched is necessary, the process forms the metal oxide 11. It can be performed simultaneously with the process, and the process can be simplified.

Embodiment 3 FIG.
In the method of manufacturing the semiconductor device according to the present embodiment, the step of forming the depression 11a on the side surface of the multilayer pattern B described in the first embodiment is performed by wet etching the side surface of the metal electrode 9a shown in FIG. Like that.
For example, when the metal electrode 9a is tungsten, an aqueous solution of ammonia hydrogen peroxide (NH ₄ OH) that can dissolve the metal electrode 9a (APM; Ammonium Hydroxide / Hydrogen Peroxide / Water Mixture) is used, and the treatment time is adjusted appropriately. Then, wet etching is performed. For example, treatment is performed at 23 ° C. for 500 seconds to 1500 seconds using an APM of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 200. Thereby, as shown in FIG. 5, the depression 11 a can be formed on the side surface of the laminated pattern B.

By forming in this way, the recess 11a can be formed on the side surface of the laminated pattern B, as in the first embodiment.
Furthermore, since the depression 11a can be formed on the side surface of the laminated pattern B only by chemical chemical wet etching, the step of forming the metal oxide 11 (see FIG. 4) can be omitted as compared with the first embodiment, and the process is simplified. can do.
Since other configurations are the same as those in the first embodiment, description thereof is omitted.

As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the step of forming the depression 11a on the side surface of the multilayer pattern B shown in the first embodiment is performed by wet etching the side surface of the metal electrode 9a. I did it.
By forming in this way, the depression 11a can be formed on the side surface of the laminated pattern B only by wet etching of the chemical solution. Therefore, in addition to the effects of the first embodiment, the process can be simplified as compared with the first embodiment.

Embodiment 4 FIG.
13 to 15 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment.
First, as shown in FIG. 2, the steps from the step of forming the first gate insulating film 2 on the silicon substrate 1 to the step of forming the hard mask film 10 are performed in the same manner as in the first embodiment.
In this way, the first gate insulating film 2, the gate film A (first conductive film) including the conductive film (polysilicon film 8) for forming at least the control gate on the silicon substrate 1, the metal film 9 And the hard mask film 10 are sequentially formed.

  Thereafter, as shown in FIG. 13, the hard mask film 10 is selectively etched using the resist pattern 19 formed on the hard mask film 10 (see FIG. 2) as a mask to form a hard mask 10a having a predetermined width. To do. Thereafter, although not shown, the resist pattern 19 is removed.

Next, as shown in FIG. 14, the metal film 9 (see FIG. 13) is isotropically etched so that both side surfaces of the metal film 9 are positioned inside the side surface position of the hard mask 10 a. A metal electrode 9a having a width smaller than that of the hard mask 10a is formed.
For example, when the metal film 9 is tungsten, isotropic etching is performed by increasing the CF ₄ gas flow rate.

Next, as shown in FIG. 15, the gate film A (see FIG. 14) is selectively etched, so that both side surfaces of the gate film A (first conductive film) are positioned outside the side surface position of the metal electrode 9a. The gate structure A including at least the control gate (polysilicon 8a) and having a width larger than the width of the metal electrode 9a is formed.
Although not shown, sidewalls are formed on the side surfaces of the gate structure A, the metal electrode 9a, and the hard mask 10a on the silicon substrate 1 by the same method as in the first embodiment.

In this process of etching the metal film 9 to form the metal electrode 9a, by performing isotropic etching, the depression 11a can be formed on the side surface of the laminated pattern B as in the first embodiment.
Furthermore, by setting the etching condition of the metal film 9 to isotropic etching, the depression 11a can be formed on the side surface of the laminated pattern B, so that the process can be simplified as compared with the first embodiment.
Since other configurations are the same as those in the first embodiment, description thereof is omitted.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, first, the gate film A including the conductive film (polysilicon film 8) for forming at least the control gate on the silicon substrate 1, The metal film 9 and the hard mask film 10 were sequentially formed, and the hard mask film 10 was selectively etched to form a hard mask 10a having a predetermined width.
Next, the metal film 9 is isotropically etched, and the metal electrodes 9a having a width smaller than the width of the hard mask 10a are arranged so that both side surfaces of the metal film 9 are positioned inside the side surface position of the hard mask 10a. To form. Then, the gate film A (first conductive film) is selectively etched so that at least the control gate (polysilicon) is positioned so that both side surfaces of the gate film A are positioned outside the side surface position of the metal electrode 9a. A gate structure A including silicon 8a) and having a width larger than that of the metal electrode 9a is formed.
Next, sidewalls are formed on the side surfaces of the gate structure A, the metal electrode 9a, and the hard mask 10a on the silicon substrate 1. Then, an interlayer insulating film 14 is formed on the silicon substrate 1, the sidewall 13, and the hard mask 10 a, and a contact hole 16 that penetrates the silicon substrate 1 on the bottom surface and exposes the sidewall 13 on the side surface is formed. It was made to form. Further, the contact 19 in which the metal film 18a (second conductive film) is embedded in the contact hole 16 is formed.

  In this way, by setting the etching condition of the metal film 9 to isotropic etching, the depression 11a can be formed on the side surface of the multilayer pattern B. Therefore, in addition to the effects of the first embodiment, the process can be simplified as compared with the first embodiment.

Sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Silicon substrate, 2a 1st gate insulating film, 3a floating gate, 7a 2nd gate insulating film, 8a polysilicon, 9a metal electrode, 10a hard mask, 11a hollow, 12 diffused layer, 13 sidewall, 14a interlayer insulating film, 16 contact holes, 17a TiN / Ti laminated film, 18a metal film, 19 contacts, A gate structure (or gate film), B laminated pattern.

Claims (5)

A substrate,
A gate structure formed with a predetermined width on the substrate;
A metal electrode stacked on the gate structure with a width smaller than the width of the gate structure, and having both side surfaces located inside the side surface position of the gate structure;
A hard mask laminated on the metal electrode with a width larger than the width of the metal electrode, and formed so that both side surfaces are respectively located outside the side surface position of the metal electrode;
A sidewall formed on a side surface of the gate structure, the metal electrode, and the hard mask on the substrate;
An interlayer insulating film formed on the substrate, the sidewall, and the hard mask;
A contact hole penetrating the interlayer insulating film, exposing the substrate on a bottom surface, and exposing the sidewall on a side surface;
A contact in which a conductive film is embedded in the contact hole;
A semiconductor device comprising: Forming a laminated pattern having a flat side surface in which a gate structure, a metal electrode, and a hard mask are sequentially laminated with substantially the same width on a substrate;
Removing a part of the metal electrode from the side surface of the metal electrode to form a depression on the side surface of the laminated pattern;
Forming a sidewall on a side surface of the laminated pattern in which the depression is formed on the substrate;
Forming an interlayer insulating film on the substrate, the sidewall, and the hard mask;
Forming a contact hole penetrating the interlayer insulating film, exposing the substrate on the bottom surface, and exposing the sidewall on the side surface;
Forming a contact with a conductive film embedded in the contact hole;
A method for manufacturing a semiconductor device, comprising:   3. The method according to claim 2, wherein the step of forming the depression on the side surface of the laminated pattern is performed by oxidizing the side surface of the metal electrode to form a metal oxide and then removing the metal oxide. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming the depression on the side surface of the stacked pattern is performed by wet etching the side surface of the metal electrode. Sequentially forming a first conductive film, a metal film, and a hard mask film on a substrate;
Selectively etching the hard mask film to form a hard mask having a predetermined width;
Forming the metal electrode having a width smaller than the width of the hard mask so that both side surfaces of the metal film are positioned at positions inside the side surface of the hard mask by isotropic etching. When,
The first conductive film is selectively etched to have a width larger than the width of the metal electrode so that both side surfaces of the first conductive film are positioned outside the side surface position of the metal electrode. Forming a gate structure;
Forming sidewalls on side surfaces of the gate structure, the metal electrode, and the hard mask on the substrate;
Forming an interlayer insulating film on the substrate, the sidewall, and the hard mask;
Forming a contact hole penetrating the interlayer insulating film, exposing the substrate on the bottom surface, and exposing the sidewall on the side surface;
Forming a contact in which a second conductive film is embedded in the contact hole;
A method for manufacturing a semiconductor device, comprising:

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