JP2008098480A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which prevents the generation of film stress in a stopper nitride film used for forming a contact hole by using a SAC technology. <P>SOLUTION: A resist material having etching selectivity in the etching of a silicon nitride film is applied to a semiconductor substrate 1 so as to cover a gate electrode 100 including a sidewall nitride film 52 and exposure treatment and development treatment are performed. By the exposure treatment and the development treatment, a resist film 6 is buried between the gate electrodes 100, a stopper nitride film 53 is exposed to the upper part of the gate electrode 100 and the stopper nitride film 53 of other parts, especially a source-drain part, is covered with the resist film 6. Then the exposed stopper nitride film 53 on the upper part of the gate electrode 100 is removed by dry etching. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a self-aligned contact technique.

  When a contact hole is opened using a self-aligned contact (SAC) technique in forming a memory cell, a side wall of a silicon nitride film is formed after forming a gate electrode, and then a silicon nitride film is further used as an etching stopper. A structure in which a film is formed is generally used.

  This is because if the silicon nitride film for the etching stopper (stopper nitride film) does not exist, the etching selectivity between the interlayer oxide film and the element isolation oxide film when the contact hole is engaged with the element isolation oxide film due to misalignment. This is because there is a possibility that the element isolation oxide film is largely etched by the contact hole etching.

  As described above, the stopper nitride film in the SAC technique is very important in terms of increasing the processing margin of the etching process, but has a problem in the sense that film stress occurs.

  That is, after the silicon nitride film is formed, an interlayer oxide film is formed in a state where the semiconductor substrate is covered with the silicon nitride film. In order to embed the interlayer oxide film without a gap between the gate electrodes, the interlayer oxide film is formed. It is necessary to perform high temperature heat treatment (reflow) after film formation. At this time, a large film stress is generated in the stopper nitride film.

  It has been confirmed that the film stress of the stopper nitride film greatly deteriorates the film quality of the gate oxide film of the transistor. For example, in flash memory, it affects the quality of the tunnel oxide film of the floating gate type transistor, and the flash memory performance, for example, flash memory erase resistance (characteristic that suppresses prolonged data erasure due to aging) and write resistance. There is a possibility that the retention characteristic (data retention characteristic) may be deteriorated (characteristic for suppressing a long time for data writing due to secular change).

  In Patent Documents 1 and 2, stress may occur in a later thermal process due to a difference in expansion coefficient between the silicon nitride film formed on the MOS transistor and the silicon oxide film formed thereon. Recognized as an issue.

Japanese Patent Laid-Open No. 2-137234 JP-A-5-206056

  As described above, when the contact hole is opened using the SAC technique, the sidewall of the silicon nitride film is formed, and the stopper nitride film is further formed thereon, and the stopper nitride film is formed on the stopper nitride film. Due to the difference in material from the formed interlayer oxide film, there has been a problem that a large film stress is generated in the stopper nitride film due to the high-temperature heat treatment after the interlayer oxide film is formed.

  The present invention has been made to solve the above-described problems, and a semiconductor in which film stress is prevented from occurring in a stopper nitride film used when a contact hole is opened using SAC technology. An object is to provide a method for manufacturing a device.

  In one embodiment according to the present invention, the following manufacturing method is presented. That is, a resist material is applied on the semiconductor substrate 1 so as to cover the gate electrode including the sidewall nitride film, and an exposure process and a development process are performed. By this exposure process and development process, a valley portion between the gate electrodes is filled with a resist film (embedded film). A stopper nitride film is exposed at the upper part of the gate electrode, and the other portions, particularly the stopper nitride films in the source / drain portions are covered with a resist film. Thereafter, the stopper nitride film on the exposed gate electrode is removed by dry etching.

  According to the above embodiment, since the stopper nitride film is removed from the upper part of the gate electrode, the stopper nitride film is divided at the upper part of the gate electrode.

  For this reason, even when reflow is performed after the formation of the interlayer oxide film, the stress applied to the stopper nitride film is alleviated due to the difference in material between the stopper nitride film and the interlayer oxide film, and the stress affects the film quality of the tunnel oxide film. Is prevented from affecting the performance of the flash memory.

  The term “MOS” has been used in the past for metal / oxide / semiconductor laminated structures, and is taken from the acronym Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials for a gate insulating film and a gate electrode have been improved from the viewpoint of recent integration and improvement of a manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of the common general knowledge, “MOS” is not only an abbreviation derived from the word source, but also has a meaning including widely a laminated structure of a conductor / insulator / semiconductor.

<A. Embodiment 1>
As a method of manufacturing the semiconductor device according to the first embodiment of the present invention, a manufacturing process of a flash memory having a floating gate type MOS transistor will be described with reference to FIGS. 1 to 8, the cross section in the gate length direction of the floating gate type MOS transistor shown by the AA line in FIG. 9 is shown as the gate portion, and the gate width of the source / drain layer shown by the BB line. A cross section in the direction is shown as a source / drain portion.

<A-1. Manufacturing process>
First, in the process shown in FIG. 1, a semiconductor substrate 1 such as a silicon substrate is prepared, and a floating gate type MOS transistor is formed on the semiconductor substrate 1.

  The floating gate type MOS transistor is formed by a well-known technique. For example, first, a silicon oxide film having a thickness of about 11 nm is formed on the entire surface of the semiconductor substrate 1 by, for example, lamp oxidation to form a tunnel oxide film 22. And Lamp oxidation is an oxidation technique that performs rapid thermal annealing (RTA) while supplying oxygen.

  Next, a non-doped polysilicon film having a thickness of about 120 nm is formed on the tunnel oxide film 22 by, for example, a CVD (Chemical Vapor Deposition) method, and then impurities such as phosphorus are ion-implanted. A floating gate 31 is formed by photolithography and dry etching of this polysilicon film.

  Next, an ONO film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked is formed on the floating gate 31 to form an intergate insulating film 7 having a thickness of about 10 nm.

  The ONO film can be obtained, for example, by forming a central silicon nitride film by a CVD method and forming upper and lower silicon oxide films by ISSG (In Situ Steam Generation) oxidation using active oxygen. ISSG oxidation is performed by Applied Materials, Inc. This is an oxidation technology provided by the company.

  Next, a doped polysilicon film having a thickness of about 80 nm is formed on the inter-gate insulating film 7 by, for example, a CVD method to form the control gate 32. When forming the doped polysilicon film, a polysilicon layer containing impurities is obtained by performing film formation while supplying a gas containing impurities such as phosphorus.

  Next, a tungsten silicide (WSi) film 4 having a thickness of about 80 nm is obtained on the control gate 32 by, eg, CVD.

  Next, a silicon oxide film having a thickness of about 10 nm is formed on the tungsten silicide film 4 by using, for example, TEOS (tetraethyl orthosilicate) by a CVD method to form a hard mask 23.

  Next, a silicon nitride film having a thickness of about 270 nm is formed on the hard mask 23 by, for example, a CVD method to form the hard mask 51.

  Thereafter, the hard masks 51 and 23, the tungsten silicide film 4, the control gate 32, the intergate insulating film 7 and the floating gate 31 are patterned by, for example, dry etching to obtain the gate electrode 100.

  Thereafter, ISSG oxidation is further performed to form a silicon oxide film on the surface of the gate electrode 100 to form the sidewall oxide film 10.

  Since ISSG oxidation also oxidizes the surface of the silicon nitride film, a silicon oxide film is also formed on the surface of the hard mask 51, but the thickness is formed on the surfaces of the control gate 32 and the floating gate 31 made of polysilicon. Although it is thinner than the silicon oxide film, such a slight difference is not shown in the drawing.

  Thereafter, impurity ions are implanted using the gate electrode 100 as an implantation mask, and the source / drain layer 11 is formed outside the side surface of the gate electrode 100 in the gate length direction.

  Subsequently, a silicon nitride film having a thickness of about 60 nm is formed on the semiconductor substrate 1 by, for example, the CVD method to cover the gate electrode 100, and then anisotropic etching is performed to form sidewall nitriding on the side surface of the gate electrode 100. By forming the film 52, a floating gate type MOS transistor is obtained.

  As shown in FIG. 1, in the source / drain portion, a source / drain layer 11 is formed in a region defined by an element isolation oxide film 21 formed in the surface of the semiconductor substrate 1, and the source / drain layer is formed. 11, a tunnel oxide film 22 is formed.

  After forming the floating gate type MOS transistor, in the step shown in FIG. 2, a silicon nitride film having a thickness of about 15 nm is formed on the upper surface of the semiconductor substrate 1 by, for example, the CVD method, and a silicon nitride film (stopper nitridation) for an etching stopper is formed. Film) 53.

  The stopper nitride film 53 is also formed in the source / drain portions and covers the element isolation oxide film 21 as well.

  Next, a resist material having etching selectivity with respect to the etching of the silicon nitride film is applied on the semiconductor substrate 1 so as to cover the gate electrode 100 including the sidewall nitride film 52, and an exposure process and a development process are performed. Do.

  By this exposure process and development process, as shown in FIG. 3, the valley portion between the gate electrodes 100 is buried with the resist film 6 (embedded film), and the stopper nitride film 53 is exposed above the gate electrode 100, A structure is obtained in which the stopper nitride film 53 in other portions, particularly the source / drain portions, is covered with the resist film 6.

  That is, a positive resist is used as the resist material, and exposure is performed without using a photomask. At this time, the exposure time is adjusted so that the portion from the outermost surface of the resist film 6 to the stopper nitride film 53 above the gate electrode 100 is exposed.

  By developing this, the portion from the outermost surface of the resist film 6 to the stopper nitride film 53 above the gate electrode 100 is removed, and the stopper nitride film 53 above the gate electrode 100 is exposed. In the above exposure, it is desirable to adjust the exposure time so that not only the surface of the stopper nitride film 53 is exposed but also the entire stopper nitride film 53 above the gate electrode 100 is exposed.

  Next, in the step shown in FIG. 4, the stopper nitride film 53 on the exposed gate electrode 100 is removed by dry etching.

  In addition, you may remove by CMP (Chemical Mechanical Polishing) instead of dry etching. In this case, the stopper nitride film 53 can be removed more easily than dry etching.

  By embedding the valley portion between the gate electrodes 100 with a resist film 6 having etching selectivity with respect to the etching of the silicon nitride film, the stopper nitride film 53 other than the upper portion of the gate electrode 100 (in particular, the source / drain portions). The stopper nitride film 53) can be reliably protected.

  Next, in the step shown in FIG. 5, the resist film 6 on the semiconductor substrate 1 is removed by ashing. Through the above steps, the stopper nitride film 53 does not cover the entire surface of the semiconductor substrate 1, but a structure is obtained in which the stopper nitride film 53 is divided above the gate electrode 100.

  FIG. 9 is a plan view of the floating gate type MOS transistor in the state shown in FIG.

  As shown in FIG. 9, the gate electrode 100 of the floating gate type MOS transistor is formed in a stripe shape so that a plurality of the gate electrodes 100 are parallel to each other. A plurality of stripe-shaped element isolation oxide films 51 are formed in parallel to each other so as to be orthogonal to the gate electrode 100 in plan view.

  In FIG. 9, hatched portions are regions covered with the stopper nitride film 53, and are formed on the upper main surface of the hard mask 51, which is the uppermost layer of the gate electrode 100, and the side walls formed on the side surfaces thereof. It is shown that the stopper nitride film 53 does not exist on the end face of the oxide film 10.

  Thus, by adopting a structure in which the stopper nitride film 53 is divided at the upper part of the gate electrode 100, even when a high-temperature heat treatment is performed after the formation of the interlayer oxide film in a later process, the silicon nitride film and the silicon oxide film The stress applied to the stopper nitride film 53 is relieved by the difference in material, and the stress is prevented from affecting the film quality of the tunnel oxide film 22.

  Here, returning to the description of the manufacturing process again, in the process shown in FIG. 6, an insulating film made of a material having high thermal fluidity such as BPSG (boro-phosphosilicate glass) is formed on the semiconductor substrate 1 by, for example, the CVD method. Then, the floating gate type MOS transistor is covered to form an interlayer oxide film 24. Then, high-temperature heat treatment (reflow) is performed in order to improve the embedding property.

  Next, in the step shown in FIG. 7, through photolithography and anisotropic etching, contact holes CH that penetrate the interlayer oxide film 24 and reach the stopper nitride film 53 are formed in the source / drain portions by the SAC technique. . At this time, etching is performed while monitoring the etching state so that the etching stops on the stopper nitride film 53. The contact hole CH may be formed in a hole shape as the name implies, or may be formed in a groove shape so as to be commonly connected to the plurality of active regions 11.

  Since the stopper nitride film 53 exists at the bottom of the contact hole CH, even when the contact hole CH is engaged with the element isolation oxide film 21 due to misalignment, the stopper nitride film 53 and the element isolation oxide film 21 Since there is etching selectivity, the element isolation oxide film is not largely etched by etching of the contact hole, and the margin of the etching process in the SAC technique is not lowered.

  Note that after the contact hole CH is opened, the resist film (not shown) used for photolithography is removed by ashing.

  Thereafter, in the step shown in FIG. 8, the stopper nitride film 53 exposed in the contact hole CH is removed by dry etching to complete the contact hole CH reaching the semiconductor substrate 1.

  After this, the process continues to the process of burying the conductor layer in the contact hole CH to form the substrate contact, but the subsequent processes are not related to the present invention and will not be described.

<A-2. Effect>
As described above, in the method of manufacturing the semiconductor device according to the first embodiment, the stopper nitride film 53 is removed from the upper part of the gate electrode 100, so that the stopper nitride film 53 is divided at the upper part of the gate electrode 100. . Therefore, even when reflow is performed after the formation of the interlayer oxide film 24, the film stress applied to the stopper nitride film 53 due to the difference in material between the stopper nitride film 53 and the interlayer oxide film 24 is alleviated.

  Since the stopper nitride film 53 is in contact with the tunnel oxide film 22 in the source / drain portion, the film stress of the stopper nitride film 53 may affect the film quality of the tunnel oxide film 22, but according to the present invention. Since the film stress can be alleviated, it is prevented that the performance of the flash memory is affected.

<A-3. Modification>
In the above description, a flash memory having a floating gate type MOS transistor has been described as an example. However, the application of the present invention is not limited to a flash memory, and any semiconductor device that forms a contact portion by SAC technology. Is effective. For example, the present invention may be applied to a DRAM having a MOS transistor, and in this case as well, it is possible to prevent the film stress of the stopper nitride film from affecting the gate insulating film.

<B. Second Embodiment>
As a method of manufacturing a semiconductor device according to the second embodiment of the present invention, a manufacturing process of a flash memory having a floating gate type MOS transistor will be described with reference to FIGS. In addition, description is abbreviate | omitted about the process same as the manufacturing method of Embodiment 1 demonstrated using FIGS.

<B-1. Manufacturing process>
After forming the stopper nitride film 53 on the semiconductor substrate 1 through the steps described with reference to FIGS. 1 and 2, in the step shown in FIG. 10, BPSG or TEOS is formed on the semiconductor substrate 1 by, eg, CVD. A silicon oxide film 25 is formed to cover the gate electrode 100 including the sidewall nitride film 52, and a valley portion between the gate electrodes 100 is buried with a silicon oxide film 25 (embedded film). At this time, it goes without saying that the silicon oxide film 25 is also formed in the source / drain portions.

  Here, no reflow is performed after the formation of the silicon oxide film 25, and since the embedding is incomplete, voids 8 are generated in the film, but there is no problem.

  Next, in the step shown in FIG. 11, the silicon oxide film 25 is removed by dry etching until the stopper nitride film 53 on the gate electrode 100 is exposed. At this time, it is desirable to adjust the etching time so that not only the surface of the stopper nitride film 53 is exposed but also the entire stopper nitride film 53 above the gate electrode 100 is exposed.

  Next, in the step shown in FIG. 12, the exposed stopper nitride film 53 on the gate electrode 100 is removed by dry etching.

  By embedding a valley portion between the gate electrodes 100 with a silicon oxide film 25 having etching selectivity with respect to the etching of the silicon nitride film, a stopper nitride film 53 other than the upper portion of the gate electrode 100 (particularly, a source / drain portion) The stopper nitride film 53) can be reliably protected.

  Thereafter, by removing the silicon oxide film 25 on the semiconductor substrate 1 by HF (hydrofluoric acid) treatment, the stopper nitride film 53 is divided on the gate electrode 100 as described with reference to FIG. Obtainable. Thereafter, the contact hole CH is obtained by the SAC technique through the steps described with reference to FIGS. 6 to 8 in the first embodiment.

<B-2. Effect>
As described above, in the method of manufacturing the semiconductor device according to the second embodiment, the stopper nitride film 53 is removed from the upper part of the gate electrode 100, so that the stopper nitride film 53 is divided at the upper part of the gate electrode 100. . Therefore, even when reflow is performed after the formation of the interlayer oxide film 24, the film stress applied to the stopper nitride film 53 due to the difference in material between the stopper nitride film 53 and the interlayer oxide film 24 is alleviated.

  Since the stopper nitride film 53 is in contact with the tunnel oxide film 22 in the source / drain portion, the film stress of the stopper nitride film 53 may affect the film quality of the tunnel oxide film 22, but according to the present invention. Since the film stress can be alleviated, it is prevented that the performance of the flash memory is affected.

<B-3. Modification>
In the method of manufacturing the semiconductor device according to the second embodiment described above, as described with reference to FIG. 11, the silicon oxide film 25 is removed by dry etching until the stopper nitride film 53 above the gate electrode 100 is exposed. However, CMP may be used to remove the silicon oxide film 25.

  That is, in the process shown in FIG. 13, a silicon oxide film 25 is formed on the semiconductor substrate 1 using BPSG or TEOS, covers the gate electrode 100 including the sidewall nitride film 52, and a valley between the gate electrodes 100. This portion is buried with a silicon oxide film 25. Thereafter, in the step shown in FIG. 14, the silicon oxide film 25 is removed by CMP until the stopper nitride film 53 above the gate electrode 100 is exposed, and then the stopper nitride film 53 above the gate electrode 100 is also removed. In this case, it is desirable to adjust the polishing time in CMP so that the entire stopper nitride film 53 above the gate electrode 100 is removed.

  By using CMP, the removal process of the silicon oxide film 25 by dry etching becomes unnecessary, and the manufacturing process can be simplified.

It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is the top view which looked at the floating gate type MOS transistor to which this invention is applied from the upper side. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of the modification of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of the modification of Embodiment 2 which concerns on this invention.

Explanation of symbols

  4 tungsten silicide film, 6 resist film, 7 gate insulating film, 10 sidewall oxide film, 22 tunnel oxide film, 23, 51 hard mask, 24 interlayer oxide film, 25 silicon oxide film, 31 floating gate, 32 control gate, 53 Stopper nitride film, 100 gate electrode.

Claims (7)

(a) a step of disposing a plurality of stripe-shaped gate electrodes, the uppermost layer of which is a silicon nitride film, on a semiconductor substrate so as to be parallel to each other;
(b) using the gate electrode as a mask, forming a source / drain layer by ion-implanting impurities into the main surface of the semiconductor substrate outside the side surface of the gate electrode;
(c) forming a sidewall nitride film so as to cover the side surface of the gate electrode;
(d) forming a stopper nitride film serving as an etching stopper so as to cover the semiconductor substrate including the gate electrode on which the sidewall nitride film is formed;
(e) forming a buried film having etching selectivity with respect to the stopper nitride film on the semiconductor substrate so as to be buried between the gate electrodes covered with the stopper nitride film;
(f) removing the buried film so that the stopper nitride film on the gate electrode is exposed;
(g) removing the stopper nitride film exposed on the gate electrode;
(h) after removing the buried film buried between the gate electrodes, forming an interlayer oxide film on the semiconductor substrate including between the gate electrodes;
(i) forming a contact hole that reaches the source / drain layer through the interlayer oxide film. The step (e)
Applying a positive resist material on the semiconductor substrate so as to cover the gate electrode including the sidewall nitride film, and embedding a gap between the gate electrodes with the resist film as the embedded film;
The step (f)
Including a step of performing an exposure process and a development process on the resist film,
In the exposure process, an exposure time is set so that a portion from the outermost surface of the resist film to the exposure of the stopper nitride film above the gate electrode is exposed,
The method for manufacturing a semiconductor device according to claim 1, wherein a portion from the outermost surface of the resist film to the exposure of the stopper nitride film above the gate electrode is removed by the development process. The step (e)
Forming a silicon oxide film on the semiconductor substrate so as to cover the gate electrode including the sidewall nitride film, and filling the gap between the gate electrodes with the silicon oxide film as the buried film;
The step (f)
2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the silicon oxide film until the stopper nitride film on the gate electrode is exposed by dry etching. The step (g)
4. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of removing the stopper nitride film exposed on the gate electrode by dry etching. The step (g)
The method of manufacturing a semiconductor device according to claim 2, further comprising a step of removing the stopper nitride film exposed on the gate electrode by chemical mechanical polishing. The step (e)
Forming a silicon oxide film on the semiconductor substrate so as to cover the gate electrode including the sidewall nitride film, and filling the gap between the gate electrodes with the silicon oxide film as the buried film;
The step (f)
Removing the silicon oxide film by chemical mechanical polishing until the stopper nitride film on the gate electrode is exposed,
The step (g)
2. The manufacturing of a semiconductor device according to claim 1, further comprising a step of removing the stopper nitride film exposed on the gate electrode by continuing the chemical mechanical polishing even after the stopper nitride film is exposed on the gate electrode. Method. The step (a)
Forming a gate electrode having a floating gate as the gate electrode;
The gate electrode is
A tunnel oxide film disposed on the semiconductor substrate;
The floating gate selectively disposed on the tunnel oxide film;
An inter-gate insulating film disposed on the floating gate;
A control gate disposed on the inter-gate insulating film;
A metal silicide film disposed on the control gate;
A silicon oxide film disposed on the metal silicide film;
The silicon nitride film disposed on the silicon oxide film;
A sidewall oxide film disposed between the side surfaces of the floating gate, the inter-gate insulating film, the control gate, the metal silicide film, the silicon oxide film and the silicon nitride film, and the sidewall nitride film; The method for manufacturing a semiconductor device according to claim 1, comprising:

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