JP2009277897A - Method of manufacturing semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor storage device which has high reliability and whose increase in cost is suppressed. <P>SOLUTION: The method of manufacturing the semiconductor storage device includes the processes of: processing word lines WL and selection transistors ST; forming a resist film 10 between the word lines WL, between the selection transistors ST, and between the selection transistors ST and word lines adjacent to the selection transistors so that an upper surface is lower than an upper surface of a control gate electrode 5; forming an insulating film 11 filling gaps between the word liens WL; forming cavities 12 by removing the resist film 10; forming an insulating film 14 filling gaps between the selection transistors ST; exposing an upper surface of the electrode 5 by removing the insulating film 6; and subjecting the electrode 5 to silicide formation. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor memory device.

  Along with miniaturization of wiring due to high integration of LSIs, an increase in signal delay due to an increase in inter-wiring capacitance has become a problem. As a configuration for reducing the inter-wiring capacitance, an air gap wiring in which a cavity region is formed between the wirings has been proposed (see, for example, Patent Document 1).

  Also, in a nonvolatile semiconductor memory device including a word line having a tunnel oxide film, a floating gate electrode, an interpoly insulating film, and a control gate electrode, which are sequentially stacked, parasitic capacitance generated between word lines (floating gate electrodes) In order to reduce the air gap, an air gap (cavity) is formed between the word lines.

  As a method of forming an air gap between the word lines, a sacrificial film such as an oxide film or a nitride film is embedded between the word lines, the word line (control gate electrode) is silicided, and the sacrificial film is removed by wet etching or the like. A method of depositing a cap film with poor coverage is known. However, in such a method, when the sacrificial film is removed by wet etching or the like, the silicide is also removed at the same time, and there is a problem that the word line resistance is increased, the variation is deteriorated, and the reliability is lowered.

As another method for forming an air gap between word lines, a sacrificial film such as an oxide film or a nitride film is embedded between the word lines, and an insulating film having a selective ratio to the sacrificial film is deposited on the sacrificial film and the word line. A method of forming a trench for removing the sacrificial film and removing the sacrificial film by wet etching or the like is known. However, such a method has a problem that a lithography process and an etching process for forming a groove for removing the sacrificial film are required, and the manufacturing cost increases.
JP 2008-10534 A

  An object of the present invention is to provide a method for manufacturing a semiconductor memory device that has high reliability and suppresses an increase in cost.

  A method for manufacturing a semiconductor memory device according to one embodiment of the present invention includes a first insulating film, a charge storage layer, a second insulating film, a control gate electrode, and a first gate electrode, which are sequentially stacked on a semiconductor substrate at a predetermined interval. A plurality of word lines each including three insulating films, and a selection transistor including a fourth insulating film, an electrode layer, and a fifth insulating film, which are arranged one by one on both ends of the plurality of word lines and sequentially stacked A plurality of memory regions adjacent to each other, and between the word lines, between the selection transistors, and between the selection transistor and a word line adjacent to the selection transistor, the upper surface is the control Forming a resist film so as to be lower than the upper surface of the gate electrode; forming a sixth insulating film so as to bury between the word lines; and And removing the third insulating film and the fifth insulating film, forming a cavity between the word lines, forming a seventh insulating film filling the select transistors, and removing the third insulating film and the fifth insulating film. And exposing the upper surface of the control gate electrode and the upper surface of the electrode layer, and silicidating the control gate electrode and the electrode layer.

  A method for manufacturing a semiconductor memory device according to one embodiment of the present invention includes a first insulating film, a charge storage layer, a second insulating film, a control gate electrode, and a first gate electrode, which are sequentially stacked on a semiconductor substrate at a predetermined interval. A plurality of word lines each including three insulating films, and a selection transistor including a fourth insulating film, an electrode layer, and a fifth insulating film, which are arranged one by one on both ends of the plurality of word lines and sequentially stacked A photosensitive resist film between the word lines, between the select transistors, and between the select transistor and a word line adjacent to the select transistor. A step of exposing the photosensitive resist film using light having a wavelength longer than an interval between adjacent word lines, and the photosensitive resist. And developing the photosensitive resist film between the select transistors, processing the photosensitive resist film between the word lines to a predetermined height, and a sixth insulation filling the word lines Forming a film, removing the photosensitive resist film to form a cavity between the word lines, removing the third insulating film and the fifth insulating film, and controlling the control gate electrode And the step of exposing the upper surface of the electrode layer and the upper surface of the electrode layer, and the step of siliciding the control gate electrode and the electrode layer.

  According to the present invention, it is possible to increase reliability and suppress an increase in cost.

  Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

  (First Embodiment) FIGS. 1 to 7 (excluding FIG. 5) are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention. In each figure, (a) shows a longitudinal section of the memory cell array portion along the bit line direction, and (b) shows a longitudinal section of the end portion of the memory cell array and the select gate transistor along the bit line direction.

  As shown in FIG. 1, a tunnel oxide film 2 made of a silicon oxide film and a floating gate electrode 3 made of a polysilicon film are formed on a semiconductor substrate 1.

  Then, the floating gate electrode 3, the tunnel oxide film 2, and the semiconductor substrate 1 are removed at a predetermined interval along the first direction (bit line direction) to form a trench. A silicon oxide film is buried in the trench to a predetermined height to form an element isolation region (not shown).

  Then, an interpoly insulating film 4 is formed so as to cover the floating gate electrode 3 and the element isolation region, and a first polysilicon film is formed on the interpoly insulating film 4. A part of the first polysilicon film and the interpoly insulating film 4 in a region where the selection transistor ST and the peripheral transistor (not shown) are formed is removed to form a groove. A second polysilicon film is formed on the first polysilicon film so as to fill this groove.

  In the memory cell array portion, the control gate electrode 5 is composed of a first polysilicon film and a second polysilicon film. The select gate transistor ST and the peripheral transistor have an etching interpoly structure in which the polysilicon films (electrode layers) above and below the interpoly insulating film 4 are connected.

  Then, a silicon nitride film 6 is formed on the control gate electrode 5. Subsequently, the silicon nitride film 6, the control gate electrode 5, the interpoly insulating film 4, the floating gate electrode 3, and the tunnel are spaced at predetermined intervals along a second direction (word line direction) orthogonal to the first direction. By removing the oxide film 2, the word line WL and the select transistor ST are processed. One selection transistor ST is disposed at each of both ends of the plurality of word lines WL.

  Then, for example, arsenic is implanted into the surface portion of the semiconductor substrate 1 between the word lines WL, between the select transistors ST, and between the select transistor ST and the word line WL1 adjacent thereto, thereby forming a diffusion layer (not shown). .

  Further, a silicon oxide film 30 is formed using LP-CVD (Low Pressure Chemical Vapor Deposition), for example, so as to cover the word line WL, the select transistor ST, and the semiconductor substrate 1 (see FIG. 14). It is possible to prevent the tunnel oxide film 2 from being deteriorated by components contained in the resist film formed between the word lines WL in the subsequent process. In the following process, the illustration of the silicon oxide film 30 is omitted.

  As shown in FIG. 2, a resist film (organic film) 10 is applied so as to fill between word lines WL, between select transistors ST, and between select transistor ST and adjacent word line WL1. Subsequently, the resist film 10 is etched back using an oxygen-based gas and processed to have a predetermined height. Etching back may be performed after planarization by CMP (chemical mechanical polishing) using the silicon nitride film 6 as a stopper.

  Here, the upper surface of the resist film 10 is higher than the upper surface of the floating gate electrode 3 and lower than the upper surface of the control gate electrode 5. This is because the resist film 10 is a sacrificial film that is removed in a later step and that part becomes a cavity (air gap) so that a cavity is formed at least between the adjacent floating gate electrodes 3.

  Then, a silicon oxide film 11 is formed by plasma CVD so as to cover the word line WL, the select transistor ST, and the resist film 10. The space between the word lines WL is filled with the silicon oxide film 11.

  As shown in FIG. 3, the silicon oxide film 11 is removed by etching so that the upper surface of the silicon nitride film 6 and the upper surface of the resist film 10 between the select transistors ST are exposed. At this time, the upper surface of the resist film formed in the peripheral circuit portion is also exposed.

  The region of the resist film 10 whose upper surface is exposed is a region where no cavity is formed. For example, a bit line contact is formed between the select transistors ST in a later process, and thus is not made hollow.

  Further, the resist film 10 is exposed at the end of the word line WL.

  As shown in FIG. 4, the resist film 10 is removed to form cavities 12 between the word lines WL and between the select transistor ST and the adjacent word line WL1. As shown in FIG. 5A, the resist film 10 is removed by impregnating sulfuric acid / hydrogen peroxide from the end of the word line WL.

  As shown in FIG. 5B, when the ends of the two word lines WL are connected to form a loop shape, wet liquid (sulfuric acid / hydrogen peroxide) is soaked from the exposed portion of the resist film 10 in the loop. As a result, the resist film is removed. In this case, the two word lines WL are made independent by cutting a predetermined portion of the loop shape in a subsequent process.

Then, a TEOS (Si (OC ₂ H ₅ ) ₄ ) film is formed and etched back to form the spacers 13 on the side walls of the select transistors ST between the select transistors ST. In the step shown in FIG. 3, when the silicon oxide film 11 ′ remains on the side wall of the select transistor ST between the select transistors ST, the silicon oxide film 11 ′ becomes a part of the spacer 13.

  Then, for example, arsenic is implanted using the spacer 13 as a mask, and a high concentration diffusion layer (not shown) is formed on the surface portion of the semiconductor substrate 1 between the select transistors ST to form an LDD (Lightly Doped Drain) structure. Subsequently, a silicon nitride film (not shown) serving as a stopper at the time of processing the contact hole is formed between the select transistors ST.

  Further, a BPSG (Boron Phosphorus Silicon glass) film 14 is formed so as to be embedded between the select transistors ST, and planarized by CMP using the silicon nitride film 6 as a stopper.

  As shown in FIG. 6, the silicon nitride film 6 is removed, and the upper surface of the control gate electrode 5 is exposed. In the process shown in FIG. 2, the silicon oxide film 11 is formed up to the upper surface of the resist film 10, that is, up to a position lower than the upper surface of the control gate electrode 5. Therefore, even if the silicon nitride film 6 is removed so that the upper surface of the control gate electrode 5 is exposed, the silicon oxide film 11 remains between the word lines WL and between the select transistor ST and the word line WL1 adjacent thereto. The cavity 12 remains formed.

  Then, a metal film such as Co or Ni is formed on the control gate electrode 5 by sputtering, heat treatment is performed by RTA (Rapid Thermal Annealing) or the like, and a part or all of the control gate electrode 5 is silicided to form a silicide layer 15. Form.

  As shown in FIG. 7, an interlayer insulating film 16 is formed so as to cover the word line WL, the select transistor ST, the silicon oxide film 11, and the BPSG film 14.

  For example, after forming a thin SiN film (not shown) to be a CMP stopper, a TEOS film is formed, and the SiN film is temporarily planarized by CMP using the stopper. An interlayer insulating film 16 is formed by forming a TEOS film thereon.

  Then, the interlayer insulating film 16 and the BPSG film 14 are removed to form a contact hole so as to expose the high concentration diffusion layer formed on the surface portion of the semiconductor substrate 1 between the select transistors ST. Subsequently, a Ti / TiN laminated barrier metal film and a W film are buried in this contact hole by a known technique, and planarization is performed by CMP to form a contact portion 17 to be a bit line contact.

  Since the semiconductor memory device formed by such a method has the cavity 12 between the word lines WL (floating gate electrodes 3), the parasitic capacitance between the floating gate electrodes 3 can be reduced and the operation speed can be improved. it can.

  Further, since the silicide layer is formed after the resist film (sacrificial film) 10 is removed, the silicide layer is not removed, and an increase in word line resistance, deterioration of variations, and the like are prevented, and a highly reliable semiconductor memory. It becomes a device.

  Further, since it is not necessary to form a groove for removing the resist film (sacrificial film) 10, an increase in manufacturing cost can be suppressed.

  (Second Embodiment) FIGS. 8 to 13 are sectional views for explaining a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention. In each figure, (a) shows a longitudinal section of the memory cell array portion along the bit line direction, and (b) shows a longitudinal section of the end portion of the memory cell array and the select gate transistor along the bit line direction. Since the process of processing the word line WL and the select transistor ST (FIG. 1) is the same as that in the first embodiment, description thereof is omitted.

  As shown in FIG. 8, a photosensitive resist film 20 is applied between the word lines WL, between the select transistors ST, and between the select transistor ST and the adjacent word line WL1.

  Then, exposure is performed using light having a wavelength longer than the distance L between the word lines WL, for example, i-line (wavelength: 365 nm) or KrF (wavelength: 248 nm), and development is performed. Since the distance between the word lines WL is narrow, the light does not reach the bottom, and the resist film 20 remains after development. On the other hand, since the gap between the select transistors ST is wide, light reaches the bottom, and the resist film 20 is completely removed by development.

  Since the distance between the select transistor ST and the word line WL1 adjacent thereto is wider than the word line WL distance, the reaching depth of the exposure light is deeper than between the word lines WL, and the remaining amount of the resist film 20 after development is Less than between word lines WL.

  The remaining amount of the resist film 20 (the amount removed by development of the resist film 20) can be adjusted by the exposure dose. In this embodiment, the resist film 20 between the select transistors ST is completely removed by development, and the upper surface of the resist film 20 between the word lines WL remaining after development is lower than the upper surface of the control gate electrode 5 and from the upper surface of the floating gate electrode 3. Adjust the dose so that it is higher.

  This is because the resist film 20 is a sacrificial film that is removed in a later step and that part becomes a cavity (air gap), so that a cavity is formed at least between the adjacent floating gate electrodes 3.

  As shown in FIG. 9, a silicon oxide film 21 is formed using, for example, a plasma CVD method so as to cover the word line WL, the select transistor ST, the resist film 20, and the semiconductor substrate 1. A space between the word lines WL is filled with a silicon oxide film 21.

  As shown in FIG. 10, the silicon oxide film 21 is etched back to expose the upper surface of the silicon nitride film 6 and the surface of the semiconductor substrate 1 between the select transistors ST. At this time, the spacer 22 is formed on the side wall of the selection transistor ST between the selection transistors ST.

  Due to the etch back of the silicon oxide film 21, the resist film 20 is exposed at the end of the word line WL.

  As shown in FIG. 11, the resist film 20 is removed to form a cavity 23 between the word lines WL and between the select transistor ST and the word line WL1 adjacent thereto. The resist film 20 is removed by impregnating sulfuric acid / hydrogen peroxide from the end of the word line WL (see FIG. 5).

  Then, for example, arsenic is implanted using the spacer 22 as a mask, and a high concentration diffusion layer (not shown) is formed on the surface portion of the semiconductor substrate 1 between the select transistors ST to form an LDD (Lightly Doped Drain) structure.

  Further, a BPSG film 24 is formed so as to be embedded between the select transistors ST, and planarized by CMP using the silicon nitride film 6 as a stopper.

  As shown in FIG. 12, the silicon nitride film 6 is removed, and the upper surface of the control gate electrode 5 is exposed. In the process shown in FIG. 9, the silicon oxide film 21 is formed up to the upper surface of the resist film 20, that is, up to a position lower than the upper surface of the control gate electrode 5. Therefore, even if the silicon nitride film 6 is removed so that the upper surface of the control gate electrode 5 is exposed, the silicon oxide film 21 remains between the word lines WL and between the select transistor ST and the word line WL1 adjacent thereto. The cavity 23 remains formed.

  Then, a metal film such as Co or Ni is formed on the control gate electrode 5 by sputtering, heat treatment is performed by RTA (Rapid Thermal Annealing) or the like, and a part or all of the control gate electrode 5 is silicided to form a silicide layer 25. Form.

  As shown in FIG. 13, an interlayer insulating film 26 is formed by depositing a silicon oxide film by, for example, a CVD method so as to cover the word line WL, the select transistor ST, the silicon oxide film 21, and the BPSG film 24.

  Then, the interlayer insulating film 26 and the BPSG film 24 are removed to form a contact hole so as to expose the high concentration diffusion layer formed on the surface portion of the semiconductor substrate 1 between the select transistors ST. Subsequently, a Ti / TiN laminated barrier metal film and a W film are buried in this contact hole by a known technique, and planarization is performed by CMP to form a contact portion 27 to be a bit line contact.

  Since the semiconductor memory device formed by such a method has the cavity 23 between the word lines WL (floating gate electrodes 3), the parasitic capacitance between the floating gate electrodes 3 can be reduced and the operation speed can be improved. it can.

  In addition, since the silicide layer is formed after the resist film (sacrificial film) 20 is removed, the silicide layer is not removed, and an increase in word line resistance, deterioration of variations, and the like are prevented, and a highly reliable semiconductor memory. It becomes a device.

  Further, since it is not necessary to form a groove for removing the resist film (sacrificial film) 20, an increase in manufacturing cost can be suppressed.

  Each of the above-described embodiments is an example and should be considered as not limiting. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is process sectional drawing explaining the manufacturing method of the semiconductor memory device which concerns on the 1st Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 1st Embodiment. It is a figure which shows an example of the end part of a word line. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 2nd Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device based on the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Tunnel oxide film 3 Floating gate electrode 4 Interpoly insulating film 5 Control gate electrode 6 Silicon nitride film 10 Resist film 11 Silicon oxide film 12 Cavity 13 Spacer 14 BPSG film 15 Silicide layer 16 Interlayer insulating film 17 Contact part

Claims (5)

A plurality of word lines each including a first insulating film, a charge storage layer, a second insulating film, a control gate electrode, and a third insulating film, which are sequentially stacked on the semiconductor substrate at a predetermined interval; A plurality of memory regions each having a fourth insulating film, an electrode layer, and a selection transistor including a fifth insulating film, which are arranged one by one on both ends of the plurality of word lines and sequentially stacked, are formed adjacent to each other. And a process of
Forming a resist film between the word lines, between the selection transistors, and between the selection transistor and a word line adjacent to the selection transistor, such that an upper surface is lower than an upper surface of the control gate electrode;
Forming a sixth insulating film so as to fill the space between the word lines;
Removing the resist film and forming a cavity between the word lines;
Forming a seventh insulating film embedded between the select transistors;
Removing the third insulating film and the fifth insulating film to expose the upper surface of the control gate electrode and the upper surface of the electrode layer;
Performing silicidation of the control gate electrode and the electrode layer;
A method for manufacturing a semiconductor memory device.   The eighth insulating film is formed so as to cover the word line, the selection transistor, and the semiconductor substrate after forming the plurality of memory regions and before forming the resist film. A manufacturing method of the semiconductor memory device described.   After the silicidation of the control gate electrode and the electrode layer, an opening is formed to expose the surface of the semiconductor substrate between the selection transistors, and a conductor is embedded in the opening to form a contact portion. A method of manufacturing a semiconductor memory device according to claim 1.   4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the resist film is formed so that an upper surface thereof is higher than an upper surface of the charge storage layer. A plurality of word lines each including a first insulating film, a charge storage layer, a second insulating film, a control gate electrode, and a third insulating film, which are sequentially stacked on the semiconductor substrate at a predetermined interval; A plurality of memory regions each having a fourth insulating film, an electrode layer, and a selection transistor including a fifth insulating film, which are arranged one by one on both ends of the plurality of word lines and sequentially stacked, are formed adjacent to each other. And a process of
Forming a photosensitive resist film between the word lines, between the selection transistors, and between the selection transistor and a word line adjacent to the selection transistor;
Exposing the photosensitive resist film with light having a wavelength longer than an interval between adjacent word lines;
Developing the photosensitive resist film, removing the photosensitive resist film between the selection transistors, and processing the photosensitive resist film between the word lines to a predetermined height; and
Forming a sixth insulating film filling the space between the word lines;
Removing the photosensitive resist film and forming a cavity between the word lines;
Removing the third insulating film and the fifth insulating film to expose the upper surface of the control gate electrode and the upper surface of the electrode layer;
Performing silicidation of the control gate electrode and the electrode layer;
A method for manufacturing a semiconductor memory device.

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