JP2008192891A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely enable formation of a contact hole for a bit line contact between gate electrodes of selection gate transistors. <P>SOLUTION: The gate electrodes MG and SG of memory cell transistors and selection gate transistors are formed on a silicon substrate 1. As the configuration between the selection gates SG-SG, a thick spacer of silicon nitride film 12 is provided on each of facing sidewalls of the gate electrodes SG. The silicon nitride film 12 is formed on the silicon substrate 1, in a state via a silicon oxide film 11. Metal silicide layers 8 of cobalt silicide are formed on the upper parts of the gate electrodes MG and SG. The contact hole 16 for the bit-line contact becomes narrower, by being subjected to constraints in a self-aligned manner at the portions of silicon nitride films 13 and 12 so that a contact plug 17 is surely formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a structure in which a contact plug is formed between gate electrodes constituting adjacent selection gate transistors, and a method for manufacturing the same.

In a semiconductor device as a nonvolatile memory device typified by a NAND flash memory device, tungsten silicide (WSi) is formed on the gate electrode in order to reduce the resistance of the gate electrode of the memory cell transistor. .
In recent years, with the miniaturization of design rules, it has been considered to form a silicide layer of cobalt silicide (CoSi) in order to further reduce the resistance of the gate electrode (see, for example, Patent Document 1). ).

In a semiconductor device including a cobalt silicide layer, there is a method of forming a cobalt silicide layer after processing a gate electrode. When this formation method is used, a silicon nitride film formed as a barrier film (or a stopper film) A two-layer structure of a first film covering the side walls of the gate electrode and a second film covering the upper surface of each gate electrode is formed.
In addition, with the miniaturization of design rules, it is important to reduce the contact diameter of the bit line contact formed between the gate electrodes of the select gate transistors. However, as the generation progresses, it is becoming difficult to make contacts finer by lithography technology.

For this reason, in the structure shown in Patent Document 1, if a misalignment with the lower layer occurs during the formation of the bit line contact, the distance between the bit line contact and the select gate electrode becomes too short, and the leakage current from the bit line contact is reduced. There was a problem that it occurred.
JP 2006-100409 A

  It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that prevent generation of leakage current from a bit line contact.

  In a semiconductor device of one embodiment of the present invention, a plurality of memory cell transistors each including a first gate electrode which is formed over a semiconductor substrate with a gate insulating film interposed therebetween and provided with a metal silicide layer thereon are arranged in a row. A memory unit in which select gate transistors each having a second gate electrode formed on the semiconductor substrate via a gate insulating film and having a metal silicide layer formed thereon is arranged at both ends of the column. An impurity diffusion region formed in a surface layer of the semiconductor substrate between adjacent second gate electrodes, between the first gate electrodes, and the first gate electrodes, A first silicon oxide film formed between the second gate electrode and a second side wall portion of the second gate electrode facing the adjacent second gate electrode. Covering the first silicon nitride film formed through the silicon oxide film, the top surfaces of the first and second gate electrodes, the top surface of the first silicon oxide film, and the top surface of the first silicon nitride film Shorter than the distance between the second silicon nitride film formed on the second silicon nitride film, the third silicon oxide film formed on the second silicon nitride film, and the adjacent second gate electrode. A width dimension is formed so as to pass through the third silicon oxide film and the second silicon nitride film and to reach the surface of the impurity diffusion region through the first silicon nitride film. A contact plug is provided.

  In addition, a method for manufacturing a semiconductor device of one embodiment of the present invention includes a plurality of memory cell transistors each including a first gate electrode formed over a semiconductor substrate with a gate insulating film interposed therebetween and provided with a metal silicide layer thereon. A selection gate transistor having a second gate electrode, which is formed in a row and is formed on the semiconductor substrate via a gate insulating film and provided with a metal silicide layer on the both ends of the row, is arranged. A method of manufacturing a semiconductor device in which memory units are arranged in a matrix direction, the step of forming an impurity diffusion region in a surface layer of the semiconductor substrate between the adjacent second gate electrodes, and the first gate electrode Forming a first silicon oxide film between and between the first gate electrode and the second gate electrode, and the first and second gate electrodes. A first silicon oxide film is interposed on the upper surface of the electrode, the upper surface of the first silicon oxide film, the side wall of the portion facing the second gate electrode, and the upper surface of the impurity diffusion region of the semiconductor substrate via the second silicon oxide film. Forming a silicon nitride film, forming a spacer on the side wall of the portion facing the second gate electrode by spacer processing the first silicon nitride film, and a third space between the spacers. A step of embedding a silicon oxide film, exposing the upper portions of the first and second gate electrodes and the upper portion of the first silicon oxide film, and forming a metal silicide on the upper portions of the first and second gate electrodes; Forming a layer; and an upper surface of the metal silicide layer above the first and second gate electrodes, an upper surface of the first silicon oxide film, the first silicon nitride film, and the third Forming a second silicon nitride film so as to cover the upper surface of the silicon oxide film; forming a fourth silicon oxide film so as to cover the second silicon nitride film; and on the impurity diffusion layer. The second silicon nitride film has a width dimension smaller than the width dimension between the second gate electrodes and a width dimension larger than the width dimension between the spacers, and penetrates the fourth silicon oxide film, Forming a contact hole penetrating through the third silicon oxide film and passing between the spacers to reach the surface of the impurity diffusion region; and forming a contact plug by burying a conductor in the contact hole. It is characterized by that.

  According to the present invention, the leakage current of the bit line contact can be prevented.

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NAND flash memory device of this embodiment will be described.
FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.

  The memory cell array of the NAND flash memory device includes two selection gate transistors Trs1 and Trs2, and a plurality (for example, 8: 2 raised to the nth power (n: 8), for example, between the selection gate transistors Trs1 and Trs2. Are positive cell numbers)) memory cell transistors Trm, and NAND cell units (memory units) SU are formed in a matrix. In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region. A plurality of STIs (shallow trench isolations) 2 as element isolation regions are formed at predetermined intervals along the Y direction in FIG. 2 on the silicon substrate 1 as a semiconductor substrate, whereby the active region 3 is formed in the X direction in FIG. Separately formed. Word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2 orthogonal to the active region 3. A selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. The gate electrode MG of the memory cell transistor that is the first gate electrode is on the active region 3 that intersects the word line WL, and the selection gate that is the second gate electrode is on the active region 3 that intersects the selection gate line SGL1. A gate electrode SG of the transistor is formed.

3 is a cross-sectional view of a portion indicated by a cutting line AA in FIG. That is, the gate electrode SG portion in the active region 3 is shown as the center. In FIG. 3, a gate electrode MG and a gate electrode SG formed on the silicon substrate 1 are formed of a polycrystalline silicon film 5 for a floating gate electrode, an ONO film, etc. via a tunnel insulating film 4 as a gate insulating film. An interelectrode insulating film 6, a polycrystalline silicon film 7 for a control gate electrode, and a cobalt silicide (CoSi ₂ ) film 8 as a metal silicide layer are sequentially laminated.

  In the inter-gate insulating film 6 of the gate electrode SG, an opening 6a for conducting the polycrystalline silicon film 5 and the polycrystalline silicon film 7 is formed, and the polycrystalline silicon film 7 is embedded in the opening 6a. An impurity diffusion region 1a serving as a source / drain region is formed between the gate electrodes MG-MG and between MG-SG of the silicon substrate 1, and an impurity diffusion region 1b is formed between the gate electrodes SG-SG in the same manner as the impurity diffusion region 1a. At the same time, an impurity diffusion region 1c for lowering the contact resistance of a bit line contact, which will be described later, is formed at the center of the impurity diffusion region 1b.

  On the side walls of the gate electrode MG and the gate electrode SG, a silicon oxide film having a thickness of, for example, about 4 nm by an RTO (rapid thermal oxidation) process from the surface of the silicon substrate 1 to a predetermined height, and a film having a thickness of, for example, about 5 nm by LP-CVD. Thick silicon oxide films are stacked and formed as a silicon oxide film 9. Between the silicon oxide film 9 of the gate electrode MG and the silicon oxide film 9 of the gate electrode SG and between the silicon oxide film 9 of the gate electrode MG, a silicon oxide film 10 is formed by LP-CVD.

  Between the pair of gate electrodes SG, a silicon oxide film 11 is formed with a film thickness of, for example, about 10 nm by LP-CVD over the inner side of the silicon oxide film 9 and the surface of the silicon substrate 1, and silicon nitride is formed in the inner region thereof. A film 12 is formed. This silicon nitride film 12 is a remaining portion of what is formed as a spacer as will be described later.

  A silicon nitride film 13 as a barrier film is formed on the upper surface of each gate electrode MG, SG and the upper surface of the silicon nitride film 12 between the pair of gate electrodes SG so as to cover them. The upper surface of the silicon nitride film 13 is in the region where the gate electrodes MG and SG are formed, the region between the gate electrode MG and the gate electrode MG, and the region between the gate electrode MG and the gate electrode SG. It is formed so as to be located at a position higher than the height from the silicon substrate 1 on the upper surface.

  On the silicon nitride film 12 between the gate electrodes SG-SG, the upper surface of the silicon nitride film 13 is formed to be lower than the height of the upper surface of the silicon nitride film 13 in the above-described region. A TEOS film 14 for flattening the recessed portion where the silicon nitride film 13 is located is buried, and further, a TEOS film 15 which is a silicon oxide film is laminated thereon.

  Between the gate electrodes SG-SG, a contact hole 16 reaching the surface of the silicon substrate 1 from the TEOS film 15 is formed in the formation region of the silicon nitride film 12 as shown in the figure. The contact hole 16 is formed so as to penetrate the TEOS films 15 and 14, the silicon nitride films 13 and 12, and the silicon oxide film 11 and expose the surface of the silicon substrate 1. A contact plug 17 in which a conductor is embedded is formed inside the contact hole 16 through a barrier film 17a and is electrically connected to the silicon substrate 1.

  In the above configuration, the contact hole 16 is composed of an upper portion of a penetrating hole formed in the TEOS films 15 and 14 and a lower portion of the hole formed between the silicon nitride films 12 formed as spacers. The opening width A at the upper part of the hole is narrower than the distance D between the adjacent gate electrodes SG and wider than the opening width B of the lower part of the hole 16a. The opening width B of the hole lower portion 16a is substantially the same as the width dimension between the silicon nitride films 12 formed as spacers. Even when the opening position of the upper part of the contact hole 16 is slightly shifted, the position of the lower part of the contact hole 16a is formed at the same position in a self-aligning manner.

Here, the structure of the impurity diffusion regions 1b and 1c will be described.
Impurity diffusion region 1b is formed between adjacent gate electrodes SG. Impurity diffusion region 1c formed for reducing contact resistance is formed in the vicinity of the center of impurity diffusion region 1b so as to be in contact with the entire bottom surface of contact plug 17 with a width wider than the opening width of hole lower portion 16a of contact hole 16. ing. The end portion of the impurity diffusion region 1c is formed to be located below the silicon nitride film 12 with a predetermined distance from the lower end of the side surface of the gate electrode SG in the surface direction of the silicon substrate 1.

  The impurity concentration of the impurity diffusion region 1b is equal to the impurity concentration of the impurity diffusion region 1a, and the impurity concentration of the impurity diffusion region 1c is formed higher than the impurity concentration of the impurity diffusion regions 1a and 1b. The depth of impurity diffusion regions 1a and 1b from the surface of silicon substrate 1 is shallower than the depth of impurity diffusion region 1c from the surface of silicon substrate 1.

  The memory cell transistors Trm share an impurity diffusion layer 1a that functions as a source / drain between those adjacent in the bit line direction. Further, the memory cell transistor is provided such that a current path is connected in series between the selection gate transistors, and is selected by the selection transistor. Here, the illustration of the other select gate transistor to be connected to the current path of the memory cell transistor is omitted. Furthermore, the number of memory cell transistors connected in series between the selection transistors may be a plurality of, for example, 8, 16, 32, and the number is not limited.

Next, a manufacturing process for manufacturing the above configuration will be described with reference to FIGS.
First, as shown in FIG. 4, a tunnel insulating film 4 is formed on a silicon substrate 1, and thereafter, a polycrystalline silicon film 5, a gate insulating film 6 and a control gate (word line) to be a floating gate are formed. A polycrystalline silicon film 7 to be formed is laminated. Further, a silicon nitride film 18 that becomes a hard mask in dry etching is stacked on the polycrystalline silicon film 7. Thereafter, a resist 19 is applied by photolithography to form a predetermined selection gate and word line pattern. After the intergate insulating film 6 is formed on the polycrystalline silicon film 5, a part of the intergate insulating film 6 in the gate electrode SG formation region is removed to form an opening 6a. When the polycrystalline silicon film 7 is formed on the intergate insulating film 6, the polycrystalline silicon film 7 is buried in the opening 6a.

  Next, as shown in FIG. 5, the silicon nitride film 18 is first etched using the patterned resist 19 as a mask by a dry etching technique (for example, RIE (reactive ion etching)), and then this is used as a hard mask. The polycrystalline silicon film 7, the intergate insulating film 6 and the polycrystalline silicon film 5 are etched. Thereafter, the resist 19 is removed.

  Next, as shown in FIG. 6, an oxidation process is performed using an RTO (rapid thermal oxidation) process to form a thermal silicon oxide film of about 4 nm, and a silicon oxide film of about 5 nm is formed by LP-CVD. Thus, the silicon oxide film 9 is formed on the side walls of the gate electrode MG and the gate electrode SG.

  Subsequently, as shown in FIG. 7, an ion implantation process for forming impurity diffusion regions 1a and 1b corresponding to the source / drain regions of the memory cell transistor and the select gate transistor is performed. Thereafter, LP-CVD ( A silicon oxide film 10 having a thickness of about 50 nm is formed over the entire surface by using a low pressure chemical vapor deposition method, and the silicon oxide film 10 is processed to form a spacer 10b by dry etching. The silicon oxide film 10 is also formed in a narrow portion between the gate electrodes MG and between the gate electrode MG and the gate electrode SG. In the dry etching process, etching back is performed to a position slightly lower than the upper surface of the silicon nitride film 18, but most of the state remains. Thereafter, ion implantation is performed on the portion between the gate electrodes SG using the spacer 10b as a mask, the impurity concentration is higher than the impurity concentration of the impurity diffusion region 1b, and the depth from the surface of the silicon substrate 1 is silicon in the impurity diffusion region 1b. An impurity diffusion region 1c deeper than the depth from the surface of the substrate 1 is formed to form an LDD structure.

  Next, as shown in FIG. 8, the resist is patterned by opening only the region between the gate electrodes SG by lithography, and the spacer 10b is removed by hydrofluoric acid chemical treatment using the resist as a mask. To do.

  Subsequently, as shown in FIG. 9, the upper portions of the gate electrodes MG and SG, the upper surface of the silicon oxide film 10 between the gate electrodes MG-MG, the sidewalls of the gate electrode SG between the gate electrodes SG-SG, and the impurities in the silicon substrate 1. A silicon oxide film 10 having a thickness of about 10 nm is formed by LP-CVD so as to cover the surface of the diffusion region 1b, and a silicon nitride film 12a having a thickness of about 80 nm is formed on the silicon oxide film 10.

  Thereafter, as shown in FIG. 10, the silicon nitride film 12a is etched from the upper surface by RIE (reactive ion etching) method, so that the upper surfaces of the gate electrodes MG and SG and portions of the silicon nitride film 12a connected thereto are formed. While removing, the spacer process which forms the spacer 12b in the side wall part of the part which the gate electrode SG has opposed is performed.

  Next, as shown in FIG. 11, an additional silicon nitride film 12c is formed on the upper surface in the above-described state to a thickness of about 20 nm by LP-CVD. Thus, the silicon nitride film 12 is formed by forming the additional silicon nitride film 12c integrally with the spacer 12b. The silicon nitride film 12 is formed so as to cover the surface of the spacer 12c and the upper surface of the second impurity diffusion region 1c.

  Subsequently, as shown in FIG. 12, a BPSG (boro-phospho silicated glass) film 20 is formed on the entire surface by CVD processing on the upper surface of the above configuration, and the BPSG film 20 is embedded in the recessed portion between the gate electrodes SG-SG. . Thereafter, a melt process is performed in a high-temperature wet oxidation atmosphere, and then a planarization process is performed using the silicon nitride film 12 as a stopper by a CMP (chemical mechanical polishing) method, and the BPSG film 20 is polished to form a gap between the gate electrodes SG-SG. The silicon nitride film 12 is planarized so as to remain only in the concave portion.

  Next, as shown in FIG. 13, the silicon nitride films 12 and 18 and the BPSG film 20 are etched by the RIE method to expose the upper surfaces and upper portions of the side surfaces of the polycrystalline silicon film 7 of the gate electrodes MG and SG.

  Thereafter, as shown in FIG. 14, a natural oxide film or the like on the exposed surface of the polycrystalline silicon film 7 serving as a control gate is removed and cleaned by an oxide film removing technique such as dilute hydrofluoric acid treatment. . In this state, the silicon oxide film 11 and the BPSG film 20 between the gate electrodes SG-SG are further etched, and the upper surface becomes a low position. Thereafter, a cobalt film 21 for forming a metal silicide is formed by a plasma sputtering technique.

Next, as shown in FIG. 15, a cobalt silicide film 8 is formed by annealing the cobalt film 21 deposited for forming the metal silicide. The annealing process is performed using a lamp annealing technique such as RTP (rapid thermal processor). Only the portion of the cobalt film 21 that is in contact with the polycrystalline silicon film 7 is silicided, and the remaining portion remains unreacted, and this is removed by treatment with a stripping solution. Thereafter, an annealing process using RTP or the like is performed again as necessary to form a stable cobalt silicide (CoSi ₂ ) film 8.

  Thereafter, as shown in FIG. 16, a silicon nitride film 13 having a thickness of about 30 nm is formed by the LP-CVD technique. The silicon nitride film 13 covers the cobalt silicide films 8 of the gate electrodes MG and SG, and the silicon oxide film 10 between the gate electrodes MG-MG and between the gate electrodes MG-SG and the silicon oxide film between the gate electrodes SG-SG. 21 is formed so as to cover 21.

  After that, as shown in FIG. 17, a TEOS film 14 is formed by LP-CVD, and CMP processing is performed using the silicon nitride film 13 as a stopper, so that a recess between the gate electrodes SG-SG of the silicon nitride film 13 is formed. The TEOS film 14 is buried in the part.

  Subsequently, as shown in FIG. 18, a TEOS film 15 as a fourth silicon oxide film is similarly formed to a thickness of 400 nm by the CVD technique. Thereafter, a resist 22 is applied by a photolithography process to form a resist pattern 22a of the contact hole 16 for forming the contact plug 17 to be a bit line contact. At this time, the width dimension A of the opening of the resist pattern 21a is set smaller than the width dimension D between the gate electrodes SG-SG.

  Next, the surface of the silicon substrate 1 is exposed through the TEOS films 15 and 14, the silicon nitride film 13, the silicon oxide film 21, the silicon nitride film 12, and the silicon oxide film 11 by the RIE technique using the resist pattern 22 a as a mask. The contact hole 16 is formed. At this time, the contact hole 16 has a width corresponding to the width A of the opening of the resist pattern 22a in the TEOS films 15 and 14, but silicon nitride is formed in a portion below the silicon nitride film 13 portion. Since the etching rate of the film 13 is slow, the opening width is reduced in a self-aligning manner, and the width dimension B is limited to the opening width of the portion where the step has occurred.

  Thereafter, as shown in FIG. 3, a contact plug 17 is formed by embedding a conductor in the contact hole 16. The contact plug 17 is formed in a state where a barrier metal 17a such as TiN is formed and then a conductor such as tungsten (W) or copper (Cu) is formed and buried in the contact hole 16 by a CMP process or the like. . Thereafter, although not shown, this multi-layer wiring process to the upper layer is continued.

  According to the present embodiment, since the silicon nitride film 12 is formed as a spacer between the gate electrodes SG and SG and is covered with the silicon nitride film 13, the contact hole 16 for bit line contact is formed. In addition, it can be formed in a self-aligned manner.

  That is, the opening width B in the hole lower portion 16a which is a portion reaching the surface of the silicon substrate 1 below the contact hole 16 is substantially the width dimension of the opening portion in which the silicon nitride film 12 formed as a spacer is not formed. Will be the same. Therefore, even if the position of the resist pattern 22a for forming the contact hole 16 is slightly deviated, the contact hole 16 can be reliably formed if it is not deviated from the position of the hole lower portion 16a formed in a self-alignment manner.

  If the formation position of the resist pattern 22a does not deviate from between the gate electrodes SG-SG, the contact hole 16 can be formed without damaging the gate electrode SG. As a result, the distance between the gate electrode SG of the select gate transistor and the contact plug 17 can be prevented from becoming too close, and the occurrence of a leakage current between the gate electrode SG and the contact plug 17 can be prevented.

  Further, a region of the impurity diffusion region 1b having a shallow depth from the surface of the silicon substrate 1 that is not overlapped with the impurity diffusion region 1c is covered with the silicon nitride film 12 and the silicon oxide films 9 and 12, and the hole of the contact hole 16 is formed. Since the lower portion 16a is formed in a self-aligned manner between the adjacent silicon nitride films 12, the lower surface of the contact plug 17 can be prevented from coming into contact with a region not overlapping the impurity diffusion region 1c of the impurity diffusion region 1b. Generation of junction leakage current flowing from the contact plug 17 to the silicon substrate 1 through the impurity diffusion region 1b can be prevented.

  Further, since the silicon oxide film 11 is formed as a base when the silicon nitride film 12 is formed, it is possible to avoid the state in which the silicon nitride film 12 is in direct contact with the silicon substrate 1. It is possible to prevent adverse effects such as stress strain.

  Further, since the silicon oxide film 10 is embedded between the gate electrodes MG and MG and between the MG and SG and the silicon nitride films 12 and 13 are not provided, silicon nitride having a dielectric constant larger than that of the silicon oxide film 10 is provided. Compared with the case where the film 12 is embedded, the parasitic capacitance in the memory cell transistor can be reduced, and malfunction between the memory cells can be prevented and an electrically stable operation can be performed.

  Further, by providing the first and second silicon nitride films 12 and 13, it is possible to prevent impurities and moisture from entering the lower layer side, and the reaction between the cobalt silicide film 8 and the insulating film such as the TEOS film 15. Can be suppressed. Further, since the second silicon nitride film 13 also functions as a stopper in the etching process or the CMP process, it can be used effectively in the processing process.

The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the present embodiment, the case where the cobalt silicide film 8 is applied as the formation of the gate electrode MG of the memory cell has been introduced. However, the same metal can be used for forming the silicide film by using Ni, Pt, Ti, Ta, and W. An effect can be obtained. Further, the silicon nitride film 13 on the electrode should be changed in film formation method according to the heat resistance of the electrode, and in this embodiment, the LP-CVD method is used. Film formation by CVD may be used.

The TEOS films 14 and 15 may be formed separately as shown in the embodiment, or may be prepared to a predetermined film thickness by performing film formation at a time and performing a CMP process.
In addition, the film thickness of the silicon oxide film on the electrode needs to be 50% or more of the frontage dimension of the upper part of the adjacent word line electrode in the memory cell. This is because the frontage can always be closed in principle if there is a film thickness of 50% or more of the frontage size.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device according to an embodiment of the present invention; Schematic plan view showing a partial layout pattern of the memory cell region Sectional drawing of the part shown by the cutting line AA in FIG. Schematic longitudinal section at one stage of the manufacturing process (Part 1) Schematic longitudinal section at one stage of the manufacturing process (2) Schematic longitudinal section at one stage of the manufacturing process (Part 3) Schematic longitudinal section at one stage of the manufacturing process (Part 4) Schematic longitudinal section at one stage of the manufacturing process (Part 5) Schematic longitudinal section at one stage of the manufacturing process (Part 6) Schematic longitudinal section at one stage of the manufacturing process (Part 7) Schematic longitudinal section at one stage of the manufacturing process (Part 8) Schematic longitudinal section at one stage of the manufacturing process (No. 9) Schematic longitudinal section at one stage of the manufacturing process (No. 10) Schematic longitudinal section at one stage of the manufacturing process (Part 11) Schematic longitudinal section at one stage of the manufacturing process (No. 12) Schematic longitudinal section at one stage of the manufacturing process (13) Schematic longitudinal section at one stage of the manufacturing process (No. 14) Schematic longitudinal section at one stage of the manufacturing process (Part 15) Schematic longitudinal section at one stage of the manufacturing process (No. 16)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is an STI (element isolation region), 3 is an active region, 8 is a cobalt silicide film, 10 is a silicon oxide film, 10a is a void, 11 is a silicon oxide film, 12 is Silicon nitride film, 13 is a TEOS film (interlayer insulating film), 14 is a silicon nitride film (barrier film), 15 is a TEOS film, 17 is a contact plug, G is a gate electrode of a memory cell transistor, and SG is a gate of a select gate transistor Electrode.

Claims (5)

A plurality of memory cell transistors each having a first gate electrode formed on a semiconductor substrate through a gate insulating film and provided with a metal silicide layer on the top are arranged in a row, A semiconductor device in which a memory unit in which a selection gate transistor having a second gate electrode formed on a semiconductor substrate via a gate insulating film and having a metal silicide layer formed thereon is arranged is arranged in a matrix direction. ,
An impurity diffusion region formed in a surface layer of the semiconductor substrate between the adjacent second gate electrodes;
A first silicon oxide film formed between the first gate electrodes and between the first gate electrode and the second gate electrode;
A first silicon nitride film formed on a side wall portion of the second gate electrode facing the adjacent second gate electrode via a second silicon oxide film;
A second silicon nitride film formed so as to cover the upper surfaces of the first and second gate electrodes, the upper surface of the first silicon oxide film, and the upper surface of the first silicon nitride film;
A third silicon oxide film formed on the second silicon nitride film;
It is formed between adjacent second gate electrodes with a width shorter than the distance between them, and penetrates the third silicon oxide film and the second silicon nitride film, and the first silicon nitride film And a contact plug formed so as to reach the surface of the impurity diffusion region. The semiconductor device according to claim 1,
In the contact plug, a first width dimension of a portion in contact with the second impurity diffusion region is defined by a dimension between the opposing second silicon nitride films, and a portion in the third silicon oxide film The semiconductor device is characterized in that the second width dimension is set larger than the first width dimension. The semiconductor device according to claim 1 or 2,
The impurity diffusion region includes a first region formed in a surface layer of the semiconductor substrate over the entire area between the adjacent second gate electrodes, and a lower portion of one end of the first silicon nitride film adjacent to one end. And the other end is located below the other of the adjacent first silicon nitride films, and has a second region whose depth from the surface of the semiconductor substrate is deeper than the first region. A semiconductor device characterized by the above. A plurality of memory cell transistors each having a first gate electrode formed on a semiconductor substrate through a gate insulating film and provided with a metal silicide layer on the top are arranged in a row, Method of manufacturing a semiconductor device in which a memory unit in which a selection gate transistor having a second gate electrode formed on a semiconductor substrate via a gate insulating film and having a metal silicide layer provided thereon is arranged in a matrix direction Because
Forming an impurity diffusion region in a surface layer of the semiconductor substrate between the adjacent second gate electrodes;
Forming a first silicon oxide film between the first gate electrodes and between the first gate electrode and the second gate electrode;
A second surface is formed on the upper surfaces of the first and second gate electrodes, the upper surface of the first silicon oxide film, the side wall portion of the portion facing the second gate electrode, and the upper surface of the impurity diffusion region of the semiconductor substrate. Forming a first silicon nitride film via a silicon oxide film;
Forming a spacer on a side wall portion of a portion facing the second gate electrode by processing the first silicon nitride film with a spacer;
Burying and forming a third silicon oxide film between the spacers;
Exposing the upper portions of the first and second gate electrodes and the upper portion of the first silicon oxide film, and forming a metal silicide layer on the upper portions of the first and second gate electrodes;
The upper surface of the metal silicide layer above the first and second gate electrodes, the upper surface of the first silicon oxide film, the upper surfaces of the first silicon nitride film and the third silicon oxide film are covered. Forming a second silicon nitride film;
Forming a fourth silicon oxide film so as to cover the second silicon nitride film;
On the impurity diffusion layer, the second silicon oxide film penetrates the second silicon oxide film with a width smaller than the width between the second gate electrodes and larger than the width between the spacers. Forming a contact hole that penetrates through the silicon nitride film, the third silicon oxide film, and reaches the surface of the impurity diffusion region through the spacers;
And a step of forming a contact plug by burying a conductor in the contact hole. In the manufacturing method of the semiconductor device according to claim 4,
The step of forming the impurity diffusion region includes the step of forming the first impurity diffusion region in the surface layer of the semiconductor substrate over the entire area between the adjacent second gate electrodes, and the first portion where one end is adjacent. Located below one of the silicon nitride films, the other end is located below the other of the adjacent first silicon nitride films, and the depth from the surface of the semiconductor substrate is deeper than the first region A method for manufacturing a semiconductor device comprising the step of forming a second impurity diffusion region.

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