JP2009283826A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress increase in the etching amount, in a trench pattern, of a semiconductor substrate when simultaneously forming a hole pattern for bit line contacts and a trench pattern for a source line contact. <P>SOLUTION: A semiconductor device includes an array of memory cells provided on a semiconductor substrate 1. In each memory cell, bit line contacts formed of a hole pattern are arranged in a word line direction, and a source line contact is composed of a trench pattern extending in the word line direction. In a portion between gate electrodes of a select gate transistor surrounding the source line contact on the surface of the semiconductor substrate 1, a laminate of a silicon oxide film 12 and a barrier film 13 for reactive ion etching (RIE) is provided. In a portion between gate electrodes of a select gate transistor surrounding each bit line contact on the surface of the semiconductor substrate 1, only a silicon oxide film 12 includes no barrier film laminated. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device suitable for a semiconductor memory device such as a NAND type or NOR type flash memory device and a method for manufacturing the same.

  In the development of semiconductor memory devices, miniaturization of elements has been promoted year by year in order to achieve large capacity and low cost. For example, in a NAND flash memory device, the wiring pitches such as bit lines and word lines have been miniaturized. When miniaturizing each wiring pitch, it is difficult to open a contact hole miniaturized to the same degree as the line wiring at a high aspect. Therefore, every other bit line contact and source line contact are arranged as bit lines. A so-called plover arrangement that is displaced in the direction has been proposed. An example of this plover arrangement is shown in Patent Document 1.

  In the configuration in which the bit line contact and the source line contact are arranged in a staggered manner, when further miniaturization is to be performed, the source line contact is focused on, and the source line contact is configured by forming a linear groove pattern. A configuration has been proposed in which the width of a region where a line contact is provided (a region between select gates) is further narrowed. An example of a semiconductor memory device that constitutes a source line contact with this groove pattern is shown in Patent Document 2.

In manufacturing a semiconductor memory device having such a configuration, when performing processing to simultaneously open a hole pattern of a bit line contact and a groove pattern of a source line contact, a reactive ion etching (hereinafter referred to as RIE) method is used. To process. In the case of the RIE method, the etching rate is generally higher in the groove pattern than in the hole pattern. For this reason, when the hole pattern of the bit line contact and the groove pattern of the source line contact are opened simultaneously, the etching rate in the groove pattern (source line contact) increases, and the depth of the groove pattern increases, that is, the silicon substrate The amount of shaving increases. As described above, when the amount of chipping of the silicon substrate is increased, the reaction tends to approach to the diffusion layer when forming a barrier metal such as Ti and silicidation to be formed later, and junction leakage occurs. there were.
JP 2005-354003 A JP 2006-303009 A

  The present invention provides a semiconductor device capable of preventing an increase in the amount of chipping of a semiconductor substrate in a groove pattern of a source line contact when performing a process of simultaneously opening a hole pattern of a bit line contact and a groove pattern of a source line contact. And it aims at providing the manufacturing method.

  The semiconductor device according to the present invention includes a semiconductor substrate in which a plurality of element regions defined by element isolation regions are formed along a predetermined direction, and a plurality of element regions extending in a perpendicular direction perpendicular to the predetermined direction above the semiconductor substrate. A plurality of words formed extending in the orthogonal direction between the first and second select gate lines formed in this manner and the first and second select gate lines above the semiconductor substrate. A memory cell transistor having a charge storage layer formed between the element region and the word line, and a first gate electrode formed between the element region and the first select gate line A first select gate transistor having a second gate electrode formed between the element region and the second select gate line, and a top surface of the semiconductor substrate. A plurality of bit lines extending in the predetermined direction corresponding to the element region, and a hole pattern, and a plurality of bit lines being arranged in the orthogonal direction corresponding to the element region. A bit line contact connecting the bit line and the memory cell transistor via the first select gate transistor, and a groove pattern extending in the orthogonal direction, and passing through the second select gate transistor A source line contact for connecting the memory cell transistor to a source line, and a first silicon oxide contacted with the second gate electrode between the source line contact and the second gate electrode. A silicon film formed between the film, a second silicon oxide film in contact with the source line contact, and the first and second silicon oxide films A nitride film is formed, and between the bit line contact and the first gate electrode, the first silicon oxide film is formed in contact with the first gate electrode and in contact with the bit line contact. The second silicon oxide film is formed, and the first and second silicon oxide films are formed so as to be in direct contact with each other.

  According to the present invention, it is possible to prevent an increase in the amount of chipping of the semiconductor substrate in the groove pattern of the source line contact when performing processing for simultaneously opening the hole pattern of the bit line contact and the groove pattern of the source line contact. .

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NAND flash memory device of this embodiment will be described.
FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.

  The memory cell array of the NAND flash memory device includes a NAND cell unit including two selection gate transistors Trs and a plurality (for example, 32) of memory cell transistors Trm connected in series between the selection gate transistors Trs. The SU is formed in a matrix. In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2 shows a layout pattern of a part of the memory cell region. In FIG. 2, a plurality of STIs (shallow trench isolation) 2 as element isolation regions are formed at predetermined intervals along the Y direction in FIG. 2 on a silicon substrate 1 as a semiconductor substrate. 2 are separated in the X direction. Word lines WL of memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2 orthogonal to the active region 3. In this case, the word lines WL and the active regions 3 are formed in a lattice shape, and form, for example, a NAND string including 32 word lines WL as a set.

  In addition, selection gate lines SGL1 and SGL2 of a pair of selection gate transistors are formed at both ends of the NAND column, respectively. The pair of select gate lines SGL1 is on the drain side, and the pair of select gate lines SGL2 is on the source side. Bit line contacts CB are formed in the active region 3 between the pair of selection gate lines SGL1. The bit line contacts CB are arranged in two columns by shifting every other hole arrangement in the bit line direction (that is, adjacent ones are alternately shifted in the bit line direction and arranged in two columns). This is a so-called plover arrangement.

  A source line contact CS is formed in the active region 3 between the pair of selection gate lines SGL2. Unlike the bit line contact CB, the source line contact CS is a linear pattern extending in the word line direction, which is configured by a single linear groove pattern.

  In the case of the above configuration, the cell array is formed by inverting the source / drain every other NAND column, sharing the bit line contact CB and the source line contact CS between adjacent NAND columns, and repeatedly arranging them. . A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate lines SGL1 and SGL2. ing.

  Next, a manufacturing process from the gate formation to the bit line contact CB and source line contact CS formation of the NAND flash memory device described above will be described with reference to FIGS. ). 3A to 14A are cross-sectional views of the peripheral portion of the bit line contact CB (a cross-sectional view taken along line AA in FIG. 2), and FIG. 3B to FIG. ) Is a cross-sectional view of the peripheral portion of the source line contact CS (cross-sectional view taken along the line BB in FIG. 2). In the present embodiment, since the bit line contacts CB are arranged in a staggered manner, every other bit line contact CB is clearly shown in the cross section along the line AA, but is shifted by, for example, 100 nm in the bit line direction. The remaining bit line contacts CB are also present.

  First, as shown in FIG. 3, an interelectrode insulating film (interpoly insulating film) made of a gate oxide film 5, a floating gate electrode polysilicon film 6, an ONO film, a NONON film, or the like is formed on a silicon substrate 1 as a semiconductor substrate. Film) 7, polysilicon film 8 for control gate electrode, and silicon nitride film 9 as a mask material for gate processing are sequentially formed. Then, the gate electrodes MG and SG are patterned by using the photolithography method and the RIE method (FIG. 3 shows a state after the gate electrode processing).

  Subsequently, as shown in FIG. 4, a silicon oxide film 10 of, eg, about 5 nm is formed by LP-CVD (FIG. 4 shows a state after the sidewall is formed). Thereafter, as shown in FIG. 5, a silicon oxide film 11 for forming LDD is formed to a thickness of about 50 nm by LP-CVD and processed into a spacer by RIE (FIG. 5 shows a state after processing of LDD spacer. ).

  Next, as shown in FIG. 6, for example, a silicon oxide film 12 and a contact processing stopper material, that is, a silicon nitride film 13 as an RIE barrier film, for example, about 20 nm are formed by LP-CVD. FIG. 6 shows a state after the liner silicon nitride film (silicon nitride film 13) is formed. Subsequently, a resist 14 is formed as shown in FIG. Then, as shown in FIG. 8, an opening 14a is formed in the resist 14 so as to correspond to the concave portion 15 for forming the drain portion, that is, the bit line contact CB, by lithography (FIG. 8A). )). In this case, the opening 14 a corresponds to a portion between the gate electrodes SG of the selection gate transistor surrounding the bit line contact CB on the surface of the silicon substrate 4. The source portion, that is, the concave portion 16 for forming the source line contact CS is covered with a resist 14 (FIG. 8B). Thereafter, as shown in FIG. 8A, the drain portion, that is, the bottom surface and the side surface in the recess 15 for forming the bit line contact CB, and the recess near the recess 15 in the upper surface of the gate electrode SG are formed by the RIE technique. The silicon nitride film 13 formed on the portion is removed.

  Subsequently, as shown in FIG. 9, after removing the resist 14, a first interlayer insulating film 17 made of, for example, an HDP film is formed, and the recesses 15 and 16, that is, between the gate electrodes are buried. Then, planarization is performed using the silicon nitride film 13 as a stopper (FIG. 9 shows a state after the first interlayer insulating film is formed and then planarized).

  Thereafter, as shown in FIG. 10, the silicon nitride film 9, the silicon oxide film 12 and the silicon nitride film 13 on the polysilicon film 8 for the control gate electrode are etched back by the RIE method (FIG. 10 shows the silicon nitride film of the mask). The state after the etch back of the film (silicon nitride film 9) is shown). Subsequently, as shown in FIG. 11, a Co film having a thickness of about 30 nm is sputtered by sputtering, and silicided by RTA treatment to form a cobalt silicide film 18. Thereafter, the unreacted Co film is peeled off by chemical treatment containing sulfuric acid (FIG. 11 shows a state after the formation of the cobalt silicide film).

  Next, as shown in FIG. 12, a silicon oxide film 19 is formed to a thickness of, for example, about 400 nm as a second interlayer insulating film by plasma CVD. Thereafter, as shown in FIG. 13, two types of contact patterns are formed by a lithography technique, that is, a hole pattern (drain portion) for the bit line contact CB and a groove pattern (source portion) for the source line contact CS, The first and second interlayer insulating films 17 and 19 are processed by the RIE method. As a result, a hole 20 for the bit line contact CB (see FIG. 13A) and a line-shaped groove 21 for the source line contact CS (see FIG. 13B) are formed. Thereafter, although not shown, a conductor is buried in the hole 20 and the groove 21 to form a bit line contact plug and a word line contact plug. Then, after a barrier metal film such as Ti is formed and silicidized, the process continues to the multilayer wiring process to the upper layer.

  In the case of the above configuration, the hole 20 for the bit line contact CB penetrates the first and second interlayer insulating films 17 and 19 and the silicon oxide film 12 as shown in FIG. It is formed to the extent of digging a little. An impurity diffusion region 1a is formed on the surface of the silicon substrate 1 by ion implantation, and a high-concentration impurity diffusion region 1b is formed to constitute an LDD structure. The impurity diffusion regions 1a and 1b are drain regions. The depth dimension d of the impurity diffusion region 1b is, for example, about 40 nm. That is, the junction (bonding) is provided at a depth of about 40 nm from the surface of the silicon substrate 1.

  Further, as shown in FIG. 14B, the line-shaped groove 21 for the source line contact CS penetrates the first and second interlayer insulating films 17 and 19, the silicon nitride film 13, and the silicon oxide film 12, The silicon substrate 4 is formed to the extent that the surface of the silicon substrate 4 is dug a little (a little deeper than the depth of the hole 20 for the bit line contact CB). An impurity diffusion region 1a is formed on the surface of the silicon substrate 1 by ion implantation, and a high-concentration impurity diffusion region 1b is formed to constitute an LDD structure. The impurity diffusion regions 1a and 1b are source regions. The depth dimension d of the impurity diffusion region 1b is, for example, about 40 nm. That is, the junction (bonding) is provided at a depth of about 40 nm from the surface of the silicon substrate 1.

  Here, when the hole 20 for the bit line contact CB and the line-shaped groove 21 for the source line contact CS are processed simultaneously by the RIE method, the etching rate of the groove 21 is higher than that of the hole 20, and thus the conventional configuration. In this case, the amount of shaving of the silicon substrate 1 is larger in the groove 21 than in the hole 20. On the other hand, in this embodiment, since the silicon nitride film 13 is removed from the bottom surface of the recess 15 for the bit line contact CB, the time for etching the silicon nitride film 13 is not required, so the entire hole 20 The time required for the etching can be shortened. As a result, the etching time of the groove 21 is shortened in the same manner, so that the amount of shaving of the silicon substrate 1 in the direction of the groove 21 is significantly reduced compared to the conventional configuration. As a result, the occurrence of junction leak can be suppressed.

  Incidentally, in the conventional configuration, since the silicon nitride film 13 is formed on the bottom surface of the recess 15 for the bit line contact CB, it is necessary to etch off the silicon nitride film 13 in order to open the hole 20. In this case, as the processing steps, there are a first step for processing the interlayer insulating film (higher selection ratio with respect to silicon nitride film) and a second step for processing the silicon nitride film 13 (not possible with respect to silicon selection ratio). In the case of the above-described conventional configuration, when the groove 21 for the source line contact CS is processed, the silicon nitride film 13 is slipped out in the first step (the etching rate with the hole 20 of the bit line contact CB). Due to the difference, the amount of scraping of the silicon substrate 1 was considerably large in combination with the second step. As described above, the adverse effect of increasing the amount of chipping of the silicon substrate 1 is that when the barrier metal film such as Ti formed later and the silicidation are formed, the reaction becomes close to the impurity diffusion layer and junction leakage is caused. It sometimes occurred. On the other hand, according to the present embodiment, the occurrence of junction leak can be suppressed as described above.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.

  In the above embodiment, the silicon nitride film 13 is formed as a barrier film on the silicon oxide film 12 in the step shown in FIG. 6, but any film having processing selectivity with the silicon oxide film 12 may be used. A silicon film may be formed. In the above embodiment, the bit line contacts CB are arranged in a staggered manner, but the adjacent bit line contacts CB may be arranged in a line without shifting.

  In the above embodiment, the present invention is applied to the NAND flash memory device. However, the present invention may be applied to other semiconductor memory devices such as a NOR flash memory device.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device according to an embodiment of the present invention; Schematic plan view showing a partial layout pattern of the memory cell region Schematic longitudinal section at one stage of the manufacturing process (Part 1) Schematic longitudinal section at one stage of the manufacturing process (2) Schematic longitudinal section at one stage of the manufacturing process (Part 3) Schematic longitudinal section at one stage of the manufacturing process (Part 4) Schematic longitudinal section at one stage of the manufacturing process (Part 5) Schematic longitudinal section at one stage of the manufacturing process (Part 6) Schematic longitudinal section at one stage of the manufacturing process (Part 7) Schematic longitudinal section at one stage of the manufacturing process (Part 8) Schematic longitudinal section at one stage of the manufacturing process (No. 9) Schematic longitudinal section at one stage of the manufacturing process (No. 10) Schematic longitudinal section at one stage of the manufacturing process (Part 11) Schematic enlarged vertical sectional view at one stage of the manufacturing process

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is STI, 3 is an active region, 5 is a gate oxide film, 6 is a polysilicon film for a floating gate electrode, 7 is an interelectrode insulating film, and 8 is a control gate electrode. Polysilicon film, 9 is a silicon nitride film, 10 is a silicon oxide film, 11 is a silicon oxide film, 12 is a silicon oxide film, 13 is a silicon nitride film (barrier film), 15 and 16 are recesses, and 17 is a first film. An interlayer insulating film, 18 is a cobalt silicide film, 19 is a silicon oxide film, 20 is a hole, and 21 is a groove.

Claims (4)

A semiconductor substrate in which a plurality of element regions partitioned by element isolation regions are formed along a predetermined direction;
A first selection gate line and a second selection gate line formed on the semiconductor substrate so as to extend in orthogonal directions orthogonal to the predetermined direction;
A plurality of word lines formed to extend in the orthogonal direction between the first and second selection gate lines above the semiconductor substrate;
A memory cell transistor having a charge storage layer formed between the element region and the word line;
A first select gate transistor having a first gate electrode formed between the element region and the first select gate line;
A second select gate transistor having a second gate electrode formed between the element region and the second select gate line;
A plurality of bit lines formed to extend in the predetermined direction above the semiconductor substrate in correspondence with the element region;
Each bit line contact is formed of a hole pattern, and is formed by being arranged in plural in the orthogonal direction corresponding to the element region, and connects the bit line and the memory cell transistor via the first selection gate transistor. When,
Comprising a groove pattern extending in the orthogonal direction, and comprising a source line contact for connecting the memory cell transistor to a source line via the second select gate transistor,
Between the source line contact and the second gate electrode, a first silicon oxide film in contact with the second gate electrode, a second silicon oxide film in contact with the source line contact, A silicon nitride film formed between the first and second silicon oxide films is formed;
Between the bit line contact and the first gate electrode, the first silicon oxide film is formed in contact with the first gate electrode and in contact with the bit line contact. A semiconductor device, wherein a silicon oxide film is formed and the first and second silicon oxide films are in direct contact with each other.   2. The semiconductor device according to claim 1, wherein every other bit line contact is shifted in the bit line direction and arranged in two columns. A memory cell array in which memory cells are arranged in a matrix on a semiconductor substrate, bit line contacts made of hole patterns in each memory cell are arranged in a word line direction, and source line contacts in each memory cell are arranged in a word line direction. In the method of manufacturing a semiconductor device configured from an extending groove pattern,
Forming a gate electrode on the active region of the semiconductor substrate by stacking a gate oxide film, a floating gate electrode, an interelectrode insulating film, and a control gate electrode;
Forming a silicon oxide film on the semiconductor substrate;
Forming a silicon nitride film on the silicon oxide film;
Removing a portion between the gate electrodes of the select gate transistor surrounding the bit line contact in the silicon nitride film;
Forming a first interlayer insulating film on the semiconductor substrate, and performing a planarization process. Removing the portion of the silicon nitride film comprises forming a resist on the silicon nitride film;
Forming an opening by a lithography technique in a portion between the gate electrodes of the select gate transistor surrounding the bit line contact in the resist;
4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of removing the silicon nitride film by a reactive ion etching method using the resist as a mask.

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