JP2008118025A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a capacitance value between a contact plug and another electrical conductive element. <P>SOLUTION: A stopper insulating film 11 is formed even in a prescribed area around an upper side-wall CBa along the upper side-wall CBa of a bit-line contact CB. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a plug and a method for manufacturing the same.

  Conventionally, a semiconductor device has been designed in consideration of mask misalignment at the time of manufacture. However, with the recent miniaturization of elements and reduction in circuit design rules, the circuit area is reduced. For this reason, a borderless contact structure with a small misalignment margin has been introduced from the design stage. For this reason, when a plug is formed, there is a possibility that a bonding failure may occur due to misalignment, and at the same time, there is a risk of inducing a device failure due to contact between adjacent gate electrodes and wiring layers. In view of this, a technique has been developed in which a spacer insulating film is formed of a silicon nitride film over the entire side wall of the gate electrode or wiring layer (see, for example, Patent Document 1).

  On the other hand, generally, a metal wiring is formed on such a plug, and is configured to give a predetermined potential to the plug (for example, see Patent Document 2). According to Patent Document 2, an etching stop layer is formed on the entire structure of the interlayer insulating film, located beside the metal wiring.

According to the technique disclosed in Patent Document 1, the spacer insulating film is provided on the entire side wall of the gate electrode or the wiring layer. However, when the spacer insulating film is formed on the entire side wall of the insulating material having a high relative dielectric constant, it is not preferable because the capacitance value between the plug and another structure increases. Further, according to the technique disclosed in Patent Document 2, since the etching stop layer is formed over the entire side in the plane direction with respect to the side portion of the upper side wall of the plug, the plug and other electrical components Similarly, the capacitance value increases in the meantime, which is not preferable.
JP 2002-110822 A (FIG. 3 etc.) Japanese Patent Laying-Open No. 2005-33163 (paragraph 0013)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce a capacitance value between a plug and another electrically conductive element.

  One embodiment of the present invention is a semiconductor substrate having a conductive layer formed as a surface layer, an interlayer insulating film formed on the semiconductor substrate, and an upper portion protruding upward from the upper surface of the interlayer insulating film. On the other hand, the first plug formed so as to penetrate the interlayer insulating film and the interlayer insulating film are formed of a different material, and the upper side wall protruding from the interlayer insulating film faces the outside of the first plug. There is provided a semiconductor device including a stopper film formed up to an outer peripheral edge portion separated by a predetermined distance and a second plug formed on the first plug.

  According to one embodiment of the present invention, a step of forming a first plug so as to penetrate a conductive layer formed on a surface layer of a semiconductor substrate in a first interlayer insulating film formed on the semiconductor substrate; Selectively removing the first interlayer insulating film to a position above the lower surface of the plug and below the upper surface of the first plug, and a first over the first interlayer insulating film and the first plug. Forming a stopper film of a material different from that of the interlayer insulating film, and on the upper surface of the first plug and the first plug while leaving the stopper film located on the side portion of the upper side wall of the first plug exposed from the interlayer insulating film. A step of removing the stopper film on the first interlayer insulating film, a step of forming a second interlayer insulating film on the first interlayer insulating film, the stopper film and the first plug, and a height higher than the stopper film. Stopper depending on selective conditions Provided is a method for manufacturing a semiconductor device, comprising: a step of removing a second interlayer insulating film using a film as a stopper to form a hole on a first plug; and a step of filling a second plug in the hole. .

  According to the present invention, the capacitance value between the plug and another electrically conductive element can be reduced.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention applied to a multilayer wiring structure configured in a memory cell region of a NAND flash memory device and a manufacturing method thereof will be described with reference to the drawings. In the description in the drawings referred to below, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.
As shown in FIG. 1, the memory cell array Ar formed in the memory cell region M of the NAND flash memory device 1 includes two select gate transistors Trs1 and Trs2 and a gap between the select gate transistors Trs1 and Trs2. Thus, NAND cell units Su including a plurality of (for example, 8: 2 to the nth power (where n is a positive number)) memory cell transistors Trm connected in series are formed in a matrix. In the NAND cell unit Su, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  In FIG. 1, the memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) are commonly connected by a word line (control gate line) WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL1. Similarly, the select gate transistors Trs2 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL2.

  A bit line contact plug CB is connected as a first plug to the drain region of the select gate transistor Trs1 (see the impurity introduction layer 2b in FIG. 3). Hereinafter, the bit line contact plug CB is abbreviated as a bit line contact CB.

  The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 via a source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region (A1 region in FIG. 1). FIG. 3 schematically shows a cross section taken along line AA of FIG. In a p-type silicon substrate 2 as a semiconductor substrate, an element isolation region Sb having an STI (Shallow Trench Isolation) structure is formed along the Y direction in FIG. A plurality of element isolation regions Sb are formed at predetermined intervals in the X direction, whereby element regions (active regions) Sa are formed separately in the X direction in FIG.

  The word line WL is formed along the X direction in FIG. 2 orthogonal to the element region Sa. The word line WL functions as a control gate electrode CG (see FIG. 3). A plurality of word lines WL are formed apart from each other in the Y direction in FIG. 2, and the plurality of word lines WL are electrically separated from each other in the Y direction by an interlayer insulating film 9 (see FIG. 3). ing.

  Further, the selection gate line SGL1 of the selection gate transistor Trs1 on the bit line contact CB side is formed along the X direction in FIG. Although not described in detail because it is not related to the features of the present embodiment, a pair of select gate lines SGL1 are formed in plan view with the bit line contact CB interposed therebetween, and an element region (active region) between the pair of select gate lines SGL1. A bit line contact CB is formed on each region Sa.

  A floating gate electrode FG (see FIG. 3) of the memory cell transistor Trm is formed on each element region Sa intersecting with the word line WL. The floating gate electrodes FG are juxtaposed in the X direction and juxtaposed in the Y direction. The word line WL is formed over the plurality of element regions Sa and the plurality of element isolation regions Sb in the X direction in FIG. 2 and over the floating gate electrodes FG arranged in parallel in the X direction. Is formed. On the element region Sa intersecting with the selection gate line SGL1, the selection gate electrode SG of the selection gate transistor Trs1 is formed and connected by the selection gate line SGL1.

Since the present embodiment is characterized by the connection method between the bit line contact CB and its upper layer wiring, the description will focus on the structure on the upper layer side of the bit line contact CB.
FIG. 3 shows a cross section of the multilayer wiring structure. FIG. 3 schematically shows a cross-sectional view when the formation region of the via hole H2 is shifted to the maximum allowable width in the Y direction.

  As shown in FIG. 3, the memory cell transistor Trm includes a gate electrode G having a laminated structure formed on a p-type silicon substrate 2 as a semiconductor substrate, and a silicon electrode located on both sides of the gate electrode G. Source / drain regions 2 a and 2 b formed on the surface layer of the substrate 2. The gate electrode G includes a gate insulating film 3, a polycrystalline silicon layer 4 doped with impurities such as phosphorus, an inter-gate insulating film 5, and polycrystalline silicon layers 6a and 6b doped with impurities such as phosphorus, A tungsten silicide layer 6c is formed on the silicon substrate 2 in order. The polycrystalline silicon layer 4 functions as the floating gate electrode FG. The conductive layer 6 includes polycrystalline silicon layers 6a and 6b and a tungsten silicide layer 6c, and functions as a control gate electrode CG and a word line WL.

  The gate electrode G of the select gate transistor Trs1 is arranged in parallel with the gate electrode G of the memory cell transistor Trm, and has substantially the same configuration as the gate electrode G of the memory cell transistor Trm, but the polycrystalline silicon layer 6a. Further, a through hole is formed in the inter-gate insulating film 5 so that the polycrystalline silicon layer 6b and the polycrystalline silicon layer 4 are structurally and electrically connected.

  A cap film 7 is formed on the gate electrodes G of the select gate transistor Trs1 and the memory cell transistor Trm. The cap film 7 is made of, for example, a silicon nitride film or a TEOS (Tetra Ethoxy Ortho Silicate) material (silicon oxide film). The side surfaces of the polycrystalline silicon layer 4, the inter-gate insulating film 5, the polycrystalline silicon layers 6a and 6b, and the tungsten silicide layer 6c are formed flush with each gate electrode G.

  Between the gate electrodes G of the two select gate transistors Trs1 adjacent in the Y direction, an impurity introduction layer 2b is formed as a conductive layer on the surface layer of the silicon substrate 2. The impurity introduction layer 2b is a layer into which an n-type impurity is ion-implanted.

  An interlayer insulating film 9 is formed so as to cover the cap film 7 and the side surface of each gate electrode G. The interlayer insulating film 9 is made of a TEOS-based material (silicon oxide film), and its upper surface 9 a is located above the upper end surface of the cap film 7.

  A contact hole H1 is provided in the interlayer insulating film 9 immediately above the impurity introduction layer 2b, and a bit line contact CB is formed in the contact hole H1. As shown in FIG. 2, the bit line contact CB is formed in a circular shape in plan view. It may be formed in an elliptical shape. An interlayer insulating film 9 is buried between the gate electrode G of the select gate transistor Trs1 and the bit line contact CB, and the bit line contact CB does not have a so-called self-aligned contact structure.

  The bit line contact CB is made of, for example, polycrystalline silicon doped with impurities, and is formed upward from the upper surface of the impurity introduction layer 2b. The upper portion is above the gate electrode G, and further, the interlayer insulating film 9 is formed so as to protrude upward from the upper surface 9a.

  That is, the bit line contact CB is formed such that the upper side wall CBa protrudes from the upper surface of the interlayer insulating film 9. The side surface of the upper side wall CBa is formed so as to be perpendicular to the upper surface 9 a of the interlayer insulating film 9.

  An interlayer insulating film 10 is formed on part of the bit line contact CB, part of the stopper insulating film 11, and on the interlayer insulating film 9. The interlayer insulating film 10 is formed of the same material (TEOS silicon oxide film) as the interlayer insulating film 9.

  A stopper insulating film 11 is formed on the side portion of the upper side wall CBa of the bit line contact CB. The stopper insulating film 11 is formed of a material different from the interlayer insulating films 9 and 10 (a material that can obtain high selectivity with the interlayer insulating film 10 during the etching process: for example, a silicon nitride film).

  The stopper insulating film 11 covers the upper side wall CBa from the upper peripheral end CBb which is the upper end of the side peripheral surface CBc of the bit line contact CB along the side surface of the upper side wall CBa of the bit line contact CB. The upper and outer surfaces of the interlayer insulating film 9 are curved so that the upper and outer surfaces thereof are convex upward.

  Further, referring to FIG. 2 as well, the stopper insulating film 11 includes an outer peripheral edge portion (outer peripheral end portion) of the stopper insulating film 11 located in a predetermined range (predetermined distance) outside and above the upper peripheral end portion CBb. ) It is formed in a curved shape whose upper outer surface is convex upward until 11a.

  As shown in FIG. 3, the stopper insulating film 11 is formed so as to cover a part of the upper surface 9a of the interlayer insulating film 9, and as shown in FIG. 2, the outer peripheral edge 11a is a select gate transistor in the Y direction. It is formed above the side wall of the gate electrode G of Trs1, and is formed so as to cover the side end of the gate electrode G.

  When forming a via plug 12 to be described later, it is necessary to form a via hole H2 on the bit line contact CB. However, if misalignment occurs in the Y direction when the via hole H2 is formed, the side surface of the gate electrode G is formed. There is a possibility that a hole reaching up to may be formed.

  Therefore, the stopper insulating film 11 is formed so that the outer peripheral edge portion 11a covers the side end portion of the gate electrode G of the selection gate electrode Trs1. Thus, if the cap film 7 is formed of a material having high selectivity (for example, a silicon nitride film) between the interlayer insulating films 9 and 10, even if the interlayer insulating film 10 is etched, the stopper insulating film 11 In addition, the etching process can be stopped on the upper surface of the cap film 7, and the above-described problems can be prevented.

  Further, as shown in FIG. 2, the stopper insulating film 11 is divided in the X direction between the side portions of the upper side walls CBa of the plurality of bit line contacts CB. An interlayer insulating film 10 is formed in this divided region. Since the relative dielectric constant of the silicon oxide film constituting the interlayer insulating film 10 is lower than the relative dielectric constant of the silicon nitride film constituting the stopper insulating film 11, the capacitance value between the adjacent bit line contacts CB is reduced. be able to.

  On the bit line contact CB and the stopper insulating film 11, a Via plug 12 is configured as a second plug. The Via plug 12 includes a barrier metal film 12a made of, for example, a Ti / TiN laminated film and a metal film 12b made of, for example, tungsten (W). The entire side surface of the Via plug 12 is covered with the interlayer insulating film 10.

  On the via plug 12, a wiring layer 13 is formed along the Y direction. An interlayer insulating film 14 is formed on the wiring layer 13, and the bit line BL is connected through a via plug 15 formed in the interlayer insulating film 14. Since this structure is not directly related to the feature of this embodiment, its detailed description is omitted.

  In the conventional technology, for example, as shown in Patent Document 1, if a silicon nitride film is formed on the entire surface of the side wall peripheral surface CBc of the bit line contact CB, the relative dielectric constant cannot be suppressed, and the bit line contact CB. Since the capacitance value between the gate electrode G and the gate electrode G increases, it is not preferable. In addition, for example, when Patent Document 2 is applied, if the etching stop layer is formed over the entire side in the plane direction with respect to the side portion of the upper side wall CBa, the bit line contact CB and other electrical components are disposed. Since the capacitance value increases similarly, it is not preferable.

  According to the structure according to the present embodiment, the stopper insulating film 11 is formed only up to the outer peripheral edge portion 11a located at a predetermined distance around the bit line contact CB along the side wall CBa above the bit line contact CB. The capacitance value between other electrical components can be suppressed.

<About manufacturing method>
Hereinafter, a method of manufacturing the multilayer wiring structure on the upper layer of the gate electrode of such a flash memory device will be described with reference to FIGS.

  Note that a method for forming the gate electrode G is omitted because it is not related to the features of the present embodiment. As shown in FIG. 4, the gate electrode G is formed on the silicon substrate 2, the cap film 7 is formed on the gate electrode G, and the gate electrode G and the cap film 7 are divided in the X direction. An n-type impurity is ion-implanted into the surface layer of the silicon substrate 2 by an ion implantation technique toward the dividing region to form the source / drain region 2a and the impurity introduction layer 2b.

  Next, a silicon oxide film such as a TEOS-based silicon oxide film or BPSG (Boro-Phospho Silicate Glass) is used as the interlayer insulating film 9 so as to cover the silicon substrate 2, the cap films 7, and the gate electrodes G and the side surfaces. Then, a contact hole H1 penetrating above the impurity introduction layer 2b is formed in the interlayer insulating film 9, a bit line contact CB is buried in the contact hole H1, and the upper part of the interlayer insulating film 9 and the bit line contact CB is formed. Planarization is performed by a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 5, the interlayer insulating film 9 is dry-etched using a condition that provides a high selection ratio with respect to the material of the bit line contact CB, so that the height of the upper surface CBd of the bit line contact CB Also, the upper surface 9a of the interlayer insulating film 9 is lowered by a predetermined height (for example, 1000 mm). Then, the side wall surface of the upper side wall CBa of the bit line contact CB is exposed in the direction perpendicular to the surface of the silicon substrate 2.

Next, as shown in FIG. 6, a stopper insulating film 11 is formed so as to cover the interlayer insulating film 9 and the bit line contact CB. The stopper insulating film 11 is a material different from that of the interlayer insulating film 9, for example, a silicon nitride film (for example, Si ₃ N ₄ ).

  Next, as shown in FIG. 7, the stopper insulating film 11 is dry-etched and etched back under conditions having high selectivity between the interlayer insulating film 9 and the bit line contact CB and the stopper insulating film 11. Then, the stopper insulating film 11 remains from the upper peripheral end portion CBb of the bit line contact CB to the upper side wall CBa along the side peripheral surface of the side wall upper portion CBa so that the upper outer surface is convex upward. In plan view, as shown in FIG. 2, the stopper insulating film 11 has an outer peripheral edge that is spaced by a predetermined range (predetermined distance) outward from the outer periphery of the upper side wall CBa of the bit line contact CB. It remains up to the part 11a.

  As shown in FIG. 2, the stopper insulating film 11 remains in a circular shape in plan view with respect to the side portion of the upper side wall CBa of the bit line contact CB in which the outer peripheral edge portion 11a is arranged in the X direction. The stopper insulating film 11 is divided between the side portions of the upper side wall CBa of the plurality of bit line contacts CB.

Next, as shown in FIG. 8, an interlayer insulating film 10 made of, for example, a TEOS-based silicon oxide film (SiO ₂ ) film is formed on the interlayer insulating film 9, the stopper insulating film 11, and the bit line contact CB. That is, the interlayer insulating film 10 is formed between the stopper insulating films 11 divided in the previous step. Therefore, since the relative dielectric constant of the interlayer insulating film 10 is lower than the relative dielectric constant of the stopper insulating film 11, the capacitance value between adjacent bit line contacts CB can be suppressed.

  Next, as shown in FIG. 9, a resist 15 is applied on the interlayer insulating film 10 and the resist 15 is patterned. Next, as shown in FIG. 10, a via hole H2 is formed by etching using the patterned resist 15 as a mask by an RIE (Reactive Ion Etching) method. At this time, during the etching process, the interlayer insulating film 10 is etched under a condition having high selectivity with respect to the material of the bit line contact CB and the stopper insulating film 11, but the normal process of etching the film thickness of the interlayer insulating film 10 is performed. An over-etching process in which the processing time is increased by about 50% with respect to the time is performed. This is for reliably exposing the upper surface of the bit line contact CB.

  In this case, misalignment of the mask occurs when the pattern of the resist 15 is formed, and the via hole H2 is deviated from the formation range W1 of the bit line contact CB within the predetermined range around the bit line contact CB (see the range W2). However, since the stopper insulating film 11 acts as a stopper for the etching process when the interlayer insulating film 10 is etched, there is no possibility that the via hole H2 penetrates to the upper part or the side part of the gate electrode G formed below. be able to.

  FIG. 11 schematically shows a cross-sectional view when the formation region of the via hole H2 is shifted to the maximum allowable range in the Y direction. As shown in FIG. 11, when the mask misalignment occurs and the via hole H2 is formed, the lower end surface of the via hole H2 is formed along the curved surface of the upper outer surface of the stopper insulating film 11. Next, a barrier metal film 12a made of, for example, a Ti / TiN laminated film is formed in the via hole H2 by sputtering.

  Next, as shown in FIG. 3, a metal film 12b is formed on the barrier metal film 12a and planarized by a CMP method. That is, the Via plug 12 is formed by the damascene method. Next, a wiring layer 13 is formed on the via plug 12 and the interlayer insulating film 10. Next, an interlayer insulating film 14, a via plug 15, and a bit line BL are formed on the wiring layer 13. Since this process is not directly related to the present embodiment, detailed description thereof is omitted.

  If the via hole H2 penetrates to the upper part or the side part of the gate electrode G located below the via hole H2, the barrier metal film 12a and the metal film 12b are formed in the via hole H2. Sometimes the electrical components of the gate electrode G and the Via plug 12 are short-circuited. In the present embodiment, since the stopper insulating film 11 is formed up to the outer peripheral edge portion 11a separated by a predetermined distance toward the outside of the bit line contact CB along the periphery of the sidewall upper portion CBa of the bit line contact CB. Even if mask misalignment occurs, there is no possibility of short circuit, and device failure can be prevented.

  According to the manufacturing method according to such an embodiment, the impurity introduction layer 2b is formed on the surface layer of the silicon substrate 2, the interlayer insulating film 9 is formed on the impurity introduction layer 2b, and penetrates through the impurity introduction layer 2b. A contact hole H1 is formed, a bit line contact CB is embedded in the contact hole H1, and an interlayer insulating film 9 is formed up to an upper surface 9a above the upper surface of the cap film 7 and below the upper surface CBd of the bit line contact CB. The stopper insulating film 11 is formed on the upper surface 9a of the interlayer insulating film 9 and the bit line contact CB, and the stopper insulating film 11 is dry-etched to dry the stopper insulating film 11 over the bit line contact CB. The interlayer insulating film 9, the stopper insulating film 11, and the bit line contact are left to a predetermined range on the side of the side wall CBa. An interlayer insulating film 10 is formed on B, and the interlayer insulating film 10 is etched by the RIE method under a condition having high selectivity with respect to the bit line contact CB and the stopper insulating film 11, thereby forming a via hole H2. A via plug 12 is formed in the via hole H2. For this reason, even if a mask misalignment occurs when forming the via hole H2, the etching process is stopped by the stopper insulating film 11, and the via hole H2 may penetrate below the side wall CBa above the bit line contact CB. Disappears. Thus, the via plug 12 can be configured not to structurally contact the gate electrode G, and the reliability of the device can be improved.

  Further, in order to form the stopper insulating film 11 so as to cover the side end surface of the gate electrode G in a plane, located above the gate electrode G of the selection gate transistor Trs1, the interlayer insulating films 9, 10 and the cap film 7 If the interlayer insulating films 9 and 10 can be etched under conditions with high selectivity between them, a mask misalignment will occur greatly when the via hole H2 is formed, and the interlayer insulating film 9 is temporarily etched. However, the etching process is stopped at the upper part of the cap film 7, and the via hole H2 can be prevented from reaching the gate electrode G, so that the reliability of the device can be maintained.

  Further, since the stopper insulating film 11 is formed only on the upper side wall CBa, not the entire side peripheral surface CBc (the entire side wall surface) of the bit line contact CB, the capacitance value between the bit line contact CB and the gate electrode G is formed. Can be suppressed.

  Moreover, since the stopper insulating film 11 is formed only within a predetermined range in plan from the upper side wall CBa of the bit line contact CB, the capacitance value between other electrical components adjacent in plan can be suppressed. . In particular, since the stopper insulating film 11 is divided between the two adjacent bit line contacts CB, the capacitance value between the two adjacent bit line contacts CB can be suppressed.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.

The diameter of the bit line contact CB and the diameter of the Via plug 13 may be formed with the same dimension, or one of them may be formed with a larger dimension.
Although applied to the bit line contact plug CB and the Via plug 12, it may be applied to other plugs such as a source line contact plug.

  After the planarization process by the CMP method, the interlayer insulating film 9 is removed to the height position of the upper surface 9a by dry etching. Instead of this, the interlayer insulating film can be similarly obtained only by performing the planarization process by the CMP method. The top of 9 can be dropped.

Although the embodiment in which the stopper insulating film 11 is formed of a silicon nitride film has been described, instead of this, other silicon such as impurity-doped or impurity-undoped polycrystalline silicon, amorphous silicon, or single crystal silicon is used. A stopper film may be formed of a system material. As long as it is a material that can obtain high selectivity during the etching process with the interlayer insulating film 10, it may be composed of any material, whether it is an insulating film or a conductive film.
The present invention is not limited to the gate electrode G having a stacked structure, and may be applied in place of a gate electrode of a general transistor.
Although applied to the flash memory device 1, it goes without saying that it can be applied to other semiconductor devices.

1 is an electrical configuration diagram of a part of a memory cell region according to an embodiment of the present invention. A plan view schematically showing a partial structure of a memory cell region (structure diagram schematically showing an A1 region in FIG. 1) Typical longitudinal cross-sectional view along the AA line of FIG. Longitudinal sectional view of contact plug and its surrounding structure during production (Part 1) Longitudinal sectional view of contact plug and its surrounding structure during production (Part 2) Longitudinal sectional view of contact plug and its peripheral structure during production (Part 3) Longitudinal sectional view of contact plug and its surrounding structure during production (Part 4) Longitudinal sectional view of contact plug and its surrounding structure during manufacture (Part 5) Longitudinal sectional view of contact plug and its peripheral structure during manufacture (Part 6) Longitudinal sectional view of contact plug and its surrounding structure during production (Part 7) Longitudinal sectional view of the contact plug and its surrounding structure during production (Part 8)

Explanation of symbols

  In the drawings, 1 is a flash memory device (semiconductor device), 2 is a silicon substrate (semiconductor substrate), 2b is an impurity introduction layer (conductive layer), 7 is a cap film, 9 is an interlayer insulating film, and 11 is a stopper insulating film (stopper). Membrane), 11a is an outer peripheral edge, 12 is a Via plug (second plug), CB is a contact plug (first plug), CBa is an upper side wall, and G is a gate electrode.

Claims (5)

A semiconductor substrate having a conductive layer formed on a surface layer;
An interlayer insulating film formed on the semiconductor substrate;
A first plug having an upper portion protruding upward from the upper surface of the interlayer insulating film and penetrating the interlayer insulating film with respect to the conductive layer;
A stopper film formed of a material different from that of the interlayer insulating film and formed from the upper side wall protruding from the interlayer insulating film to an outer peripheral edge spaced a predetermined distance toward the outside of the first plug;
A semiconductor device comprising: a second plug formed on the first plug. A plurality of the first plugs are juxtaposed in a predetermined direction,
2. The semiconductor device according to claim 1, wherein the stopper film is formed on each of the side walls of the plurality of first plugs, and is divided between the plurality of adjacent first plugs. A gate electrode formed on the semiconductor substrate in parallel with the first plug;
A cap film formed on the gate electrode, the cap film formed of a material having high selectivity during the etching process with respect to the interlayer insulating film,
The first plug is configured such that its upper end protrudes to above the upper end of the cap film,
The stopper film is formed so that an outer peripheral edge portion thereof is positioned above a gate electrode adjacent to the first plug and covers a side end portion of the gate electrode. 2. The semiconductor device according to 2.   The semiconductor device according to claim 1, wherein the stopper film is formed of a silicon nitride film. Forming a first plug in the first interlayer insulating film formed on the semiconductor substrate so as to penetrate the conductive layer formed on the surface layer of the semiconductor substrate;
Selectively removing the first interlayer insulating film to a position above the lower surface of the first plug and to a position below the upper surface of the first plug;
Forming a stopper film on the first interlayer insulating film and the first plug with a material different from that of the first interlayer insulating film;
The stopper film on the upper surface of the first plug and on the first interlayer insulating film is removed while leaving the stopper film located on the side portion of the upper side wall of the first plug exposed from the interlayer insulating film. And a process of
Forming a second interlayer insulating film on the first interlayer insulating film, the stopper film, and the first plug;
Removing the second interlayer insulating film using the stopper film as a stopper under a condition having high selectivity with respect to the stopper film to form a hole on the first plug;
And a step of burying a second plug in the hole.

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