JP2009252924A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a stacked contact structure which enhances a contact yield. <P>SOLUTION: In a bit line contact of a NAND type flash memory, a first contact opening CH1, a second contact opening CH2a, and a third contact opening CH2b are provided, constituting a stacked contact. The first contact opening CH1 of a lower layer is disposed at a central part of the bit line contact, the second contact opening CH2a of an upper layer is disposed at a left part of the bit line contact, its central position is arranged in a left direction only by an offset of the second contact opening CH2a with respect to a central position of the bit line contact, the third contact opening CH2b of the upper layer is disposed at a right part of the bit line contact, and its central position is arranged in a right direction only by an offset of the third contact opening CH2b with respect to the central position of the bit line contact. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a stacked contact structure and a manufacturing method thereof.

  In recent years, with the progress of miniaturization and high integration of semiconductor elements, the cell area of DARM (Dynamic Random Access Memory), flash memory, and the like as semiconductor devices has been reduced. In order to cope with the reduction in the cell area, for example, a stacked contact structure in which a plurality of contacts are stacked and disposed is frequently used (see, for example, Patent Document 1).

In a semiconductor device having a stacked contact structure described in Patent Document 1 and the like, when the miniaturization progresses and the contact diameter decreases and the aspect ratio (height / diameter in the contact cross section) increases, the lower layer contact opening Seams (referred to as unfilled portions or cavities) are likely to occur in the central portion of the conductive plug embedded in the portion. When the seam is generated, there is a problem that the contact resistance between the conductive plug embedded in the upper contact opening and the conductive plug embedded in the lower contact opening becomes a predetermined value or more. Further, when the diameter of the seam is increased, there arises a problem that the contact between the conductive plug embedded in the upper contact opening and the conductive plug embedded in the lower contact opening becomes impossible.
JP-A-8-298286

  The present invention provides a semiconductor device having a stacked contact structure capable of achieving a high contact yield and a method for manufacturing the same.

  A semiconductor device of one embodiment of the present invention is provided on a first main surface of a semiconductor substrate, and has a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate, an insulating film provided on the semiconductor layer, and a first interlayer insulating layer A first conductive plug embedded in a first contact opening provided so as to penetrate the film and expose the surface of the semiconductor layer; and on the first conductive plug and the first interlayer insulating film It is provided so as to penetrate the provided second interlayer insulating film and expose the surface of the first conductive plug, and the center position is shifted in the end direction with respect to the center position of the first contact opening. And n conductive plugs embedded in n (where n is 2 or more) contact openings that are arranged and spaced apart from each other.

  Furthermore, a method for manufacturing a semiconductor device according to one embodiment of the present invention is a method for manufacturing a semiconductor device having a stacked contact structure, and includes an insulating film and a first layer between gates of transistors formed over a semiconductor substrate. Forming a first contact opening so as to penetrate the interlayer insulating film and exposing the source or drain of the transistor, burying a first conductive plug in the first contact opening, A second contact opening is formed so as to penetrate the first conductive plug and the second interlayer insulating film provided on the first interlayer insulating film and to expose the upper left end of the first conductive plug. Forming a third contact opening spaced from the second contact opening so as to penetrate the second interlayer insulating film and expose an upper right end of the first conductive plug; When the second conductive plugs buried in the second contact opening, characterized by comprising the step of embedding a third conductive plug in said third contact opening.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which has a stacked contact structure which can achieve a high contact yield, and its manufacturing method can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor device and a manufacturing method thereof according to Example 1 of the present invention will be described with reference to the drawings. 1 is a plan view showing a semiconductor device, FIG. 2 is a plan view showing a bit line contact portion, and FIG. 3 is a cross-sectional view of the semiconductor device taken along line AA of FIG. In this embodiment, two upper layer contacts are arranged on the lower layer contact of the bit line contact portion of the NAND flash memory.

  As shown in FIG. 1, the semiconductor device 70 is a NAND flash memory. The semiconductor device 70 is provided with a plurality of unit memory cell units, and bit lines BL1 to BL3 separated in the element isolation region are arranged in parallel in the horizontal direction in the drawing. A source line SL, a control line SGS, a word line WL1,..., A word line WLn, a control line SGD, a control line SGDa, and a word line WLna that cross the bit lines BL1 to BL3 are arranged in parallel in the vertical direction in the drawing. .

  A bit line contact BLC for connecting the bit line BL and the source or drain of the selection transistor is provided between the control line SGD and the control line SGDa.

  For example, in the unit memory cell portion indicated by a broken line in the drawing, a source line contact portion is provided at the intersection of the bit line BL3 and the source line SL, and a selection transistor is provided at the intersection of the bit line BL3 and the control line SGS. The memory cell transistor is provided at the intersection of the bit line BL3 and the word line WL1, the memory cell transistor is provided at the intersection of the bit line BL3 and the word line WLn, and is selected at the intersection of the bit line BL3 and the control line SGD. A transistor is provided, and a bit line contact BLC for connecting the bit line BL and the source or drain of the selection transistor is provided.

  That is, n memory cell transistors are connected in cascade between the selection transistor at the intersection of the bit line BL3 and the control line SGS and the selection transistor at the intersection of the bit line BL3 and the control line SGD.

  As shown in FIG. 2, the bit line contact BLC is provided with a first contact opening CH1, a second contact opening CH2a, and a third contact opening CH2b. The lower first contact opening CH1, the upper second contact opening CH2a, and the third contact opening CH2b constitute a stacked contact.

  The first contact opening CH1 is disposed at the center of the bit line contact BLC, has a rectangular shape with a horizontal dimension of X1 and a vertical dimension of Y1, and the center position CCH1 of the contact opening is the bit line contact BLC. Arranged at the center position.

  The second contact opening CH2a is disposed on the left side of the bit line contact BLC, has a rectangular shape with a horizontal dimension of X2 and a vertical dimension of Y2, and the center position CCH2a of the contact opening is the bit line contact BLC. The second contact opening is arranged to the left by an amount of deviation ΔX1 with respect to the center position (the center position CCH1 of the contact opening). The center position CCH2a of the contact opening is arranged at the left end of the first contact opening CH1.

  The third contact opening CH2b is disposed on the right side of the bit line contact BLC, has a rectangular shape with a horizontal dimension of X3 and a vertical dimension of Y3, and the center position CCH2b of the contact opening is the bit line contact BLC. With respect to the center position (center position CCH1 of the contact opening), the third contact opening is arranged to the right by the amount of deviation ΔX2. The center position CCH2b of the contact opening is arranged at the right end of the first contact opening CH1.

Here, the relationship between the lateral dimensions X1, X2, and X3, the longitudinal dimensions Y1, Y2, and Y3, the amount of deviation ΔX1 of the second contact opening, and the amount of deviation ΔX2 of the third contact opening,
X1 <X2 = X3 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
ΔX1> (X2) / 2 Equation (2)
ΔX2> (X3) / 2 ..... Equation (3)
X1 = 2 (ΔX1) = 2 (ΔX2) ............ Formula (4)
Y1 <Y2 = Y3 ... Formula (5)
Is set.

The distance L1 between the center position of the bit line contact BLC (center position CCH1 of the contact opening) and the right end of the second contact opening CH2a is:
L1 = ΔX1 − {(X2) / 2}> 0... Equation (6)
And
The distance L2 between the center position of the bit line contact BLC (center position CCH1 of the contact opening) and the left end of the third contact opening CH2b is:
L2 = L1 = ΔX2 − {(X3) / 2}> 0... Equation (7)
It becomes.

  For this reason, even if misalignment of the second contact opening CH2a and the third contact opening CH2b occurs with respect to the first contact opening CH1, the lower first contact opening CH1 and the upper contact opening CH1 The contact area between the second contact opening CH2a and the third contact opening CH2b can be kept constant.

  Further, the right end of the second contact opening CH2a is shifted by a distance L1 with respect to the center position CCH1 of the contact opening which is the center position of the first contact opening CH1, and the left end of the third contact opening CH2b is shifted to the first position. It is shifted by a distance L2 with respect to the center position CCH1 of the contact opening, which is the center position of one contact opening CH1.

  Therefore, when the first contact opening CH1 is miniaturized and the aspect ratio (height / diameter in the contact cross section) of the first contact opening CH1 is large, the first contact opening CH1 is embedded in the first contact opening CH1. Even if a seam (also referred to as an unfilled portion or a cavity) is generated at the center of the conductive plug, the distances L1 and L2 are set larger than (1/2) of the seam diameter, so that the influence of the seam Abnormal contact resistance and poor contact between the lower conductive plug and the upper conductive plug can be avoided.

  As shown in FIG. 3, in the semiconductor device 70, the first main surface (front surface) of the semiconductor substrate 1 made of P-type silicon is opposite to the semiconductor substrate 1 serving as the source or drain region of the memory cell transistor or selection transistor. A conductive N-type semiconductor layer 2 is provided. The semiconductor layer 2 in the bit line contact portion is provided with an N-type semiconductor layer 3 that is deeper than the semiconductor layer 2 and has the same conductivity type as the semiconductor layer 2. A first gate insulating film 4 serving as a floating gate insulating film of the memory cell transistor and a gate insulating film of the selection transistor is provided on the end portions of the semiconductor substrate 1 and the semiconductor layer 2.

  In the memory cell transistor portion, a floating gate electrode film 5 and a second gate which is a control gate insulating film are provided on the semiconductor substrate 1 between the semiconductor layers 2 and on the end portion of the semiconductor layer 2 via the first gate insulating film 4. The insulating film 6, the control gate electrode film 7, and the metal silicide film 8 are stacked.

  In the select transistor portion, the floating gate electrode film 5, the second gate insulating film 6, and the control gate electrode are disposed on the semiconductor substrate 1 between the semiconductor layers 2 and on the end portion of the semiconductor layer 2 via the first gate insulating film 4. The film 7 and the metal silicide film 8 are selectively stacked and formed, the central portion of the second gate insulating film 6 is removed by etching, and the floating gate electrode film 5 and the control gate electrode film 7 are connected. The floating gate electrode film 5 becomes a floating gate electrode, and the control gate electrode film 7 and the metal silicide film 8 become control gate electrodes.

  An insulating film 9 is provided at one end of the gate of the selection transistor. An insulating film 10 as a side wall insulating film is provided at both ends of the gate of the memory cell transistor and the other end of the gate of the selection transistor. An insulating film 11 is buried between the gates of the memory cell transistors with an insulating film 10 interposed therebetween. An insulating film 12 is provided between the gates of the selection transistors via an insulating film 9, and an insulating film 13 is embedded on the insulating film 12.

  An insulating film 14 and an interlayer insulating film 15 are stacked on the gate of the memory cell transistor, the gate of the selection transistor, the insulating film 11, and the insulating film 13. In the bit line contact portion, a first contact opening CH1 is provided so as to penetrate the interlayer insulating film 15, the insulating film 14, the insulating film 13, and the insulating film 12 and expose the semiconductor layer 2. A first conductive plug 17 is embedded in the first contact opening CH1. A barrier metal film 16 is provided below and at the end of the first conductive plug 17.

  An interlayer insulating film 18 is provided on the interlayer insulating film 15 and the first conductive plug 17. On the first conductive plug 17, the second contact opening CH2a and the third contact opening CH2b are formed so as to penetrate the interlayer insulating film 18 and expose the first conductive plug 17. Is done. A second conductive plug 20 is embedded in the second contact opening CH2a. A third conductive plug 21 is embedded in the third contact opening CH2b. A barrier metal film 19 is provided on the lower and end portions of the second conductive plug 20 and the third conductive plug 21.

  A metal wiring 23 as a bit line BL is provided on the interlayer insulating film 18, the second conductive plug 20, and the third conductive plug 21. A barrier metal film 22 is provided below the metal wiring 23. An insulating film 24 is provided on the metal wiring 23.

  Next, the seam generated in the lower conductive plug will be described with reference to FIG. FIG. 4 is a diagram showing the relationship between the diameter of the contact opening and the seam diameter.

  As shown in FIG. 4, in the relationship between the diameter of the contact opening and the seam diameter, the increase in the size of the seam diameter and the variation width is relatively small even when the diameter of the contact opening is reduced. On the other hand, when the aspect ratio of the contact opening is large (for example, 7 to 10), the size of the seam diameter and the variation width are greatly increased. The seam diameter varies depending on the material of the conductive plug to be embedded and the formation method, but is likely to occur when the aspect ratio of the contact opening is 5 or more, for example.

Next, the yield of stacked contacts will be described with reference to FIG. FIG. 5 is a diagram showing the contact chain yield with respect to the displacement amount of the upper layer contact. Here, the number of contact chain is 10 ^6. One upper contact opening is provided on the lower contact opening. The aspect ratio of the lower contact opening is 10, the upper diameter of the lower contact opening is 60 nm, and the lower diameter of the upper contact opening is 40 nm.

  As shown in FIG. 5, when there is no deviation of the upper layer contact with respect to the lower layer contact (when the deviation amount of the upper layer contact is 0 (zero)), the contact chain yield decreases due to the influence of the seam generated in the lower layer conductive plug. When the displacement of the upper layer contact with respect to the lower layer contact increases, the seam generated in the lower layer conductive plug and the conductive plug embedded in the upper layer contact opening begin to separate, and the contact chain yield increases. The contact chain yield becomes the maximum value when the influence of the seam is eliminated, for example, when the amount of deviation of the upper layer contact is 20 nm. Further, when the amount of displacement of the upper layer contact with respect to the lower layer contact is increased, the influence of the seam is eliminated, but the contact area between the lower layer contact and the upper layer contact is decreased, thereby reducing the contact chain yield.

  In this embodiment, based on the facts found in FIG. 4 and FIG. 5, considering the size of the seam diameter generated in the first conductive plug 17 embedded in the first contact opening CH1 in the lower layer, The shape of the second contact opening CH2a and the third contact opening CH2b in the upper layer, the center position of the bit line contact BLC (the center position CCH1 of the contact opening), and the right end of the second contact opening CH2a The distance L1 and the distance L2 between the center position of the bit line contact BLC (contact opening center position CCH1) and the left end of the third contact opening CH2b are set to optimum values.

  Next, a method for manufacturing a semiconductor device will be described with reference to FIGS. 6 to 9 are cross-sectional views showing the manufacturing process of the semiconductor device.

  As shown in FIG. 6, first, after forming the first gate insulating film 4, the floating gate electrode film 5, and the second gate insulating film 6 on the semiconductor substrate 1, the second gate at the center of the select transistor portion is formed. The gate insulating film 6 is selectively etched. The reason why the second gate insulating film 6 is selectively etched is that the floating gate electrode film 5 and the control gate electrode film 7 are connected to make the gate of the selection transistor a single layer gate.

  Here, illustration and description of wells, channel regions and the like formed in the semiconductor substrate 1 are omitted. The first gate insulating film 4 is formed as a tunnel oxide film, for example, 8 nm. For example, a polycrystalline silicon film having a thickness of 80 nm is formed using the floating gate electrode film 5 as a floating gate. Using the second gate insulating film 6 as an interpoly insulating film, for example, an ONO film is formed to a thickness of 12 nm.

  After forming the control gate electrode film 7 and the insulating film (not shown) on the second gate insulating film 6, a resist pattern (not shown) is formed using a well-known lithography method. Using this resist pattern as a mask, the insulating film, the control gate electrode film 7, the second gate insulating film 6, and the floating gate electrode film 5 are continuously etched by, for example, RIE (Reactive Ion Etching) method to The gate of the selection transistor is formed.

  Alternatively, after etching the insulating film using this resist pattern as a mask, the control gate electrode film 7, the second gate insulating film 6, and the floating gate electrode film 5 may be etched using the insulating film as a mask. Here, using the control gate electrode film 7 as a control gate, for example, a polycrystalline silicon film is formed to a thickness of 100 nm. For example, a silicon nitride film (SiN film) having a thickness of 80 nm is formed as a mask material during gate processing of the insulating film.

  Using the insulating film, the control gate electrode film 7, the second gate insulating film 6, and the floating gate electrode film 5 as a mask, the N-type semiconductor layer 2 having a conductivity type opposite to that of the semiconductor substrate 1 is formed by, for example, arsenic ion implantation and heat treatment. Form. Further, between the select transistors, an N semiconductor layer 3 having a conductivity type opposite to that of the semiconductor substrate 1 is formed on the surface of the semiconductor substrate 1 by, for example, arsenic ion implantation and heat treatment. The semiconductor layer 2 becomes the source or drain of the memory cell transistor and the selection transistor.

  An insulating film 10 serving as a side wall insulating film is formed on the side surface of the gate of the memory cell transistor and one side surface of the gate of the selection transistor. An insulating film 11 is buried between the gates of the memory cell transistors and between the gates of the memory cell transistors and the gates of the selection transistors via the insulating film 10. An insulating film 12 is formed on the other side surface of the gate of the selection transistor (between the gates of the selection transistor). An insulating film 13 is buried between the gates of the select transistors with the insulating film 12 interposed therebetween.

  After selectively removing the insulating film on the control gate electrode film 7 until the control gate electrode film 7 is exposed, a cobalt (Co) film is deposited using, for example, a sputtering method, and then heat-treated at about 800 ° C. in a nitrogen atmosphere. To form a metal silicide film 8 on the control gate electrode film 7. With this metal silicide film 8, the sheet resistance of the word line WL is set to 10Ω / □ or less, for example. Here, cobalt (Co) is used, but other metals (for example, nickel (Ni)) may be used.

  An insulating film 14 and an interlayer insulating film 15 are stacked on the insulating film 11, the insulating film 12, the insulating film 13, and the metal silicide film 8. A resist film 31 is provided on the interlayer insulating film 15 for forming the first contact opening CH1 by using a well-known lithography method.

  Next, as shown in FIG. 7, using the resist film 31 as a mask, the interlayer insulating film 15, the insulating film 14, the insulating film 13, and the insulating film 12 are etched by, eg, RIE to form the first contact opening CH1. To do. After stripping the resist film 31 and removing the RIE damage, a barrier metal film 16 and a first conductive plug 17 are stacked on the first contact opening CH1 and the interlayer insulating film 15. After the barrier metal film 16 and the first conductive plug 17 are stacked, the barrier metal film 16 and the first conductive plug 17 are polished by, for example, a CMP (Chemical Mechanical Polishing) method until the interlayer insulating film 15 is exposed and flattened. Turn into.

  Subsequently, as shown in FIG. 8, after the post-CMP treatment, an interlayer insulating film 18 is formed on the interlayer insulating film 15 and the first conductive plug 17. A resist film 32 is provided on the interlayer insulating film 18 for forming the second contact opening CH2a and the third contact opening CH2b by using a well-known lithography method.

  Then, as shown in FIG. 9, using the resist film 32 as a mask, the interlayer insulating film 18 is etched by, eg, RIE to form the second contact opening CH2a and the third contact opening CH2b. After the resist film 31 is peeled off, the barrier metal film 19 and the conductive plug are stacked on the second contact opening CH2a, the third contact opening CH2b, and the interlayer insulating film 18.

  After the barrier metal film 19 and the conductive plug are stacked, the barrier metal film 19 and the conductive plug are polished and planarized by, for example, a CMP method until the interlayer insulating film 18 is exposed. As a result, the second conductive plug 20 is embedded in the second contact opening CH2a, and the third conductive plug 21 is embedded in the third contact opening CH2b.

  After the barrier metal film 22, the metal wiring 23, and the insulating film 24 are formed, an interlayer insulating film and a wiring layer are formed using a known technique, thereby completing the semiconductor device 70 as a NAND flash memory.

  Here, although TiN (titanium nitride) is used for the barrier metal films 16, 19, and 22, TaN (tantalum nitride), Ti (titanium), Ta (tantalum), or Nb (niobium) is used instead. May be. In addition, a stacked metal film may be used instead of the single-layer metal film. Although W (tungsten) is used for the first conductive plug 17, Al (aluminum), Au (gold), Ag (silver), or a polycrystalline polysilicon film may be used instead. The second conductive plug 20 and the third conductive plug 21 use W (tungsten), but instead use Cu (copper), Al (aluminum), Au (gold), Ag (silver), or the like. It may be used.

  As described above, in the semiconductor device and the manufacturing method thereof according to the present embodiment, the first contact opening CH1 and the second contact opening CH2a constituting the stacked contact are provided in the bit line contact BLC of the NAND flash memory. , And a third contact opening CH2b is provided. The lower first contact opening CH1 is disposed at the center of the bit line contact BLC, has a rectangular shape with a lateral dimension of X1 and a longitudinal dimension of Y1, and is disposed at the center position of the bit line contact BLC. . The upper second contact opening CH2a is disposed on the left side of the bit line contact BLC, has a rectangular shape with a horizontal dimension of X2 and a vertical dimension of Y2, and the center position CCH2a of the contact opening is the bit line contact. The second contact opening is arranged to the left by a deviation amount ΔX1 with respect to the center position of the BLC. The upper third contact opening CH2b is disposed on the right side of the bit line contact BLC, has a rectangular shape with a horizontal dimension of X3 and a vertical dimension of Y3, and the center position CCH2b of the contact opening is the bit line contact. The third contact opening is arranged to the right by a deviation amount ΔX2 with respect to the center position of the BLC. The vertical dimension of the second contact opening CH2a and the third contact opening CH2b is larger than the vertical dimension of the first contact opening CH1. A first conductive plug 17 is embedded in the first contact opening CH1. A barrier metal film 16 is provided below and at the end of the first conductive plug 17. A second conductive plug 20 is embedded in the second contact opening CH2a. A third conductive plug 21 is embedded in the third contact opening CH2b. A barrier metal film 19 is provided on the lower and end portions of the second conductive plug 20 and the third conductive plug 21.

For this reason, the first contact opening CH1 is miniaturized, the aspect ratio of the first contact opening CH1 is increased, and the first conductive plug 17 embedded in the first contact opening CH1 has a central portion. Even if the seam occurs, the right end of the second contact opening CH2a is shifted by the distance L1 with respect to the center position CCH1 of the contact opening, and the left end of the third contact opening CH2b is set to the center position CCH1 of the contact opening. On the other hand, since the distance L2 is shifted, it is possible to prevent the contact resistance abnormality and contact failure between the lower conductive plug and the upper conductive plug due to the influence of the seam. Even if the second contact opening CH2a and the third contact opening CH2b are misaligned with respect to the first contact opening CH1, the lower first contact opening CH1 and the upper contact Since the contact area between the second contact opening CH2a and the third contact opening CH2b can be kept constant, the contact resistance between the lower conductive plug and the upper conductive plug can be kept constant. The second contact opening CH2a and the third contact opening CH2b, which are the contact openings, are arranged and formed along the bit line BL, but are not necessarily limited thereto. For example, it may be arranged in parallel so as to be orthogonal to the bit line BL. In addition, two upper layer contact openings are provided on the first contact opening CH1, but the center position is shifted from the center position of the first contact opening CH1, and three or more formed at a distance from each other. An upper contact opening may be provided. Furthermore, although the shape of the contact opening is rectangular, it is not necessarily limited to this. For example, the shape may be a square or a round shape.

  Next, a semiconductor device and a manufacturing method thereof according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 10 is a cross-sectional view showing a semiconductor device, and FIG. 11 is a cross-sectional view showing a manufacturing process of the semiconductor device. In this embodiment, a conductive plug having a U-shape is provided in the contact opening in the lower layer of the bit line contact portion of the DRAM.

  As shown in FIG. 10, the semiconductor device 71 is provided with a plurality of memory cell transistors on the semiconductor substrate 1. The semiconductor device 71 is a DRAM (Dynamic Random Access Memory) provided with a plurality of memory cell transistors, a peripheral circuit (not shown), and an input / output circuit. MIS transistors are used as the transistors constituting the peripheral circuit and the input / output circuit, and Nch MIS transistors are used as the memory cell transistors. A MOS transistor may be used instead of the MIS transistor.

  The MIS transistor is also called a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The MOS transistor is also called a MISFET (Metal Oxide Semiconductor Field Effect Transistor). The MIS transistor and the MOS transistor are also called insulated gate field effect transistors.

  In the semiconductor device 71, a gate insulating film 43, a gate electrode film 44, a metal silicide film 45, and an insulating film 46 are stacked on the semiconductor substrate 1 made of P-type silicon. The gate insulating film 43, the gate electrode film 44, and the metal silicide film 45 constitute the gate of the memory cell transistor. A gate insulating film 43, a gate electrode film 44, a metal silicide film 45, and an insulating film 46 are stacked on a shallow trench isolation (STI) 41 embedded in the first main surface (front surface) of the semiconductor substrate 1, and a gate electrode The film 44 and the metal silicide film 45 are used as wiring.

  On the surface of the semiconductor substrate 1 between the gate insulating film 43 and between the gate insulating film 43 and the shallow trench isolation (STI) 41, an N-type semiconductor layer 42 having a conductivity type opposite to that of the semiconductor substrate 1 is provided. . An insulating film 47 as a sidewall insulating film is provided on the side surfaces of the gate insulating film 43, the gate electrode film 44, the metal silicide film 45, and the insulating film 46 that are stacked. An insulating film 48 is formed on the N-type semiconductor layer 42, the shallow trench isolation (STI) 41, the insulating film 46, and on the side surface of the insulating film 47. An interlayer insulating film 49 is provided on the insulating film 48.

  In the bit line contact portion between the gates of the memory cell transistors, a first contact opening CH1 is provided so as to penetrate the interlayer insulating film 49 and the insulating film 48 and expose the N-type semiconductor layer 42. The first contact opening CH1 is provided with a first conductive plug 51 having a U-shape. A barrier metal film 50 is provided on the lower and outer end portions of the first conductive plug 51.

  An interlayer insulating film 52 is formed on the first conductive plug 51 and the interlayer insulating film 49. In the bit line contact portion between the gates of the memory cell transistors, the second contact opening CH2a and the third contact opening CH2b pass through the interlayer insulating film 52 and expose the first conductive plug 51. Provided. The second contact opening CH2a is provided on the U-shaped left portion of the first conductive plug 51. The third contact opening CH2b is provided on the U-shaped right portion of the first conductive plug 51.

  A second conductive plug 54 is embedded in the second contact opening CH2a, and a third conductive plug 55 is embedded in the third contact opening CH2b. A barrier metal film 53 is provided on the lower and end portions of the second conductive plug 54 and the third conductive plug 55.

  On the second conductive plug 54 and the third conductive plug 55, a metal wiring 57 connected to the bit line is provided. A barrier metal film 56 is provided below the metal wiring 57. An insulating film 58 is provided on the metal wiring 57 and the interlayer insulating film 52.

  Here, the shapes and positional relationships of the first contact opening CH1, the second contact opening CH2a, and the third contact opening CH2b in the present embodiment are the same as those in the first embodiment. A second contact opening CH2a provided on the left portion of the first conductive plug 51 having a U-shape embedded in the first contact opening CH1, and a U embedded in the first contact opening CH1. The third contact opening CH2b provided on the right part of the first conductive plug 51 having the mold shape is arranged symmetrically with respect to the center position of the first contact opening CH1.

  For this reason, even if misalignment of the second contact opening CH2a and the third contact opening CH2b occurs with respect to the first contact opening CH1, the lower first contact opening CH1 and the upper contact opening CH1 The contact area between the second contact opening CH2a and the third contact opening CH2b can be kept constant.

  Next, a method for manufacturing a semiconductor device will be described with reference to FIG. FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device.

  As shown in FIG. 11, first, shallow trench isolation (STI) 41 is embedded in the surface of the semiconductor substrate 1 made of P-type silicon. On the semiconductor substrate 1 and the shallow trench isolation (STI) 41, a gate insulating film 43, a gate electrode film 44, a metal silicide film 45, and an insulating film 46 are stacked. A reverse conductivity type N-type semiconductor layer 42 is formed on the surface of the semiconductor substrate 1 between the gate insulating film 43 and between the gate insulating film 43 and the shallow trench isolation (STI) 41. An insulating film 47 as a sidewall insulating film is formed on the side surfaces of the gate insulating film 43, the gate electrode film 44, the metal silicide film 45, and the insulating film 46. An insulating film 48 is formed on the N-type semiconductor layer 42, the insulating film 46, and the shallow trench isolation (STI) 41 and on the side surface of the insulating film 47, and the interlayer is formed on the insulating film 48 so that the upper part has a flat shape. An insulating film 49 is formed.

  Here, the insulating film 46 is used as a mask material for gate processing. As the insulating film 46, the insulating film 47, and the insulating film 48, for example, a silicon nitride (SiN) film is used. Although the TEOS film is used for the interlayer insulating film 49, a P-SiOC film or the like may be used instead.

  After the formation of the interlayer insulating film 49, the first insulating film CH1 is formed by etching the interlayer insulating film 49 and the insulating film 48 by, for example, RIE using the resist film as a mask. A barrier metal film 50 and a first conductive plug 51 are stacked on the first contact opening CH 1 and the interlayer insulating film 49.

  After the barrier metal film 50 and the first conductive plug 51 are stacked, the barrier metal film 50 and the first conductive plug 51 are polished and planarized by, for example, a CMP method until the interlayer insulating film 49 is exposed. As a result, the U-shaped first conductive plug 51 is embedded in the first contact opening CH1.

  Next, an interlayer insulating film 52 is formed on the first conductive plug 51 and the interlayer insulating film 49. Using the resist film as a mask, the interlayer insulating film 52 is etched by, for example, the RIE method to form a second contact opening CH2a on the U-shaped left portion of the first conductive plug 51, and the first conductive plug 51 A third contact opening CH2b is formed on the right side of the U-shape. Since the subsequent steps are the same as those in the first embodiment, illustration and description thereof are omitted.

  As described above, in the semiconductor device and the manufacturing method thereof according to this embodiment, the first contact opening CH1, the second contact opening CH2a, and the third contact opening constituting the stacked contact are used as the bit line contact of the DRAM. Contact opening CH2b is provided. The lower first contact opening CH1 is disposed at the center of the bit line contact BLC, and is disposed at the center of the bit line contact. The upper second contact opening CH2a is disposed on the left side of the bit line contact BLC and is shifted in the left direction with respect to the center position of the bit line contact. The upper third contact opening CH2b is arranged at the right part of the bit line contact, and is shifted to the right with respect to the center position of the bit line contact. The vertical dimension of the second contact opening CH2a and the third contact opening CH2b is larger than the vertical dimension of the first contact opening CH1. A first conductive plug 51 is embedded in the first contact opening CH1. A barrier metal film 50 is provided on the lower and end portions of the first conductive plug 51. A second conductive plug 54 is embedded in the second contact opening CH2a. A third conductive plug 55 is embedded in the third contact opening CH2b. A barrier metal film 53 is provided on the lower and end portions of the second conductive plug 54 and the third conductive plug 55.

  For this reason, even if misalignment of the second contact opening CH2a and the third contact opening CH2b occurs with respect to the first contact opening CH1, the lower first contact opening CH1 and the upper contact opening CH1 Since the contact area between the second contact opening CH2a and the third contact opening CH2b can be kept constant, the contact resistance between the lower conductive plug and the upper conductive plug can be kept constant.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, the first embodiment applies to a bit line contact portion of a NAND flash memory, and the second embodiment applies to a bit line contact portion of a DRAM. However, the present invention is not limited to this. For example, the present invention may be applied to a system LSI or SoC (System on a Chip) logic unit having a larger number of multilayer wirings than a memory. In the second embodiment, two upper contact openings are provided, but three or more upper contact openings may be provided.

The present invention can be configured as described in the following supplementary notes.
(Appendix 1) Provided on a first main surface of a semiconductor substrate, penetrating a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate, an insulating film and a first interlayer insulating film provided on the semiconductor layer, A first conductive plug embedded in a first contact opening provided to expose the surface of the semiconductor layer; and a second conductive plug provided on the first conductive plug and the first interlayer insulating film. The second insulating layer is provided so as to penetrate the interlayer insulating film and expose the surface of the first conductive plug, and the center position is shifted from the center position of the first contact opening in the end direction. A second conductive plug embedded in the contact opening and the second interlayer insulating film are provided so as to expose the surface of the first conductive plug, and the center position is the first contact opening. Shifted in the direction of the end with respect to the center position of the second, A third conductive plug embedded in a third contact opening disposed to face the contact opening of the first contact opening, and a direction connecting the centers of the first to third contact openings is an X direction. In the semiconductor device, the maximum dimension in the Y direction of the second and third contact dimensions is larger than the maximum dimension in the Y direction of the first contact dimension.

(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the first to third contact openings have a rectangular or square shape.

(Supplementary Note 3) A method of manufacturing a semiconductor device having a stacked contact structure, wherein the insulating film and the first interlayer insulating film are penetrated between the gates of the transistors formed on the semiconductor substrate, and the source of the transistors Alternatively, a step of forming a first contact opening so as to expose the drain, a step of embedding a first conductive plug having a U-shape in the first contact opening, and the first conductive plug And a second contact opening so as to pass through the second interlayer insulating film provided on the first interlayer insulating film and to expose the left end of the upper portion of the U-shaped shape of the first conductive plug. A third contact opening spaced from the second contact opening so as to expose the right end of the U-shaped upper portion of the first conductive plug. Shape the part Process and the the second contact openings are embedded second conductive plug, a method of manufacturing a semiconductor device including the step of embedding a third conductive plug in said third contact opening.

(Additional remark 4) The manufacturing method of the semiconductor device of Additional remark 3 with which a barrier metal film is provided in the lower part and edge part of said 1st thru | or 3rd conductive plug.

(Supplementary Note 5) The first conductive plug is W (tungsten), Al (aluminum), Au (gold), Ag (silver), or a polycrystalline polysilicon film, and the second and third conductive plugs. 5 is a method of manufacturing a semiconductor device according to appendix 4, wherein W (tungsten), Cu (copper), Al (aluminum), Au (gold), or Ag (silver).

(Additional remark 6) The said barrier metal film is a manufacturing method of the semiconductor device of Additional remark 5 which is TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Ta (tantalum), or Nb (niobium).

1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention. 1 is a plan view showing a bit line contact portion according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device along the line AA in FIG. 1. The figure which shows the relationship between the diameter of the contact opening part and seam diameter which concern on Example 1 of this invention. The figure which shows the contact chain yield with respect to the deviation | shift amount of the upper layer contact which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. FIG. 6 is a plan view showing a semiconductor device according to Example 2 of the invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 3, 42 Semiconductor layer 4 1st gate insulating film 5 Floating gate electrode film 6 2nd gate insulating film 7 Control gate electrode film 8, 45 Metal silicide films 9-14, 24, 46-48, 58 Insulating films 15, 18, 49, 52 Interlayer insulating films 16, 19, 22, 50, 53, 56 Barrier metal films 17, 51 First conductive plugs 20, 54 Second conductive plugs 21, 55 Third conductive Plug 23, 57 Metal wiring 31, 32 Resist film 41 Shallow trench isolation (STI)
43 Gate insulating film 44 Gate electrode films 70 and 71 Semiconductor devices BL1 to 3 Bit line BLC Bit line contact CH1 First contact opening CH2a Second contact opening CH2b Third contact opening CCH1, CCH2a, CCH2b Contact opening Center position SGD, SGS Control line SL Source lines WL1, WLn, WLna Word lines X1, X2, X3 Horizontal dimensions Y1, Y2, Y3 Vertical dimensions ΔX1 Deviation amount ΔX2 of second contact opening Third contact Deviation amount of opening

Claims (5)

A semiconductor layer provided on the first main surface of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate;
A first conductive plug embedded in a first contact opening provided through the insulating film and the first interlayer insulating film provided on the semiconductor layer and exposing the surface of the semiconductor layer;
The first conductive plug and the second interlayer insulating film provided on the first interlayer insulating film are provided so as to expose the surface of the first conductive plug, and the center position is the first position. N conductive plugs embedded in n (where n is 2 or more) contact openings, which are arranged to be shifted in the end direction with respect to the center position of the contact openings, and are spaced apart from each other;
A semiconductor device comprising: A semiconductor layer provided on the first main surface of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate;
A first conductive plug embedded in a first contact opening provided through the insulating film and the first interlayer insulating film provided on the semiconductor layer and exposing the surface of the semiconductor layer;
The first conductive plug and the second interlayer insulating film provided on the first interlayer insulating film are provided so as to expose the surface of the first conductive plug, and the center position is the first position. A second conductive plug embedded in the second contact opening disposed so as to be shifted in the end direction with respect to the center position of the contact opening;
The second interlayer insulating film is provided so as to expose the surface of the first conductive plug, the center position is shifted toward the end with respect to the center position of the first contact opening, and the first A third conductive plug embedded in a third contact opening disposed to face the two contact openings;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first conductive plug has a U-shape, and an interlayer insulating film is embedded in the U-shaped recess.   The semiconductor device according to claim 1, wherein the conductive plug is a metal plug, and a barrier metal film is provided at a lower part and an end part. A method of manufacturing a semiconductor device having a stacked contact structure,
Forming a first contact opening between the gate of the transistor formed on the semiconductor substrate and penetrating the insulating film and the first interlayer insulating film so as to expose the source or drain of the transistor;
Burying a first conductive plug in the first contact opening;
A second contact opening is formed so as to penetrate the first conductive plug and the second interlayer insulating film provided on the first interlayer insulating film and expose the upper left end of the first conductive plug. Forming a third contact opening spaced from the second contact opening so as to pass through the second interlayer insulating film and to expose an upper right end of the first conductive plug. Process,
Burying a second conductive plug in the second contact opening, and burying a third conductive plug in the third contact opening;
A method for manufacturing a semiconductor device, comprising:

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