JP2009164534A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an easy-to-form laminate plug structure for which the connection resistance of conductive plugs on the upper layer side and the lower layer side is reduced. <P>SOLUTION: The semiconductor device has a first conductive plug composed of impurity-containing polycrystalline silicon, a second conductive plug comprising a metal, and a connecting conductive layer connecting the first conductive plug and the second conductive plug. The connecting conductive layer has a metal silicide layer connected to the end part of the first conductive plug, and a metal layer laminated on the metal silicide layer, which is brought into contact with the end part of the second conductive plug and is constituted of the metal of the same kind as the metal that constitutes the second conductive plug. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for connecting a conductive plug.

  In a semiconductor device, as a structure for connecting conductive layers provided in different layers, a lower conductive plug connected to a lower conductive layer and an upper conductive plug connected to an upper conductive layer are stacked. The structure is known.

  For example, Patent Document 1 (Japanese Patent Laid-Open No. 11-97535) describes a structure in which a conductor layer is provided between a lower plug and an upper plug.

In addition, as an example of a semiconductor device using stacked conductive plugs, Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2007-173470) describes a DRAM having a COB (Capacitor Over Bit line) type memory cell structure. ing. In this DRAM, a capacitor constituting a memory cell and a source / drain region of a transistor are connected by stacked plugs.
JP 11-97535 A JP 2007-173470 A

  However, when the distance between adjacent plugs is close, such as a memory cell of a DRAM, in the structure described in Patent Document 1, there is a high possibility that adjacent plugs are short-circuited.

  In the DRAM having the COB type memory cell structure as described above, the conductive plug (capacitance contact plug) connected to the contact plug connected to the source / drain region and connected to the capacitor is a narrow space between the bit lines. In order to pass through the portion, the size (outer diameter) of the plug must be reduced so as not to short-circuit the adjacent bit line. Furthermore, with the recent miniaturization of design rules, the size of the capacitor contact plug needs to be further reduced. Thus, the size of the capacitor contact plug is reduced and the bottom diameter thereof is reduced, so that the electrical resistance between the capacitor contact plug and the lower-layer contact plug connected to the capacitor contact plug is increased, and the operation of the DRAM circuit is increased. There was a problem that the characteristics were affected.

  As a countermeasure, a refractory metal such as tungsten is used as a material for the capacitor contact plug instead of the conventional polycrystalline silicon.

  However, with further progress in miniaturization, when the contact area between the plugs stacked on each other decreases, there is a problem that the contact resistance cannot be sufficiently reduced only by using one of the plugs as a metal plug formed of metal. there were.

  In addition, in order to reduce the contact resistance when connecting the upper metal plug and the lower polysilicon plug, an attempt is made to form a metal silicide layer by siliciding the contact surface of the polycrystalline silicon plug. There is a problem that a short circuit occurs between adjacent plugs due to the lateral expansion of the metal silicide layer.

  Further, when forming a through hole with a high aspect ratio as in the case of forming a capacitor contact plug, in the dry etching process, the through hole sufficiently opened to the bottom of the hole is uniformly distributed over the entire semiconductor substrate. There was also a problem that it was difficult to form.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a laminated plug structure that can be easily formed with reduced connection resistance between a conductive plug on the upper layer side and a conductive plug on the lower layer side, and a method for manufacturing the same.

According to the present invention, a first conductive plug made of impurity-containing polycrystalline silicon;
A second conductive plug made of metal;
A connection conductive layer connecting the first conductive plug and the second conductive plug;
The connection conductive layer is stacked on the metal silicide layer connected to the end portion of the first conductive plug, is in contact with the end portion of the second conductive plug, and the second conductive plug is connected to the end portion of the second conductive plug. There is provided a semiconductor device including a metal layer and a metal layer made of the same kind of metal.

According to the invention, a semiconductor substrate, a MOS transistor having a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a diffusion layer provided on both sides of the gate electrode; A semiconductor device comprising: a lower electrode provided above the MOS transistor; a dielectric film provided on the lower electrode; and a capacitor having an upper electrode disposed opposite to the lower electrode through the dielectric film A device,
A first conductive plug made of impurity-containing polycrystalline silicon connected to the diffusion layer of the MOS transistor;
A second conductive plug made of metal connected to the lower electrode of the capacitor;
A connection conductive layer connecting the first conductive plug and the second conductive plug;
The connection conductive layer is made of a metal silicide layer connected to the upper end portion of the first conductive plug, and a metal of the same type as the metal that contacts the lower end portion of the second conductive plug and constitutes the second conductive plug. A semiconductor device having a stacked structure including a metal layer is provided.

According to the invention, the first interlayer insulating film is formed, the first through hole is formed in the first interlayer insulating film, and the first through hole made of impurity-containing polycrystalline silicon is formed in the first through hole. Forming a conductive plug of 1;
Forming a second interlayer insulating film, and forming a second through hole reaching the first conductive plug in the second interlayer insulating film;
Forming a first metal film so as to cover the first conductive plug exposed at the bottom of the second through hole;
A heat treatment is performed to react the impurity polycrystalline silicon constituting the first conductive plug with the first metal film to form a metal silicide layer on the first conductive plug. Removing the metal film;
Forming a second metal film so as to fill the second through-hole, removing the second metal film outside the second through-hole, and a metal layer made of the second metal film; Forming a connection conductive layer having a laminated structure including the metal silicide layer;
Forming at least one insulating film as a third interlayer insulating film, and forming a third through hole reaching the connection conductive layer in the third interlayer insulating film;
Forming a second conductive plug made of the same kind of metal as the metal constituting the metal layer of the connection conductive layer in the third through hole and in contact with the metal layer. A method is provided.

According to the invention, a semiconductor substrate, a MOS transistor having a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a diffusion layer provided on both sides of the gate electrode; A semiconductor device comprising: a lower electrode provided above the MOS transistor; a dielectric film provided on the lower electrode; and a capacitor having an upper electrode disposed opposite to the lower electrode through the dielectric film A device manufacturing method comprising:
Forming the MOS transistor on the semiconductor substrate;
A first interlayer insulating film is formed, a first through hole reaching the diffusion layer is formed in the first interlayer insulating film, and a first made of impurity-containing polycrystalline silicon is formed in the first through hole. Forming a conductive plug of
Forming a second interlayer insulating film, and forming a second through hole reaching the first conductive plug in the second interlayer insulating film;
Forming a first metal film so as to cover the first conductive plug exposed at the bottom of the second through hole;
A heat treatment is performed to react the impurity polycrystalline silicon constituting the first conductive plug with the first metal film to form a metal silicide layer on the first conductive plug. Removing the metal layer;
Forming a second metal film so as to fill the second through-hole, removing the second metal film outside the second through-hole, and a metal layer made of the second metal film; Forming a connection conductive layer having a laminated structure including the metal silicide layer;
Forming at least one insulating film as a third interlayer insulating film, and forming a third through hole reaching the connection conductive layer in the third interlayer insulating film;
Forming a second conductive plug made of the same kind of metal as the metal constituting the metal layer of the connection conductive layer in the third through hole, and in contact with the metal layer;
Forming a capacitor having a lower electrode connected to the second conductive plug. A method for manufacturing a semiconductor device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which has the laminated plug structure with easy formation, and its manufacturing method with which the connection resistance of the upper conductive plug and the lower conductive plug was reduced can be provided.

  One embodiment of a semiconductor device according to the present invention includes a conductive plug (lower layer side plug) made of impurity-containing polycrystalline silicon provided on the lower layer side, and a conductive plug (upper layer side plug) made of metal provided on the upper layer side. Have a stacked plug structure connected via a connection conductive layer. From the viewpoint of the occupied area of the laminated plug structure in the substrate plane, it is preferable that the upper layer side plug is provided directly above the lower layer side plug via the connection conductive layer.

  The connection conductive layer has a laminated structure including a metal silicide layer connected to the upper end portion of the lower layer side plug, and a metal layer that is in contact with the lower end portion of the upper layer side plug and is made of the same kind of metal as the metal constituting the upper layer side plug. have. The metal component of the metal silicide layer may be a metal different from the metal constituting the metal layer and the upper layer side plug, or the same kind of metal.

  Moreover, it is preferable that the dimension of this connection conductive layer lower end of the board | substrate plane direction is below the dimension of the board | substrate plane direction of the lower end side plug upper end. Further, it is preferable that the entire lower surface of the connection conductive layer is connected to the upper end of the lower layer side plug. Here, the dimension in the substrate plane direction at the lower end of the connection conductive layer indicates the area of the lower surface of the connection conductive layer (the area of the area where the lower surface is projected onto the substrate plane, or the outer diameter when this area is circular). The dimension in the substrate plane direction of the upper end of the plug indicates the area of the upper surface of the lower layer side plug (the area of the region where the upper surface is projected onto the substrate plane, or the outer diameter when this region is circular).

  Moreover, it is preferable that the dimension of the upper end of the connection conductive layer in the substrate plane direction is larger than the dimension of the upper layer side plug lower end in the substrate plane direction. Moreover, it is preferable that the entire lower surface of the upper layer side plug is in contact with the upper surface of the connection conductive layer. Here, the dimension of the upper end of the connection conductive layer in the direction of the substrate plane indicates the area of the upper surface of the connection conductive layer (the area of the area projected on the plane of the substrate, or the outer diameter if this area is circular). The dimension of the lower end of the plug in the substrate plane direction indicates the area of the lower surface of the upper plug (the area of the region where the lower surface is projected onto the substrate plane, or the outer diameter when this region is circular).

  Since the lower end portion of the connection conductive layer is formed of metal silicide, the contact resistance with the metal layer at the upper end portion of the connection conductive layer and the contact resistance with the lower-layer side plug made of impurity-containing polycrystalline silicon are reduced. be able to. Since the upper end portion of the connection conductive layer is formed of the same type of metal as that of the upper layer side plug, the contact resistance between the connection conductive layer and the upper layer side plug can be reduced. As a result, the connection resistance between the upper layer side contact plug and the lower layer side contact plug can be reduced.

  Further, since the entire lower surface of the connection conductive layer is connected to the upper end of the lower layer side plug, that is, the dimension in the substrate plane direction of the lower end of the connection conductive layer is equal to or less than the dimension in the substrate plane direction of the upper end of the lower layer side plug. As a result, a fine wiring structure in which a short circuit between adjacent plugs is suppressed can be obtained.

  Further, when the entire lower surface of the upper layer side plug is in contact with the upper surface of the connection conductive layer, that is, the dimension in the substrate plane direction at the upper end of the connection conductive layer is larger than the dimension in the substrate plane direction at the lower end of the upper layer side plug. The dimension of at least the lower end side of the side plug can be reduced, and a fine wiring structure in which a short circuit between the upper layer side plug and another conductive layer adjacent to the upper layer side plug is suppressed can be obtained.

  The connection conductive layer does not need to be so high in order to obtain a desired connection structure, and can be set low enough to obtain sufficient processing accuracy. Therefore, in this connection conductive layer forming step, the through hole can be formed shallowly, a metal film for forming the metal silicide layer can be formed uniformly at the bottom of the through hole, and a metal silicide layer having a uniform thickness can be formed. It can be formed easily. As a result, a contact conductive layer with a low contact resistance with the lower layer side plug can be formed.

  From this point of view, the thickness of the connection conductive layer (the length in the direction perpendicular to the substrate surface) is preferably 1/5 or less of the height of the upper plug (the length in the direction perpendicular to the substrate surface). 100 nm or less is preferable, 70 nm or less is more preferable, and 30 nm or more is preferable from the viewpoint of obtaining a desired connection structure.

  Further, by providing such a connection conductive layer, the through hole can be formed shallower by the thickness of the connection conductive layer in the upper layer side plug forming step, and the aspect ratio can be relaxed, so that the processing accuracy can be improved.

  A refractory metal selected from tungsten, titanium, nickel, molybdenum, cobalt, and the like can be used as the metal constituting the upper plug and the metal layer of the connection conductive layer.

  As the metal component of the metal silicide layer of the connection conductive layer, a refractory metal selected from tungsten, titanium, nickel, molybdenum, cobalt, and the like can be used.

  Hereinafter, as an example of a semiconductor device according to the present invention, a case where a DRAM memory cell is formed will be described.

  The memory cell structure of the DRAM in this embodiment is shown in FIG. 1 (A), FIG. 1 (B), and FIG. FIG. 2 schematically shows a plan view of a DRAM memory cell as viewed from above, and shows the structure of the lower layer side of the capacitor for the sake of simplicity. 1A shows a cross-sectional structure taken along line AA in FIG. 2, and FIG. 1B shows a cross-sectional structure taken along line BB in FIG.

  1A, FIG. 1B, and FIG. 2, 10 is a silicon substrate, 11 is an element isolation region, 12 is an N-type diffusion layer, 13 is a word wiring (gate electrode), 14 is a diffusion layer contact plug, 15 is a connection plug (connection conductive layer), 16 is a bit line contact plug, 17 is a bit line, 18 is a capacitance contact plug, 111 is a capacitor lower electrode, 112 is a dielectric film, 113 is a capacitor upper electrode, 20, 30, 40 and 50 are interlayer insulating films, 41 is a stopper insulating film (silicon nitride film), and 21 is an active region.

  As shown in FIG. 2, the element isolation region 11 is formed so as to surround the active region 21. The element isolation region 11 is formed by filling a groove formed in a predetermined pattern with an insulating film using an STI (Shallow Trench Isolation) method.

  The gate electrode 13 functions as a word line of the DRAM. The portion of the active region 21 that is not covered with the gate electrode 13 is an N-type diffusion layer 12 into which an N-type impurity has been introduced, and functions as a source / drain region of a MOS transistor that constitutes a memory cell.

  The bit line 17 is arranged so as to cross the gate electrode 13 and is connected to the N-type diffusion layer 12 located in the center of the active region 21 through the bit line contact plug 16 and the diffusion layer contact plug 14. .

  A diffusion layer contact plug 14 is connected to the N-type diffusion layer 12 at both ends of the active region 21, a connection plug 15 is connected to the upper surface of the contact plug 14, and a capacitor contact plug 18 is connected to the upper surface of the connection plug. Is connected. In the connection plug 15, the lower layer portion in contact with the diffusion layer contact plug 14 is made of metal silicide, and the upper layer portion in contact with the capacitor contact plug 18 is formed of a refractory metal made of the same material as the capacitor contact plug.

  The capacitor contact plug 18 is connected to the lower electrode 111 of the capacitor. Therefore, the lower electrode 111 of the capacitor is connected to the N-type diffusion layer 12 via the capacitor contact plug 18, the connection plug 15, and the diffusion layer contact plug 14. A dielectric film 112 is formed on the capacitor lower electrode 111, and an upper electrode 113 is provided so as to face the lower electrode through the dielectric film. The lower electrode 111, the dielectric film 112, and the upper electrode 113 serve as a capacitor. Is formed. The presence / absence of charge held in the capacitor is determined by detecting a potential fluctuation of the bit line caused by turning on the MOS transistor using the word wiring.

  An example of a method for manufacturing the memory cell structure described above will be described below.

  In the drawings referred to in the following description, FIG. (A) corresponds to a cross section taken along line AA in FIG. 2, and FIG. (B) corresponds to a cross section taken along line BB.

  First, the structure shown in FIGS. 3A and 3B is formed as follows.

  After forming an element isolation region (STI) 11 on the silicon substrate 10 using a normal method, a MOS transistor is formed.

The gate electrode 13 of the MOS transistor is formed of polycrystalline silicon (Poly-Si) or a laminated film of polycrystalline silicon and a refractory metal, and functions as a word wiring of the memory cell. This polycrystalline silicon is doped with N-type impurities such as phosphorus or P-type impurities such as boron. The diffusion layer 12 is doped with an N-type impurity such as phosphorus and functions as a source / drain of the MOS transistor. A side wall may be formed on the side surface of the gate electrode 13 with a silicon nitride film (Si ₃ N ₄ ) or the like.

Next, a first interlayer insulating film 20 made of a silicon oxide film (SiO ₂ ) is formed so as to cover the MOS transistor.

  Next, a diffusion layer contact plug 14 connected to the diffusion layer 12 is formed using a normal method. In these diffusion layer contact plugs, a contact hole reaching the diffusion layer 12 is formed in the first interlayer insulating film 20, and polycrystalline silicon doped with N-type impurities is formed so as to fill the hole. Then, it can be formed by polishing by CMP (Chemical Mechanical Polishing) method to remove the polycrystalline silicon outside the hole and planarizing the surface.

  A second interlayer insulating film 31 made of a silicon oxide film and having a thickness of about 50 nm is formed so as to cover the upper surface of the diffusion layer contact plug 14.

  As described above, the structure shown in FIGS. 3A and 3B can be obtained.

  Next, as shown in FIGS. 4A and 4B, a through hole 101 having a size equal to or smaller than the diameter of the upper surface of the diffusion layer contact plug 14 is formed on the diffusion layer contact plug 14. The upper surface of the plug 14 is exposed in the entire bottom opening of the hole. At this time, the through hole 101 is not formed on the diffusion layer contact plug 14 (the center contact plug in FIGS. 4A and 4B) for connection to the bit line. That is, the through hole 101 is formed only on the diffusion layer contact plug 14 for electrical connection with the capacitor.

Next, a cobalt (Co) layer is formed to a thickness of about 20 nm by sputtering so as to cover the bottom of the through hole 101 and the second interlayer insulating film 31, and subsequently heat treatment is performed in a nitrogen atmosphere at about 650 ° C. As a result, a cobalt silicide (CoSi) layer 102 is formed at the bottom of the through hole 101. Excess cobalt that has not reacted with the polycrystalline silicon is removed using a chemical such as sulfuric acid (H ₂ SO ₄ ). In this manner, the cobalt silicide layer 102 can be formed as shown in FIGS. 5A and 5B. According to this process, since the cobalt silicide layer 102 can be formed only at the bottom of the through hole 101, a short circuit between adjacent contact plugs due to silicidation can be prevented. Further, since the second interlayer insulating film 31 is as thin as about 50 nm, the step coverage at the time of forming the cobalt layer is good, and a cobalt silicide layer having a uniform thickness can be easily formed. Instead of cobalt, a titanium (Ti) layer may be formed by a CVD method, and then a similar heat treatment may be performed to form a titanium silicide (TiSi) layer at the bottom of the through hole 101. In addition, a silicide layer of the metal can be formed using another metal capable of forming a silicide layer.

  Next, as shown in FIGS. 6A and 6B, a tungsten (W) film 103 is filled into the through-hole 101 by the CVD method so as to cover the second interlayer insulating film 31. Form. In the drawing, the cobalt silicide layer 102 formed earlier is not distinguished from the tungsten film 103 for simplification of the drawing (the same applies to the following explanatory drawings).

  Next, as shown in FIGS. 7A and 7B, the surface of the tungsten film 103 is polished by CMP to leave the tungsten film only in the through hole 101, and is made of a cobalt silicide layer and tungsten. A connection plug 15 is formed. In this embodiment, the material of the metal layer above the connection plug is tungsten, and the metal material for forming the metal silicide layer at the bottom of the connection plug is cobalt. Although both materials are different, the same metal material may be used. Good.

  Next, as shown in FIGS. 8A and 8B, a third interlayer insulating film 32 made of a silicon oxide film having a thickness of about 60 nm is formed (in the following explanatory drawings, the second interlayer insulating film 32 is formed). The boundary between the interlayer insulating film 31 and the third interlayer insulating film 32 is omitted, and is denoted by reference numeral 30).

  Next, as shown in FIGS. 9A and 9B, a through hole 104 for forming the bit line contact plug 16 is formed on the diffusion layer contact plug 14 at the center.

  Next, as shown in FIGS. 10A and 10B, a bit having a two-layer structure including a cobalt silicide layer and a tungsten film is formed in the through hole 104 in the same manner as the formation of the connection plug 15 described above. A line contact plug 16 is formed. A titanium silicide layer or another silicide layer can be formed instead of the cobalt silicide layer, and a titanium film or another conductive film can be formed instead of the tungsten film. In the drawing, the cobalt silicide layer is not distinguished from the tungsten film for simplification of the drawing (the same applies to the subsequent explanatory drawings).

  Next, as shown in FIGS. 11A and 11B, a tungsten film is formed and patterned by using a normal method, and the bit line 17 is formed. The bit line 17 is connected to the diffusion layer 12 via the bit line contact plug 16 and the diffusion layer contact plug 14. Thereafter, a protective film such as a silicon nitride film may be formed on the upper and side surfaces of the bit line.

  Next, the structure shown in FIGS. 12A and 12B is formed as follows.

  A fourth interlayer insulating film 40 made of a silicon oxide film or the like is formed so as to cover the bit line 17. A through hole reaching the connection plug 15 is formed in the interlayer insulating film, and the upper surface of the connection plug 15 is exposed in the entire bottom opening of the hole. Next, a tungsten film is formed so as to fill this through hole. The tungsten film outside the through hole is removed by CMP to form a capacitor contact plug 18. Since the capacitor contact plug 18 is provided between the bit lines 17 as shown in FIG. 12A, it is necessary to reduce the opening size of the through hole so as not to be short-circuited with the bit line 17. However, from the viewpoint of reducing electrical resistance, it is preferable that the opening size of the upper portion of the through hole is larger than that of the lower portion, that is, the contact hole is tapered so that the opening size of the lower portion is smaller than that of the upper portion.

  The lower end of the capacitor contact plug 18 is in contact with the connection plug 15. However, since the capacitor contact plug 18 and the connection plug 15 are formed of the same metal (tungsten), the contact resistance can be reduced. Moreover, since the lower dimension of the connection plug 15 can be set to be approximately the same as the upper surface dimension of the diffusion layer contact plug 14, the contact resistance between the connection plug and the diffusion layer contact plug can be reduced.

  Further, in the processing of the through hole for forming the capacitor contact plug 18, since the connection plug 15 is provided before the through hole is formed, the through hole can be formed shallower by the height of the connection plug. Therefore, the aspect ratio of the through hole is relaxed, and the etching process is facilitated. Therefore, the occurrence of defects (for example, the hole is not completely opened to the bottom of the contact hole) can be suppressed, and the yield can be improved.

  Next, according to a normal method, an interlayer insulating film, a capacitor and the like are formed to complete a DRAM memory cell. A stopper insulating film (for example, silicon nitride film) can be provided before the formation of the interlayer insulating film (for example, silicon oxide film) for the purpose of preventing penetration during etching of the interlayer insulating film in forming the capacitor hole.

  The lower electrode 111 constituting the capacitor is connected to the capacitor contact plug 18. As described above, the capacitor contact plug 18 needs to be reduced in size in order to avoid a short circuit with the bit line 17. However, by applying the structure of the present embodiment, the capacitor contact plug 18 can be diffused. It is possible to suppress an increase in electrical resistance in the connection path between the layers.

  Hereinafter, as another embodiment, a structure in which a connection plug is provided in the connection portion between the bit line and the diffusion layer contact plug in the same manner as the connection portion between the capacitor contact plug and the diffusion layer contact plug will be described.

  First, the structure shown in FIGS. 3A and 3B is formed in the same manner as in the above embodiment.

  Next, a through hole 101 having a size equal to or smaller than the diameter of the upper surface of the diffusion layer contact plug 14 is formed on the diffusion layer contact plug 14. At this time, a through hole is simultaneously provided on the diffusion layer contact plug for the bit line. Next, in the same manner as in the above embodiment, the connection plug 15 having a laminated structure of cobalt silicide and tungsten is formed. In this manner, as shown in FIGS. 13A and 13B, the connection plugs 15 are formed on all the diffusion layer contact plugs 14.

  Next, as shown in FIGS. 14A and 14B, a third interlayer insulating film is formed so as to cover the connection plug 15.

  Next, a through hole is formed on the connection plug formed on the bit line diffusion layer contact plug so that the connection plug is exposed. A tungsten film is formed so as to fill this through hole, and the tungsten film outside the hole is removed by CMP, and the bit line contact plug 16 is placed in the hole as shown in FIGS. 15A and 15B. Form.

  With respect to the subsequent steps, DRAM memory cells can be formed in the same manner as in the above embodiment.

  In this embodiment, in addition to providing the connection plug on the capacitor diffusion layer contact plug, the connection plug is also provided on the bit line diffusion layer contact plug. Therefore, even when the dimensions of the bit line contact plug are reduced due to the influence of variations during manufacturing, an increase in electrical resistance at the connection portion can be suppressed.

  The present invention is not limited to application to a DRAM memory cell, but can be applied to any structure having a structure for connecting a plug formed of polycrystalline silicon and a plug formed of metal. In particular, in the case where the dimension of the plug formed of metal in the substrate plane direction is limited (for example, when it is necessary to reduce the dimension in order to avoid a short circuit with the adjacent wiring layer), the present invention. The electric resistance can be effectively reduced by applying.

It is sectional drawing which shows the memory cell structure of DRAM which is an example of the semiconductor device of this invention. FIG. 2 is a plan view corresponding to the memory cell structure of the DRAM shown in FIG. 1. It is sectional drawing after a series of processes for demonstrating an example of the manufacturing method of the semiconductor device by this invention. It is sectional drawing for demonstrating the process following the formation process of the structure shown in FIG. FIG. 5 is a cross-sectional view for explaining a step that follows the formation step of the structure shown in FIG. 4. FIG. 6 is a cross-sectional view for explaining a step that follows the formation step of the structure shown in FIG. 5. FIG. 7 is a cross-sectional view for explaining a step that follows the formation step of the structure shown in FIG. 6. It is sectional drawing for demonstrating the process following the formation process of the structure shown in FIG. FIG. 9 is a cross-sectional view for explaining a step that follows the formation step of the structure shown in FIG. 8. FIG. 10 is a cross-sectional view for explaining a step that follows the formation step of the structure shown in FIG. 9. FIG. 11 is a cross-sectional view for explaining a process following the structure forming process shown in FIG. 10. It is sectional drawing for demonstrating the process following the formation process of the structure shown in FIG. It is sectional drawing after a series of processes for demonstrating the other example of the manufacturing method of the semiconductor device by this invention. It is sectional drawing for demonstrating the process following the formation process of the structure shown in FIG. FIG. 15 is a cross-sectional view for explaining a step that follows the formation step of the structure shown in FIG. 14.

Explanation of symbols

10 Silicon substrate 11 Element isolation region 12 N-type diffusion layer 13 Word wiring (gate electrode)
14 Diffusion layer contact plug 15 Connection plug (connection conductive layer)
16 bit line contact plug 17 bit line 18 capacitor contact plug 20 interlayer insulating film (first interlayer insulating film)
21 active region 30 interlayer insulating film (second and third interlayer insulating films)
31 Second interlayer insulating film 32 Third interlayer insulating film 40 Interlayer insulating film (fourth interlayer insulating film)
41 Stopper insulating film 50 Interlayer insulating film 101 Through hole 102 Cobalt silicide layer 103 Tungsten film 104 Through hole 111 Capacitor lower electrode 112 Dielectric film 113 Capacitor upper electrode

Claims (10)

A first conductive plug made of impurity-containing polycrystalline silicon;
A second conductive plug made of metal;
A connection conductive layer connecting the first conductive plug and the second conductive plug;
The connection conductive layer is stacked on the metal silicide layer connected to the end portion of the first conductive plug, is in contact with the end portion of the second conductive plug, and the second conductive plug is connected to the end portion of the second conductive plug. A semiconductor device including a metal layer made of the same kind of metal as a constituent metal.   The semiconductor device according to claim 1, wherein the second conductive plug is provided directly on the first conductive plug via the connection conductive layer.   The semiconductor device according to claim 2, wherein an entire lower surface of the connection conductive layer is connected to an upper end of the first conductive plug.   4. The semiconductor device according to claim 2, wherein an entire lower surface of the second conductive plug is in contact with an upper surface of the connection conductive layer. 5.   5. The semiconductor device according to claim 1, wherein the metal silicide layer of the connection conductive layer is formed of cobalt silicide or titanium silicide, and the second conductive plug is formed of tungsten or titanium. A MOS transistor having a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a diffusion layer provided on both sides of the gate electrode; and above the MOS transistor A semiconductor device comprising: a lower electrode provided; a dielectric film provided on the lower electrode; and a capacitor having an upper electrode disposed to face the lower electrode through the dielectric film,
A first conductive plug made of impurity-containing polycrystalline silicon connected to the diffusion layer of the MOS transistor;
A second conductive plug made of metal connected to the lower electrode of the capacitor;
A connection conductive layer connecting the first conductive plug and the second conductive plug;
The connection conductive layer is made of a metal silicide layer connected to the upper end portion of the first conductive plug, and a metal of the same type as the metal that contacts the lower end portion of the second conductive plug and constitutes the second conductive plug. A semiconductor device having a stacked structure including a metal layer. A first interlayer insulating film is formed, a first through hole is formed in the first interlayer insulating film, and a first conductive plug made of impurity-containing polycrystalline silicon is formed in the first through hole. Process,
Forming a second interlayer insulating film, and forming a second through hole reaching the first conductive plug in the second interlayer insulating film;
Forming a first metal film so as to cover the first conductive plug exposed at the bottom of the second through hole;
A heat treatment is performed to react the impurity polycrystalline silicon constituting the first conductive plug with the first metal film to form a metal silicide layer on the first conductive plug. Removing the metal film;
Forming a second metal film so as to fill the second through-hole, removing the second metal film outside the second through-hole, and a metal layer made of the second metal film; Forming a connection conductive layer having a laminated structure including the metal silicide layer;
Forming at least one insulating film as a third interlayer insulating film, and forming a third through hole reaching the connection conductive layer in the third interlayer insulating film;
Forming a second conductive plug made of the same kind of metal as the metal constituting the metal layer of the connection conductive layer in the third through hole and in contact with the metal layer. Method.   The method of manufacturing a semiconductor device according to claim 7, wherein the second through hole is formed so that the upper surface of the first conductive plug is exposed in the entire bottom opening.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the third through hole is formed so that the upper surface of the connection conductive layer is exposed in the entire bottom opening. A MOS transistor having a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a diffusion layer provided on both sides of the gate electrode; and above the MOS transistor A method of manufacturing a semiconductor device comprising: a lower electrode provided; a dielectric film provided on the lower electrode; and a capacitor having an upper electrode disposed opposite to the lower electrode through the dielectric film. ,
Forming the MOS transistor on the semiconductor substrate;
A first interlayer insulating film is formed, a first through hole reaching the diffusion layer is formed in the first interlayer insulating film, and a first made of impurity-containing polycrystalline silicon is formed in the first through hole. Forming a conductive plug of
Forming a second interlayer insulating film, and forming a second through hole reaching the first conductive plug in the second interlayer insulating film;
Forming a first metal film so as to cover the first conductive plug exposed at the bottom of the second through hole;
A heat treatment is performed to react the impurity polycrystalline silicon constituting the first conductive plug with the first metal film to form a metal silicide layer on the first conductive plug. Removing the metal layer;
Forming a second metal film so as to fill the second through-hole, removing the second metal film outside the second through-hole, and a metal layer made of the second metal film; Forming a connection conductive layer having a laminated structure including the metal silicide layer;
Forming at least one insulating film as a third interlayer insulating film, and forming a third through hole reaching the connection conductive layer in the third interlayer insulating film;
Forming a second conductive plug made of the same kind of metal as the metal constituting the metal layer of the connection conductive layer in the third through hole, and in contact with the metal layer;
Forming the capacitor whose lower electrode is connected to the second conductive plug.

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