JP2002083940A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the reliability of a semiconductor device by preventing increase in leakage current of a capacitive element having an MIM structure. SOLUTION: The semiconductor device comprises a capacitive element having a metal film for an electrode. The capacitive element consists of a first capacitive element formed with a metal electrode which is in contact with an insulation film, and a second capacitive element formed with a metal electrode which is in contact with a barrier film. The metal electrode of the second capacitive element is formed thickner than that of the first capacitive element. A method of fabricating the capacitive element comprises a process of forming a metal film which becomes a lower electrode in the bottom of the capacitive element; a process of forming the insulation film; a process of forming a hole in the insulation film to expose the surface of the metal film; and a process of forming a metal film which becomes a lower electrode on the side wall and bottom face of the hole. By these processes, the lower electrode of the capacitive element is formed thicker in the bottom than in the side wall.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitance element, and more particularly to a technique effective when applied to a semiconductor device using a metal film for a lower electrode of the capacitance element.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memory)
ry) memory cell is a selection MISFET (Metal Insu
The memory cell is made smaller by the development of microfabrication technology, but the reduction in the amount of charge stored in the capacitor becomes a problem. In order to solve this problem, a method of increasing the area of the electrode by making the capacitor three-dimensional and increasing the amount of accumulated charge has been considered.

FIG. 1 shows an example of a memory cell in which a capacitive element is made three-dimensional. In this memory cell, two main regions of a semiconductor substrate 1 made of single crystal silicon or the like are divided into an active region partitioned by an isolation insulating film 2. A selection FET is formed,
Each FET comprises a gate electrode 4 formed on a main surface of a semiconductor substrate 1 with a gate insulating film 3 interposed therebetween, and a pair of semiconductor regions 5 and 6 serving as a source region and a drain region.
One semiconductor region 5 of the ET is commonly shared. The FET is covered with a first interlayer insulating film 7, and a bit line 8 formed on the first interlayer insulating film 7 and the one semiconductor region 5 are connected by a plug 9 penetrating the interlayer insulating film 7. It is connected.

The bit line 8 is covered with a second interlayer insulating film 10, a capacitor is formed on the second interlayer insulating film 10, and the lower electrode 11 of the capacitor and the other semiconductor region 6 of the FET are formed. Are connected by a plug 9 penetrating the interlayer insulating film 7 and a plug 12 penetrating the interlayer insulating film 10, respectively. The capacitive element includes a metal film upper electrode 14 and an insulator dielectric film 1 in a hole provided in a third interlayer insulating film 13.
5. MIS in which lower electrode 11 of polycrystalline silicon is laminated
(Metal-Insulator-Silicon) structure, and the capacitive element is covered with a protective insulating film 16 formed on the entire surface.

In this capacitive element, the third interlayer insulating film 1
Since the area obtained by adding the area of the bottom surface of the hole provided in 3 and the area of the side wall of the hole is used as the area of the electrode, the electrode area is enlarged as compared with the area of the bottom surface, which is the area occupied on a plane. can do. However, in order to promote further miniaturization, the amount of accumulated charge is insufficient only with such a three-dimensional capacitor. For this reason, tantalum oxide (Ta ₂ O ₅ ), strontium titanate (STO), and titanium, which are materials having a higher dielectric constant than silicon nitride (relative dielectric constant: 7 to 8) conventionally used as a dielectric film, are used. A method of increasing the amount of accumulated charges by using a high dielectric / ferroelectric material such as barium strontium acid (BST) for a dielectric film has been considered. Tantalum oxide has a relative dielectric constant of about 40, and strontium titanate and barium strontium titanate have a relative dielectric constant of about 200 to 500, so that an increase in the amount of accumulated charge can be expected.

As an example, a manufacturing process of a capacitor having a MIS structure using tantalum oxide as a dielectric will be described with reference to FIGS. First, a plug 12 made of polycrystalline silicon is formed in a predetermined region of the second interlayer insulating film 10, and a silicon nitride film to be a lower film 13a of the third interlayer insulating film 13 is formed on the entire surface. This state is shown in FIG. Subsequently, a silicon oxide film to be the upper layer film 13b of the third interlayer insulating film 13 is formed on the entire surface. This state is shown in FIG.

Next, a hole is formed in a predetermined region of the third interlayer insulating film 13 by etching using a mask patterned by photolithography, and the surface of the plug 12 is exposed at the bottom of the hole. In this etching, the lower layer film 13a of the silicon nitride functions as an etching stopper to improve the etching accuracy. This state is shown in FIG.

Next, a polycrystalline silicon film 11 'to be the lower electrode 11 is formed on the entire surface. This state is shown in FIG. Subsequently, the holes are filled with a silicon oxide film 17. This state is shown in FIG. Subsequently, after the polysilicon film 11 'in the hole is protected by the silicon oxide film 17 and the other polysilicon film 11' is removed, the silicon oxide film 17 in the hole is removed.
Is removed to form the lower electrode 11. This state is shown in FIG.

Next, at 750 ° C. in an ammonia atmosphere.
After forming a thin thermal nitride film on the surface of the lower electrode 11, a tantalum oxide serving as the dielectric film 15 is deposited on the entire surface, and a heat treatment is performed at 800 ° C. for 3 minutes in an oxidizing atmosphere. This state is shown in FIG. Next, CV
D, and an upper electrode 1 in which a titanium nitride film 14a formed by sputtering and a titanium nitride 14b formed by sputtering are sequentially stacked.
4 and the entire surface is covered with a protective insulating film 16 to form a capacitive element. This state is shown in FIG.

The high dielectric / ferroelectric material is crystallized and modified by the above-mentioned heat treatment in an oxidizing atmosphere, so that the relative dielectric constant increases and the leak current decreases. For this purpose, the heat treatment is required, and the heat treatment oxidizes the thermal nitride film on the surface of the polycrystalline silicon, which is the lower electrode, to become a silicon oxynitride film, and the dielectric film is made of this silicon oxynitride film and tantalum oxide. And a laminated film. As a result, the leak current can be maintained at an extremely low level.

The present inventors have measured the leakage current of a MIS structure capacitive element. The above-mentioned capacitance element
Since it is considered that the capacitance formed on the side wall portion and the capacitance formed on the bottom portion of each different configuration are connected in parallel integrally, in this measurement, measurements were individually performed on models that assumed each capacitance. .

FIG. 10A shows a model assuming a capacitance formed on a side wall portion of a capacitive element. The structure is such that a silicon oxide corresponding to an interlayer insulating film is formed on an n-type silicon semiconductor substrate 101. A film 102 is formed, a polycrystalline silicon film 103 serving as a lower electrode is formed thereon, and a heat treatment at 750 ° C. for 3 minutes is performed in an ammonia atmosphere to form a thin thermal nitride film of about 1 nm on the surface of the polycrystalline silicon film 103. Is formed, a 10 nm thick tantalum oxide film 104 corresponding to a dielectric film is formed by CVD, and a heat treatment is performed in an oxygen atmosphere at 800 ° C. for 3 minutes, and then a titanium nitride film 105 corresponding to an upper electrode is formed by CVD. Then, the tantalum oxide film 104 is partially opened to expose the polycrystalline silicon film 103. FIG. 10B shows a model assuming the capacitance formed on the bottom surface of the capacitive element. The structure of the model is obtained by removing the silicon oxide film 102 corresponding to the interlayer insulating film from the above-described side wall model. Configuration.

For these models, for the side wall model, a voltage is applied between the titanium nitride film 105 serving as the upper electrode and the polycrystalline silicon film 103 serving as the lower electrode, and the leak current of the dielectric film is measured. With respect to the model of the bottom portion, the result of measuring the leak current of the tantalum oxide film 104 supposed to be a dielectric film by applying a voltage between the titanium nitride film 105 serving as the upper electrode and the semiconductor substrate 101 is shown in FIG. Shown in As is clear from this figure, the result of measuring the current density of the leak current by changing the applied voltage to the upper electrode from −3 V to +3 V shows that the results are the same in any of the models. Then 1E-
The leak current level is as extremely low as 9 A / cm ² .

Although the capacitance element having the MIS structure has such an advantage that the leak current is reduced, the silicon oxynitride film formed by the above-described heat treatment has a low dielectric constant. There is a problem that the dielectric constant of the entire dielectric film is lowered by forming a laminated film with tantalum oxide. To prevent such a decrease in the dielectric constant, an MIM (Metal-Insulator-Metal) structure using a metal material that does not form a low-dielectric-constant layer in a lower electrode serving as a base of the dielectric film is used. Capacitors have been considered, and specific examples thereof include platinum group ruthenium, platinum, and iridium.

As an example, FIGS. 12 to 2 show a manufacturing process of a capacitance element having an MIM structure using ruthenium as a lower electrode.
1 will be described. First, a plug 12 made of polycrystalline silicon is formed in a predetermined region of the second interlayer insulating film 10, and an insulating film 18 is formed on the entire surface. This state is shown in FIG. Subsequently, an opening for exposing the surface of the plug 12 is provided in the insulating film 18. This state is shown in FIG. Subsequently, a barrier layer 19 of titanium nitride filling the opening is formed. This state is shown in FIG. Subsequently, a third interlayer insulating film 13 is formed on the entire surface. This state is shown in FIG.
When a metal film is used for the lower electrode, the barrier layer 19 prevents the silicon of the plug 12 from reacting with the metal film due to the heat treatment to prevent the metal silicide film from being formed because the metal film easily transmits oxygen. Japanese Patent Application Laid-Open No. H10-79481 discloses that titanium,
A conductive layer containing a high-melting point metal such as tungsten tantalum, cobalt, and molybdenum, silicon, and nitrogen has been proposed.

Next, holes are formed in predetermined regions of the third interlayer insulating film 13 by etching using a mask patterned by photolithography, and the bottom surface of the holes exposes the surface of the barrier layer 19. This state is shown in FIG.
6 is shown. Next, a ruthenium film 20 'serving as the lower electrode 20 is formed on the entire surface. This state is shown in FIG. Subsequently, the holes are filled with a silicon oxide film 21. This state is shown in FIG. Subsequently, the silicon oxide film 21 protects the ruthenium film 20 ′ in the hole and removes another ruthenium film 20 ′, and then removes the silicon oxide film 21 in the hole to form the lower electrode 20. This state is shown in FIG.

Next, tantalum oxide to be the dielectric film 22 is deposited on the entire surface, and a modified crystallization is performed by applying a heat treatment at about 650 ° C. in an oxidizing atmosphere. FIG. 20 shows this state. Next, a lower film 23a using ruthenium formed on the entire surface by CVD and an upper film 2 formed by sputtering.
An upper electrode 23 in which 3b layers are sequentially stacked is formed, and the entire surface is covered with the protective insulating film 16 to form a capacitor. This state is shown in FIG.

[0018]

The leakage current of the capacitor having the MIM structure was measured. Similar to the above-described measurement of the leak current, the measurement was individually performed on a model that assumes the capacitance formed on the side wall portion and the capacitance formed on the bottom portion.

FIG. 22A shows a model assuming a capacitance formed on a side wall portion of a capacitive element. The structure is such that a silicon oxide film corresponding to an interlayer insulating film is formed on an n-type silicon substrate 101. A ruthenium film 106 serving as a lower electrode is formed thereon to a thickness of 20 nm, and a 10 nm-thick tantalum oxide film 107 corresponding to a dielectric film is formed on the CV.
D, heat treatment is performed in an oxygen atmosphere at 650 ° C. for 2 minutes to perform crystallization reforming treatment, and then a ruthenium film 108 corresponding to an upper electrode is deposited and patterned by CVD, and a tantalum oxide film 107 is partially opened. Thus, the ruthenium film 106 serving as the lower electrode is exposed.

FIG. 22B shows a model assuming a capacitance formed on the bottom surface of the capacitive element. The structure of the model is a polycrystalline silicon film 103 assuming a plug on an n-type silicon substrate 101. Is formed, a titanium nitride film 109 as a barrier layer is formed, a ruthenium film 106 serving as a lower electrode is formed thereon with a thickness of 20 nm, and a 10 nm-thick tantalum oxide film 107 corresponding to a dielectric film is formed. CVD
After performing a heat treatment in an oxygen atmosphere at 650 ° C. for 2 minutes to perform crystallization reforming, a ruthenium film 108 corresponding to an upper electrode is deposited and patterned by CVD.

As for these models, regarding the model of the side wall portion, the leakage of the tantalum oxide film 107 serving as a dielectric film by applying a voltage between the ruthenium film 108 serving as an upper electrode and the ruthenium film 107 serving as a lower electrode is described. FIG. 23 shows the result of measuring the current and measuring the leak current of the tantalum oxide film 107 by applying a voltage between the ruthenium film 108 serving as the upper electrode and the semiconductor substrate 101 for the model of the bottom surface portion.

As is apparent from FIG. 2, the voltage applied to the upper electrode was changed from -3 V to +3 V, and the current density of the leak current was measured. Although there is little good leakage current and good characteristics are shown, the leakage current is extremely large in the model of the bottom portion. Therefore, the charge to be accumulated leaks at the bottom portion and information cannot be held, so that it becomes difficult to fulfill the function as a storage element.

This is because the lower electrode of the MIS structure is not affected by the underlying film of the lower electrode because the lower electrode is made of polycrystalline silicon and does not transmit oxygen. Since the lower electrode transmits oxygen, it is affected by the underlying film. That is, it is considered that the characteristics of the dielectric are different due to the difference in the configuration that the lower electrode is in contact with the insulating film at the bottom portion while the lower electrode is in contact with the insulating film at the side wall portion. Can be

An object of the present invention is to solve such a problem and prevent an increase in leakage current of a capacitor having an MIM structure.
It is an object of the present invention to provide a technique capable of improving the reliability of a semiconductor device. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0025]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. In a semiconductor device having a capacitance element having a metal film as an electrode, a first capacitance element in which a capacitance element of the electrode is in contact with an insulating film and a metal electrode is formed, and a first capacitance element in which a metal electrode is formed in contact with a barrier film. And the thickness of the metal electrode of the second capacitor is greater than the thickness of the metal electrode of the first capacitor. Further, in the manufacturing method, a step of forming a metal film to be a lower electrode on a bottom portion of the capacitive element, a step of forming the insulating film, and forming a hole in the insulating film to expose a surface of the metal film And forming a metal film to be a lower electrode on the side wall and the bottom of the hole, so that the bottom of the lower electrode of the capacitive element is formed thicker than the side wall.

FIG. 24 shows a model of the bottom portion shown in FIG. 22B, in which the thickness of the tantalum oxide film 107 is fixed at 10 nm and the thickness of the ruthenium film 106 serving as the lower electrode is 20, It is a graph which shows the result of having measured the change of the leak current when changing to 50,100,200nm (film thickness ratio: 2,5,10,20). Film thickness 20nm
And 50 nm, the leakage current is extremely large.
At 00 nm, the leakage current is significantly reduced. However, when the film thickness is 100 nm, the current density of the leak current is 1E-7A.
/ Cm ² , which is insufficient for practical characteristics. On the other hand, when the film thickness is 200 nm (film thickness ratio: 20), the leak current is further reduced, and the current density of the leak current is 1E-9 A / cm ² at an applied voltage of 1 V, which is a characteristic that can sufficiently withstand practical use.

[0027]

Embodiments of the present invention will be described below. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 25 is a longitudinal sectional view showing a capacitive element of a semiconductor device according to an embodiment of the present invention. The capacitor of this embodiment has an MIM structure using tantalum oxide for the dielectric film.

The capacitive element according to the present embodiment is formed on an interlayer insulating film 10 covering a main surface of a semiconductor substrate such as single crystal silicon or the like, and a hole provided in an interlayer insulating film 13 formed on the interlayer insulating film 10. An upper electrode 23 in which a lower film 23a made of titanium nitride or ruthenium and an upper film 23b made of titanium nitride or tungsten are laminated, a dielectric film 22 of about 5 nm in thickness using tantalum oxide, and a lower film using ruthenium. The capacitor is formed by laminating the electrodes 20, and the capacitor is covered by the protective insulating film 16 formed on the entire surface.

The lower electrode 20 is formed on the interlayer insulating film 13 via a tantalum oxide film as an adhesive layer 24 on the side wall of the hole.
The bottom surface of the hole is in contact with a barrier layer 19 made of titanium nitride or tantalum nitride. From this difference in configuration, it is considered that the capacitor is formed by connecting the first capacitor formed on the side wall portion and the second capacitor formed on the bottom portion in parallel. The lower electrode 20 is composed of an upper film 20a having a thickness of 20 nm formed on the side wall and the bottom and a lower film 20b having a thickness of 200 nm formed on the bottom. In the second embodiment, the lower electrode 20 is formed to have a thickness of about 20 nm by the upper layer film 20a.
0 is 220 nm by the upper film 20a and the lower film 20b.
The lower electrode 20 is integrated because the upper film 20a is continuous. The barrier layer 19 in contact with the lower layer film 20b is formed on the silicide layer 25, and a plug 12 penetrating the interlayer insulating film 10 is connected to the silicide layer 25, and the plug 12 is formed on the main surface of the semiconductor substrate. To the semiconductor region.

In the present embodiment, the lower electrode 2 on the bottom portion
Since 0 is formed to be 20 times or more the thickness ratio of the lower electrode in the side wall portion, it is possible to prevent the above-described increase in the leak current.

Next, a method of manufacturing the capacitive element shown in FIG. 25 will be described with reference to FIGS. First, FIG.
As shown in FIG. 6, a plug 12 made of polycrystalline silicon is formed in a predetermined region of the interlayer insulating film 10 and an insulating film 18 is formed on the entire surface.
Is formed, and as shown in FIG.
An opening is provided to expose the surface of No. 2. Subsequently, as shown in FIG. 28, a metal film 25 'such as ruthenium or titanium is formed on the entire surface.
Then, heat treatment is performed in a non-oxidizing atmosphere at 650 ° C. for about 1 minute to remove unreacted metal, and a metal silicide layer 25 is formed in the opening as shown in FIG.

Next, as shown in FIG. 30, a metal film 19 'made of titanium nitride, tantalum nitride, or the like is deposited on the entire surface.
As shown in FIG. 1, the metal film 19 ′ on the surface is removed, and the opening is filled with a barrier layer 19. Then, the thickness 20
An insulating film 26 is formed to a thickness of about 0 nm, an opening for exposing the barrier layer 19 is provided as shown in FIG. 32, and a ruthenium film 20b 'is deposited on the entire surface as shown in FIG. The ruthenium film 20b 'on the surface is removed to form a lower film 20b of the lower electrode 20 inside the opening.

Next, as shown in FIG. 35, the interlayer insulating film 1
3, a lower film 13a, an upper film 13b, and a hard mask 27 are sequentially formed on the entire surface, and then the hard mask 27 is patterned in a predetermined region using a resist mask patterned by photolithography. Depending on the etching used, FIG.
A hole is formed as shown in FIG. 5 and the surface of the lower film 20b of the lower electrode 20 is exposed at the bottom of the hole.

Next, the hard mask 27 is removed, and FIG.
38, a tantalum oxide film 24 'serving as an adhesive layer 24 is formed to a thickness of about 5 nm on the entire surface, and as shown in FIG. 38, the tantalum oxide film 24' on the surface and the bottom of the hole is removed by anisotropic dry etching. And an adhesive layer 2 is provided on the side wall of the hole.
4 is formed.

Next, as shown in FIG.
Ruthenium film 20a 'to be the upper layer film 20a
Then, as shown in FIG. 40, the hole is filled with a resist mask 28, and then the ruthenium film 20 in the hole is formed by the resist mask 28.
After protecting other a 'and removing the other ruthenium film 20a', the resist mask 28 in the hole is removed to form an upper layer film 20a of the lower electrode 20, as shown in FIG. For this purpose, a heat treatment at 700 ° C. for about 1 minute is performed.

Next, as shown in FIG. 42, tantalum oxide serving as the dielectric film 22 is deposited on the entire surface, and heat treatment is performed at 650 ° C. for about 2 minutes in a non-oxidizing atmosphere. A heat treatment is performed at about 1 ° C. for about 1 minute to perform modified crystallization of tantalum oxide. Thereafter, an upper electrode 23 is formed by sequentially laminating a lower film 23a such as ruthenium and titanium nitride formed by CVD and an upper film 23b such as titanium nitride and tungsten formed by sputtering over the entire surface. The capacitor is formed so as to cover it, and the state shown in FIG. 25 is obtained.

(Embodiment 2) FIG. 43 is a longitudinal sectional view showing a capacitive element of a semiconductor device according to another embodiment of the present invention. The capacitive element of the present embodiment has a configuration in which the barrier layer 19 is embedded in the interlayer insulating film 10 on which the plug 12 is formed, and other configurations are substantially the same as those of the above-described embodiment.

The capacitive element according to the present embodiment has an interlayer insulating film 1
An upper electrode 23 in which a lower film 23a made of titanium nitride or ruthenium and an upper film 23b made of titanium nitride or tungsten are stacked in a hole provided in the interlayer insulating film 13 formed on the upper electrode 23, and tantalum oxide is used. A capacitive element is formed by laminating a dielectric film 22 having a thickness of about 5 nm and a lower electrode 20 using ruthenium, and the capacitive element is covered by a protective insulating film 16 formed on the entire surface.

The lower electrode 20 is formed on the interlayer insulating film 13 via a tantalum oxide film as an adhesive layer 24 on the side wall of the hole.
The bottom surface of the hole is in contact with a barrier layer 19 made of titanium nitride or tantalum nitride. The lower electrode 20 has a thickness of 20 nm formed on the side wall and the bottom.
Thickness of 200 nm formed on the upper layer film 20a and the bottom surface
And the lower electrode 20 is formed by the upper layer film 20a in the first capacitive element in the side wall portion.
m, and in the second capacitive element at the bottom, the lower electrode 20 is formed by the upper film 20a and the lower film 20b.
The lower electrode 20 is integrated since the upper layer 20a is formed to have a thickness of about 0 nm and is continuous. The barrier layer 19 in contact with the lower layer film 20b is formed on the silicide layer 25, and the barrier layer 19 and the silicide layer 25 are buried in holes provided in the interlayer insulating film 10.

In this embodiment, the insulating film 18 for forming the barrier layer 19, which is required in the above-described embodiment, is not required, and the process can be simplified.

Subsequently, a method of manufacturing the capacitive element shown in FIG. 43 will be described with reference to FIGS. First, FIG.
As shown in FIG. 4, a plug 12 made of polycrystalline silicon is formed in a predetermined region of the interlayer insulating film 10, an opening is formed by dug the plug 12 by about 100 nm from the surface, and as shown in FIG. A metal silicide layer 25 and a barrier layer 19 are sequentially formed to fill the opening. next,
An insulating film 26 having a thickness of about 200 nm is formed on the entire surface.
As shown in FIG. 6, an opening for exposing the barrier layer 19 is provided in the capacitive element formation region, and as shown in FIG. 47, a lower layer film 20b of the lower electrode 20 is formed inside the opening.

Next, as shown in FIG.
3, a lower film 13a, an upper film 13b, and a hard mask 27 are sequentially formed on the entire surface, respectively, and then a hole is formed in a predetermined region as shown in FIG.
0 exposes the surface of the lower film 20b. Thereafter, an adhesive layer 24 is formed on the side wall of the hole, and the upper layer 2 of the lower electrode 20 is formed.
0a is formed, tantalum oxide to be the dielectric film 22 is deposited on the entire surface, and subsequently, a lower film 23a such as ruthenium and titanium nitride formed by CVD and an upper film such as titanium nitride and tungsten formed by sputtering are formed. 23b
Are sequentially laminated, and the entire surface is covered with the protective insulating film 15 to form a capacitive element, resulting in the state shown in FIG.

(Embodiment 3) FIG. 50 is a longitudinal sectional view showing a capacitive element of a semiconductor device according to another embodiment of the present invention. In the capacitive element of the present embodiment, a metal silicide nitride layer 29 is provided in place of the metal silicide layer 25 and the barrier layer 19, and the lower film 20a of the lower electrode 20 is formed over the entire bottom surface of the hole. Instead, it is provided only in the portion of the metal silicide nitride layer 29, and the other configuration is substantially the same as that of the above-described embodiment.

The capacitive element according to the present embodiment has an interlayer insulating film 1
An upper electrode 23 in which a lower film 23a made of titanium nitride or ruthenium and an upper film 23b made of titanium nitride or tungsten are stacked in a hole provided in the interlayer insulating film 13 formed on the upper electrode 23, and tantalum oxide is used. A capacitive element is formed by laminating a dielectric film 22 having a thickness of about 5 nm and a lower electrode 20 using ruthenium, and the capacitive element is covered by a protective insulating film 16 formed on the entire surface.

The lower electrode 20 is formed on the interlayer insulating film 13 via a tantalum oxide film as an adhesive layer 24 on the side wall of the hole.
The bottom surface of the hole is in contact with a barrier layer 19 made of titanium nitride or tantalum nitride. The lower electrode 20 has a thickness of 20 nm formed on the side wall and the bottom.
Thickness of 200 nm formed on the upper layer film 20a and the bottom surface
And the lower electrode 20 is formed by the upper layer film 20a in the first capacitive element in the side wall portion.
m, and in the second capacitive element at the bottom, the lower electrode 20 is formed by the upper film 20a and the lower film 20b.
The lower electrode 20 is integrated since the upper layer 20a is formed to have a thickness of about 0 nm and is continuous. The lower film 20b is in contact with the plug 12 via the metal silicide nitride layer 29, and the metal silicide nitride layer 29 is embedded in a hole provided in the interlayer insulating film 10 where the plug 12 is formed.

In the present embodiment, the silicide layer 25 and the barrier layer 19 of the above-described embodiment are used as the metal silicide nitride layers 29, and the interlayer insulating film 26 required for forming the lower layer film 20a becomes unnecessary. , The process can be simplified.

Next, a method of manufacturing the capacitive element shown in FIG. 50 will be described with reference to FIGS. First, FIG.
As shown in FIG. 1, a plug 12 made of polycrystalline silicon is formed in a predetermined region of the interlayer insulating film 10, an opening is formed by digging the plug 12 by about 100 nm from the surface, and a metal is formed in the opening as shown in FIG. The film 30 is formed, the metal film 30 is reacted with the silicon of the plug 12 as shown in FIG. 53 to form a metal silicide layer 31, and the unreacted metal film 30 is removed as shown in FIG.

Next, as shown in FIG. 55, the metal silicide layer 31 is nitrided to form a metal silicide nitride layer 29, and a ruthenium film 20b 'is formed on the entire surface including the inside of the opening as shown in FIG. As shown in FIG. 57, the ruthenium film 20b 'other than in the opening is removed by deposition and the lower electrode 2 filling the opening as shown in FIG.
0b is formed.

Next, as shown in FIG.
3, a lower film 13a, an upper film 13b, and a hard mask 27 are sequentially formed on the entire surface. Subsequent steps are the same as those of the above-described embodiment. A hole is formed in the interlayer insulating film 13, an adhesive layer 24 is formed on a side wall of the hole, an upper layer film 20a of the lower electrode 20 is formed, and a dielectric Tantalum oxide serving as the body film 22 is deposited, subsequently, the upper electrode 23 is formed, and the entire surface is covered with the protective insulating film 16 to form a capacitive element, resulting in the state shown in FIG.

(Embodiment 4) FIG. 59 is a longitudinal sectional view showing a capacitive element of a semiconductor device according to another embodiment of the present invention. In the capacitive element of the present embodiment, the metal silicide nitride layer 29 is provided in place of the metal silicide layer 25 and the barrier layer 19, but the unreacted metal is formed by using the metal film 30 of the above-described embodiment as ruthenium. The step of removing the film 30 can be omitted, and the step can be simplified. Other configurations are substantially the same as those of the above-described embodiment.

The capacitive element according to the present embodiment has an interlayer insulating film 1
An upper electrode 23 in which a lower film 23a made of titanium nitride or ruthenium and an upper film 23b made of titanium nitride or tungsten are stacked in a hole provided in the interlayer insulating film 13 formed on the upper electrode 23, and tantalum oxide is used. A capacitive element is formed by laminating a dielectric film 22 having a thickness of about 5 nm and a lower electrode 20 using ruthenium, and the capacitive element is covered by a protective insulating film 16 formed on the entire surface.

The lower electrode 20 is formed on the interlayer insulating film 13 via a tantalum oxide film as an adhesive layer 24 on the side wall of the hole.
The bottom surface of the hole is in contact with a barrier layer 19 made of titanium nitride or tantalum nitride. The lower electrode 20 has a thickness of 20 nm formed on the side wall and the bottom.
Thickness of 200 nm formed on the upper layer film 20a and the bottom surface
And the lower electrode 20 is formed by the upper layer film 20a in the first capacitive element in the side wall portion.
m, and in the second capacitive element at the bottom, the lower electrode 20 is formed by the upper film 20a and the lower film 20b.
The lower electrode 20 is integrated since the upper layer 20a is formed to have a thickness of about 0 nm and is continuous. The lower film 20b is in contact with the plug 12 via the metal silicide nitride layer 29, and the metal silicide nitride layer 29 is embedded in a hole provided in the interlayer insulating film 10 where the plug 12 is formed.

Next, a method of manufacturing the capacitive element shown in FIG. 59 will be described with reference to FIGS. First, FIG.
As shown in FIG. 0, a plug 12 made of polycrystalline silicon is formed in a predetermined region of the interlayer insulating film 10, an opening is formed by dug the plug 12 by about 100 nm from the surface, and a metal film 30 made of ruthenium is formed in the opening. The metal film 30 is reacted with the silicon of the plug 12 to form a metal silicide layer 31, and the metal silicide layer 31 is nitrided to form a metal silicide nitride layer 29 as shown in FIG.

Next, as shown in FIG. 62, a ruthenium film 20b 'is deposited on the entire surface including the inside of the opening, and the ruthenium film 20b' and the metal film 30 other than in the opening are deposited by etching as shown in FIG. By removing, the lower electrode 20b filling the opening is formed.

Subsequent steps are the same as those of the above-described embodiment, and the lower film 13a, the upper film 13b,
A hard mask 27 is sequentially formed on the entire surface, holes are formed, an adhesive layer 24 is formed on side walls of the holes, and a lower electrode 20 is formed.
An upper layer film 20a is formed, tantalum oxide serving as a dielectric film 22 is deposited on the entire surface, an upper electrode 23 is formed, and the entire surface is covered with a protective insulating film 16 to form a capacitor. The state shown in FIG.

(Embodiment 5) FIG. 64 is a longitudinal sectional view showing a capacitive element of a semiconductor device according to another embodiment of the present invention. In the capacitive element of the present embodiment, the underlayer on the bottom surface of the upper layer film 20a of the lower electrode 20 is made of a tantalum oxide film, and the other structures are substantially the same as those of the above-described embodiment.

The capacitive element according to the present embodiment has an interlayer insulating film 1
An upper electrode in which a lower layer film 23a using titanium nitride or ruthenium and an upper layer film 23b using titanium nitride or tungsten are stacked in a hole provided in the interlayer insulating film 13 formed on the substrate 0 with a tantalum oxide film 32 interposed therebetween. A capacitance element is formed by laminating a dielectric film 22 of about 5 nm thickness using tantalum oxide and a lower electrode 20 using ruthenium, and the capacitance element is covered by a protective insulating film 16 formed on the entire surface. .

The lower electrode 20 is formed on the interlayer insulating film 13 via a tantalum oxide film as an adhesive layer 24 on the side wall of the hole.
The bottom surface of the hole is in contact with a barrier layer 19 made of titanium nitride or tantalum nitride. The lower electrode 20 has a thickness of 20 nm formed on the side wall and the bottom.
Thickness of 200 nm formed on the upper layer film 20a and the bottom surface
And the lower electrode 20 is formed by the upper layer film 20a in the first capacitive element in the side wall portion.
m, and in the second capacitive element at the bottom, the lower electrode 20 is formed by the upper film 20a and the lower film 20b.
The lower electrode 20 is integrated since the upper layer 20a is formed to have a thickness of about 0 nm and is continuous. The lower film 20b is in contact with the plug 12 via the metal silicide nitride layer 29, and the metal silicide nitride layer 29 is embedded in a hole provided in the interlayer insulating film 10 where the plug 12 is formed.

In this embodiment, in addition to the above-described embodiment, the bottom surface of the upper film 20a of the lower electrode 20 and the side surface of the lower film 20b become the tantalum oxide film 32. .

Next, a method of manufacturing the capacitive element shown in FIG. 64 will be described with reference to FIGS. First, FIG.
As shown in FIG. 5, the tantalum oxide film 3 is formed on the interlayer insulating film 10.
Then, as shown in FIG. 66, holes are formed in predetermined regions of the interlayer insulating film 10 and the tantalum oxide film 32, and plugs 12 made of polycrystalline silicon are formed in the holes. An opening is formed by digging down about 100 nm. Subsequently, as shown in FIG. 67, a metal silicide nitride layer 29 is formed in the opening, a ruthenium film 20b 'is deposited on the entire surface including the opening, and the opening is formed in the opening as shown in FIG. The other part of the ruthenium film 20b 'is removed to form a lower electrode 20b filling the opening.

Subsequent steps are the same as those of the above-described embodiment, and the lower film 13a, the upper film 13b,
A hard mask 27 is sequentially formed on the entire surface, holes are formed, an adhesive layer 24 is formed on side walls of the holes, and a lower electrode 20 is formed.
The upper layer film 20a is formed, tantalum oxide serving as the dielectric film 22 is deposited on the entire surface, the upper electrode 23 is formed, and the entire surface is covered with the protective insulating film 16 to form a capacitor. The state shown in FIG.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0064]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, there is an effect that the leak current can be reduced by making the bottom surface portion of the metal lower electrode of the capacitor element thicker than the side wall portion. (2) According to the present invention, according to the above-mentioned effect (1), MIM
There is an effect that a capacitive element having a structure can be realized. (3) According to the present invention, the effect (2) has an effect that a material having a high dielectric constant can be adopted for the dielectric film of the capacitor. (4) According to the present invention, the effect (3) has an effect that the capacitance of the capacitor can be increased. (5) According to the present invention, there is an effect that the memory cell can be further miniaturized by the effect (4). (6) According to the present invention, the effect (5) has an effect that the storage capacity of the semiconductor memory device can be further increased. (7) According to the present invention, the effect (5) has an effect that the chip size of a semiconductor memory device having the same storage capacity can be reduced.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a memory cell of a DRAM.

FIG. 2 is a longitudinal sectional view showing a MIS structure capacitive element for each process.

FIG. 3 is a longitudinal sectional view showing a MIS structure capacitive element for each process.

FIG. 4 is a longitudinal sectional view showing a MIS structure capacitive element for each process.

FIG. 5 is a longitudinal sectional view showing a MIS structure capacitive element in each step.

FIG. 6 is a vertical sectional view showing a capacitor having a MIS structure in each step.

FIG. 7 is a longitudinal sectional view showing a MIS structure capacitive element for each process.

FIG. 8 is a vertical cross-sectional view showing a MIS structure capacitive element for each process.

FIG. 9 is a vertical cross-sectional view showing a MIS structure capacitive element for each process.

FIG. 10 is a longitudinal sectional view showing a model assuming capacitances formed on a side wall portion and a bottom surface portion of a capacitance element having a MIS structure.

11 is a diagram showing a result of measuring a leak current of the model shown in FIG.

FIG. 12 is a vertical cross-sectional view showing a MIM structure capacitive element for each process.

FIG. 13 is a vertical cross-sectional view showing a capacitance element having an MIM structure in each step.

FIG. 14 is a vertical cross-sectional view showing a MIM structure capacitive element for each process.

FIG. 15 is a vertical cross-sectional view showing a MIM structure capacitive element for each process.

FIG. 16 is a vertical cross-sectional view showing a MIM structure capacitive element for each step.

FIG. 17 is a vertical cross-sectional view showing a MIM structure capacitive element for each process.

FIG. 18 is a longitudinal sectional view showing a MIM structure capacitive element for each process.

FIG. 19 is a vertical cross-sectional view showing a MIM structure capacitive element for each step.

FIG. 20 is a vertical cross-sectional view showing a MIM structure capacitive element for each process.

FIG. 21 is a longitudinal sectional view showing a capacitor having an MIM structure in each step.

FIG. 22 is a longitudinal sectional view showing a model assuming capacitances formed on a side wall portion and a bottom surface portion of the capacitance element having the MIM structure.

FIG. 23 is a view showing a result of measuring a leak current of the model shown in FIG. 22;

24 is a diagram showing a result of measuring a leak current while changing the thickness of the lower electrode of the model shown in FIG. 22;

FIG. 25 is a longitudinal sectional view showing a capacitor of the semiconductor device according to one embodiment of the present invention;

FIG. 26 is a longitudinal sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 27 is a longitudinal sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 28 is a longitudinal sectional view showing a capacitor of the semiconductor device according to the embodiment of the present invention for each process;

FIG. 29 is a longitudinal sectional view showing the capacitor of the semiconductor device according to the embodiment of the present invention for each process;

FIG. 30 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 31 is a longitudinal sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 32 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 33 is a longitudinal sectional view showing the capacitor of the semiconductor device according to the embodiment of the present invention for each process;

FIG. 34 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 35 is a longitudinal sectional view showing a capacitor of the semiconductor device according to the embodiment of the present invention for each process;

FIG. 36 is a longitudinal sectional view showing a capacitor of the semiconductor device according to the embodiment of the present invention for each process;

FIG. 37 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 38 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 39 is a longitudinal sectional view showing the capacitor of the semiconductor device according to the embodiment of the present invention for each process;

FIG. 40 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 41 is a longitudinal sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 42 is a longitudinal sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention for each step;

FIG. 43 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 44 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 45 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process.

FIG. 46 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 47 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 48 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 49 is a longitudinal sectional view showing, for each step, a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 50 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention.

FIG. 51 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 52 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 53 is a longitudinal sectional view showing, for each step, a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 54 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 55 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 56 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 57 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 58 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 59 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 60 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 61 is a longitudinal sectional view showing, for each step, a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 62 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 63 is a longitudinal sectional view showing, for each step, a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 64 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 65 is a longitudinal sectional view showing, for each step, a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 66 is a longitudinal sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

FIG. 67 is a longitudinal sectional view showing, for each step, a capacitor of a semiconductor device according to another embodiment of the present invention;

FIG. 68 is a vertical cross-sectional view showing a capacitor of a semiconductor device according to another embodiment of the present invention for each process;

[Description of Signs] 1 ... semiconductor substrate, 2 ... isolation insulating film, 3 ... gate insulating film,
4 gate electrode, 5, 6 semiconductor region, 7, 10, 13
... interlayer insulating film, 13a ... lower layer film, 13b ... upper layer film, 8 ...
Bit lines, 9, 12,... Plugs, 11, 20,.
11 ': polycrystalline silicon film, 14, 23: upper electrode, 1
5: dielectric film, 16: protective insulating film, 17: silicon oxide film,
18, 26 ... insulating film, 19 ... barrier layer, 20 '... ruthenium film, 21 ... silicon oxide film, 22 ... dielectric film, 23a ...
Lower film, 23b Upper film, 24 Adhesive layer, 25, 31 ...
Metal silicide film, 27 hard mask, 28 resist mask, 29 metal silicon nitride film, 30
Metal film, 32: tantalum oxide film, 101: semiconductor substrate,
102, 105: titanium nitride film, 103: polycrystalline silicon film, 104, 107: tantalum oxide film, 106, 10
8. Ruthenium film.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isamu Isano 3-16-16 Shinmachi, Ome-shi, Tokyo F-term in Hitachi Device Co., Ltd. F-term (reference) 5F083 AD24 AD42 AD43 GA06 JA06 JA35 JA38 JA39 JA40 MA05 MA06 MA17 PR33

Claims (5)

[Claims] 1. A semiconductor device having a capacitance element having a metal film as an electrode, wherein: a first capacitance element in which the capacitance element of the electrode is in contact with an insulating film to form a metal electrode; and a metal electrode in contact with a barrier film. A semiconductor device comprising: a second capacitor having a first capacitor formed thereon, wherein the thickness of the metal electrode of the second capacitor is greater than the thickness of the metal electrode of the first capacitor. 2. A semiconductor device comprising: a first capacitor provided on a side wall portion of a hole provided in an insulating film; and a second capacitor provided on a bottom portion of the hole, wherein the first capacitor is provided. A lower electrode is formed in contact with the insulating film, and the second capacitor is formed with a lower electrode in contact with the barrier film, and the metal films forming the respective lower electrodes are connected to form the first capacitor and the first capacitor. A semiconductor device in which a second capacitor is connected in parallel, and a film thickness of a lower electrode of the second capacitor is larger than a film thickness of a lower electrode of the first capacitor. 3. The method according to claim 1, wherein the thickness of the lower electrode of the second capacitor is equal to or smaller than the first thickness.
3. The semiconductor device according to claim 1, wherein the thickness of the lower electrode of the capacitive element is about 10 times. 4. The semiconductor device according to claim 1, wherein the lower electrode of the capacitor is made of ruthenium, and the dielectric film is made of tantalum oxide. 5. A method of manufacturing a semiconductor device in which a capacitance element is formed on a bottom portion and a side wall portion of a hole formed in an insulating film, wherein a step of forming a metal film to be a lower electrode on the bottom portion of the capacitance element; Forming a hole exposing the surface of the metal film in the insulating film; forming a metal film serving as a lower electrode on a side wall portion and a bottom surface portion of the hole; A method of manufacturing a semiconductor device, comprising: forming a bottom surface portion of a lower electrode of an element thicker than a side wall portion.