JP2000156479A - Semiconductor memory and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent reaction between silicon and an electrode material by forming no adhesion layer or a barrier layer on the side wall part of a cylinder type electrode and forming only a barrier layer at the lower part of the electrode thereby preventing capacity loss or junction leakage attributed to the adhesion layer or barrier layer on the side wall part of the electrode. SOLUTION: A contact hole 3 is made in an interlayer insulation film 1 and a polysilicon plug 4 is formed therein. A cylinder type lower electrode 8 is formed on the polysilicon plug 4 through a barrier layer 5 and covered with a capacitor insulating film 9 and an upper electrode 10. The barrier layer 5 or an adhesion layer is not formed on the side wall of the lower electrode 8. Consequently, capacity loss or increase of leakage current attributed to the barrier layer on the side wall part of the electrode can be suppressed while preventing reaction between the plug material and the electrode material. The lower electrode 8 can be formed while suppressing delamination.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a semiconductor memory device having upper and lower electrodes made of metal and a capacitor insulating film made of a metal oxide film or the like.
The present invention relates to a semiconductor memory device having M (Metal Insulator Metal) memory cells and a method of manufacturing the same.

[0002]

2. Description of the Related Art DRAM as a typical semiconductor memory device
Memory cells are composed of one transistor and one capacitance element (capacitor). Conventionally, the capacitor structure of a memory cell has been of a planar type (flat type), but with the miniaturization and high integration of semiconductor storage devices, a stack type (stacked type) or trench type (trench type) has been adopted since the 4Mb generation.
Etc. have come to be adopted. In a stacked capacitor, the main part of the capacitor is extended to the upper part of the gate electrode or the field oxide film to increase the area of the capacitor electrode pair, thereby securing the capacitance of the capacitor. A typical example of the stacked capacitor is a cylindrical capacitor having a cylindrical electrode.

In a conventional stack type capacitor, upper and lower electrodes are formed of semiconductors, and an SIS (Silicon I) having a silicon nitride film based capacitor insulating film between the upper and lower electrodes.
nsulator Silicon) type. With the use of metal oxides such as Ta ₂ O ₅ having a higher dielectric constant than a silicon oxide film or a silicon nitride film as a capacitor insulating film, MIM capacitors having upper and lower electrodes made of metal are now being used. Migrating.

An electrode of a cylinder type capacitor used as a storage node electrode of a semiconductor memory device is formed by forming a sacrificial film made of a silicon oxide film into a concave or convex shape and using this as a mold. A conventional method of forming a cylindrical capacitor having an MIM structure will be described with reference to FIGS. FIGS. 9 and 10 show a case where a sacrificial film is arranged inside a cylinder electrode, and FIGS. 11 and 12 show a case where a sacrificial film is arranged around the cylinder electrode.

When a sacrificial film is arranged inside a cylinder electrode, first, as shown in FIG. 9A, a silicon as an etching stopper layer is formed on an interlayer insulating film 1 made of, for example, a silicon oxide film. Nitride film (Si ₃ N ₄ layer)
Form 2 A contact hole 3 is formed in the Si ₃ N ₄ layer 2 and the interlayer insulating film 1 by etching, and a polysilicon (or conductive amorphous silicon) plug 4 is formed so as to fill the contact hole 3. On the entire surface of the upper layer, a Ti layer or Ti
Then, a silicon oxide film 6 serving as a sacrifice film for forming a cylindrical capacitor electrode is formed.

Next, as shown in FIG. 9B, the oxide film 6 and the barrier layer 5 are removed by etching while leaving only the oxide film 6 on the polysilicon plug 4. In order to prevent delamination between the silicon oxide film 6 and the metal layer serving as the lower electrode, Ti is formed as an adhesion layer 7 on the entire surface including the side wall of the oxide film 6.
Alternatively, a Ti / TiN layer (laminated film) is formed. For example, a tungsten (W) layer or a tungsten nitride (WN) layer is formed as a metal layer 8 serving as a lower electrode on the adhesion layer 7.

Next, as shown in FIG.
(Chemical mechanical polishing chemicalmechanica
After removing the W or WN layer 8 and the adhesion layer 7 on the oxide film 6 by performing l polishing, the oxide film 6 between the electrodes is removed by etching. Alternatively, an oxide film (not shown) may be formed so as to bury the space between the electrodes, and then the entire surface may be etched back to remove the lower electrode 8 and the adhesive layer 7 on the oxide film 6. In that case,
After the entire surface is etched back, the oxide film 6 between the electrodes and the buried oxide film (not shown) are removed by, for example, etching using hydrofluoric acid.

[0010] Thereafter, as shown in FIG. 10 (B), the entire surface is covered with Ta ₂ so as to cover the adhesion layer 7 and the lower electrode 8.
A capacitor insulating film 9 made of a dielectric such as O ₃ is formed. After forming a metal layer made of, for example, Ti as the upper electrode 10 on the entire surface, the storage electrode is formed by patterning the upper electrode 10, the capacitor insulating film 9 and the Si ₃ N ₄ layer 2.

On the other hand, when a storage node electrode is formed by disposing a sacrificial film around a cylinder electrode, first, as shown in FIG. 11A, a sacrificial film is formed inside the cylinder electrode. In the same manner as the case where Si is disposed, Si _{3 is formed} as an etching stopper layer on the interlayer insulating film 1.
An N ₄ layer 2 is formed, a contact hole 3 is provided in these layers, and a polysilicon plug 4 is formed so as to fill the contact hole 3. A silicon oxide film 6 serving as a sacrificial film for forming a cylindrical capacitor electrode is formed thereon.

Next, as shown in FIG. 11B, only the oxide film 6 on the polysilicon plug 4 is removed by etching. For example, a Ti or Ti / TiN layer is formed as an adhesion layer 7 on the entire surface including the side wall of the oxide film 6, and a W layer or a WN layer is formed thereon as a lower electrode 8.
The adhesion layer 7 also functions as a barrier layer for preventing a reaction between the polysilicon and the metal material of the lower electrode 8 at the interface with the polysilicon plug 4.

Subsequently, as shown in FIG.
P is performed to remove the lower electrode 8 and the adhesion layer 7 above the oxide film 6, and then the oxide film 6 between the electrodes is removed by etching. Alternatively, after forming an oxide film (not shown) so as to bury the inside of the electrode, the entire surface is etched back to remove the lower electrode 8 and the adhesion layer 7 above the oxide film 6, and thereafter, for example, hydrofluoric acid is used. Oxide film 6 between electrodes by etching
Also, the buried oxide film (not shown) may be removed.

Thereafter, as shown in FIG. 12B, the entire surface is covered with Ta ₂ O ₃ so as to cover the adhesion layer 7 and the lower electrode 8.
A capacitor insulating film 9 made of a dielectric material such as Further, after forming a metal layer of Ti or the like to be the upper electrode 10 on the entire surface, the upper electrode 10, the capacitor insulating film 9 and the S
By patterning the i ₃ N ₄ layer 2, a storage node electrode is formed.

According to the above-described conventional method for forming a capacitor, the adhesion layer 7 is formed on the entire surface including the side wall of the oxide film 6 in order to prevent delamination between the oxide film 6 serving as a sacrificial film and the lower electrode 8. In addition, a polysilicon plug is often used for a storage node of a DRAM memory cell in order to reduce a junction leak. In order to prevent a reaction between a metal of an electrode material and polysilicon, for example, Ti or Ti /
It is necessary to form a barrier layer (reaction prevention layer) 5 made of a TiN laminated film. Therefore, as shown in FIG. 10B or FIG. 12B, the structure is such that the side wall of the cylinder electrode is covered with the adhesion layer or the barrier layer.

[0014]

However, the side wall portion of the cylinder type capacitor is the portion which greatly contributes to the area of the capacitor electrode pair, and if the adhesion layer or the barrier layer is formed on the cylindrical electrode side wall portion. This causes a loss of capacitance of the capacitor and an increase in leakage current of the capacitor insulating film. The present invention has been made in view of the above problems, and therefore, the present invention relates to a semiconductor memory device having a cylinder type capacitor having an MIM structure, which has a capacity loss and a junction due to an adhesion layer or a barrier layer on an electrode side wall. An object of the present invention is to provide a semiconductor memory device in which leakage is prevented and a reaction between silicon and an electrode material is prevented, and a method for manufacturing the same.

[0015]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a semiconductor substrate having an active element formed thereon, an interlayer insulating film formed on the semiconductor substrate, and an interlayer insulating film formed on the semiconductor substrate. A contact hole reaching the surface of the active element provided in the insulating film; a plug made of a conductor formed in the contact hole; and a semiconductor substrate surface formed so as to cover at least an upper portion of the plug. A barrier layer, a cylindrical lower electrode including a bottom surface formed above the barrier layer and a side surface formed upward from the bottom surface, and a capacitor insulating film made of a dielectric formed on the surface of the lower electrode; An upper electrode formed on a surface of the capacitor insulating film.

In the semiconductor memory device according to the present invention, preferably, the plug is made of silicon, and the lower electrode is made of tungsten. Alternatively, the semiconductor memory device of the present invention is preferably characterized in that the plug is made of silicon and the lower electrode is made of tungsten nitride. In the semiconductor memory device according to the present invention, preferably, the barrier layer is made of titanium. Alternatively, the semiconductor memory device of the present invention is preferably characterized in that the barrier layer is formed of a laminated film of titanium and titanium nitride. In the semiconductor memory device according to the present invention, preferably, the capacitor insulating film is made of tantalum oxide. In the semiconductor memory device according to the present invention, preferably, the upper electrode is made of titanium.

Thus, in the cylinder type capacitor, the adhesion layer or the barrier layer is not formed on the side wall portion which greatly contributes to the area of the capacitor electrode pair, so that the capacitance loss due to the adhesion layer or the barrier layer on the electrode side wall portion, An increase in leakage current of the capacitor insulating film is prevented. On the other hand, at the interface between the polysilicon plug for electrical connection between the transistor and the capacitor and the lower electrode of the capacitor,
A barrier layer is formed to prevent reaction between silicon and the electrode material. According to the above structure, the effective area of the capacitor can be effectively used by reducing the capacitance loss and the leak current. Therefore, the area of the capacitor electrode pair can be reduced, and the height of the cylinder electrode can be reduced. As a result, the aspect ratio of the contact hole formed around the capacitor is reduced, and the memory cell can be miniaturized, so that the capacity of the semiconductor memory device can be increased.

Further, in order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming an interlayer insulating film on a semiconductor substrate, and a step of forming a contact hole reaching the surface of the semiconductor substrate in the interlayer insulating film. Providing a;
A step of forming a plug made of a conductor in the contact hole, a step of forming a sacrificial film on the entire surface, and forming an opening in the sacrificial film above the contact hole to reach the plug surface, the upper end being narrower than the lower end. Providing a first metal layer over the entire surface except for the side wall of the opening to form an adhesion layer on the sacrificial film, and forming a barrier layer at the bottom of the opening; Forming a second metal layer on the entire surface including the side wall of the opening; removing the adhesion layer and the second metal layer above the adhesion layer to form a cylindrical lower electrode in the opening; A step of removing the sacrificial film, a step of forming a capacitor insulating film made of a dielectric on the surface of the lower electrode, and a step of forming an upper electrode on the surface of the capacitor insulating film. Feature

In the method of manufacturing a semiconductor memory device according to the present invention, preferably, the step of removing the adhesion layer and the second metal layer above the adhesion layer and forming the lower electrode includes the step of: Chemical mechanical polishing (CM) until removed
P). Alternatively, in the method of manufacturing a semiconductor memory device according to the present invention, preferably, the step of removing the adhesion layer and the second metal layer on the adhesion layer and forming the lower electrode includes burying the opening in the opening. This is a step of forming a sacrificial film and performing etch back on the entire surface, and the step of removing the sacrificial film is a step of removing the sacrificial film and the buried sacrificial film.

In the method for manufacturing a semiconductor memory device according to the present invention, preferably, the step of forming the sacrificial film on the entire surface includes the step of forming a first sacrificial film and the step of forming a sacrificial film on the first sacrificial film. Forming a second sacrificial film having a thickness sufficiently smaller than that of the first sacrificial film and a small etching selectivity;
The step of providing the opening in the sacrificial film is a step of performing etching so that the diameter of the opening in the second sacrificial film is relatively smaller than the diameter of the opening in the first sacrificial film. It is characterized by. In the method of manufacturing a semiconductor memory device according to the present invention, more preferably, the step of providing the opening in the sacrificial film includes performing anisotropic etching on the second sacrificial film and the first sacrificial film using a resist as a mask. Performing a step of providing an opening reaching the plug surface, and performing isotropic etching on the opening to etch a side wall of the first sacrificial film relatively larger than a side wall of the second sacrificial film. It is characterized by having.

In the method for manufacturing a semiconductor memory device according to the present invention, preferably, the step of forming an adhesion layer on the sacrificial film includes the steps of:
Forming a step of forming the adhesion layer on an upper portion and a side wall of the second sacrificial film. In the method for manufacturing a semiconductor memory device according to the present invention, preferably, the first sacrificial film is a PS film.
G (phosphosilicate glass)
And the second sacrificial film is NSG (non-dop).
ed silica glass). Alternatively, in the method for manufacturing a semiconductor memory device according to the present invention, preferably, the first sacrificial film is BPSG (bo
ro-phosphosilicate glass
s), wherein the second sacrificial film is made of NSG. The method for manufacturing a semiconductor memory device according to the present invention includes:
Preferably, the adhesion layer and the second layer above the adhesion layer
The step of removing the metal layer and forming the lower electrode is a step of performing chemical mechanical polishing (CMP) on the entire surface until the second sacrificial film is removed.

In the method of manufacturing a semiconductor memory device according to the present invention, preferably, the plug is made of silicon, and the lower electrode is made of tungsten. Or,
In the method of manufacturing a semiconductor memory device according to the present invention, preferably, the plug is made of silicon, and the lower electrode is made of tungsten nitride. In the method for manufacturing a semiconductor memory device according to the present invention, preferably, the sacrificial film is made of silicon oxide. In the method of manufacturing a semiconductor memory device according to the present invention, preferably, the adhesion layer and the barrier layer are made of titanium or a laminated film of titanium and titanium nitride. In the method for manufacturing a semiconductor memory device according to the present invention, preferably, the capacitor insulating film is made of tantalum oxide.

Thus, it is possible to prevent the adhesion layer or the barrier layer from being deposited on the side wall of the opening provided in the sacrificial film. Therefore, the barrier layer can be formed only on the contact hole and in the vicinity thereof, and it is possible to suppress the capacitance loss and the leak current at the electrode side wall while preventing the reaction between the plug material and the lower electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming an interlayer insulating film on a semiconductor substrate; and forming a contact hole reaching the surface of the semiconductor substrate in the interlayer insulating film. Forming a plug made of a conductor in the contact hole; forming a barrier layer on the entire surface; forming a sacrificial film on the entire upper surface of the barrier layer; Forming an adhesion layer on the entire surface of the upper layer, providing an opening in the adhesion layer above the contact hole, and forming an opening reaching the plug surface in the sacrificial film above the contact hole using the adhesion layer as a mask. Providing, forming a metal layer on the entire surface including the side wall of the opening, removing the adhesion layer and the metal layer on the adhesion layer, Forming a cylindrical lower electrode,
A step of removing the sacrificial film, a step of etching and removing the barrier layer using the lower electrode as a mask, a step of forming a capacitor insulating film made of a dielectric on a surface of the lower electrode, and a surface of the capacitor insulating film And forming an upper electrode.

According to the method of manufacturing a semiconductor memory device of the present invention described above, the lower barrier layer is etched using the lower electrode (metal layer) made of, for example, tungsten or tungsten nitride as a mask. The barrier layer can be formed only on the bottom surface of the substrate. This makes it possible to prevent a reaction between the plug material and the electrode material and to suppress a capacitance loss or an increase in leakage current of the capacitor due to the barrier layer on the electrode side wall. In addition, when depositing a metal layer serving as a lower electrode on a sacrificial film made of, for example, an oxide film, an adhesion layer is formed on the sacrificial film. ) Can be formed.

[0026]

Embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1A is a cross-sectional view showing a storage node electrode portion of a semiconductor memory device of this embodiment. A contact hole 3 is provided in the interlayer insulating film 1, and a polysilicon plug 4 is formed in the contact hole 3. A cylindrical lower electrode 8 is formed above the polysilicon plug 4 with a barrier layer 5 interposed therebetween. A capacitor insulating film 9 and an upper electrode 10 are formed so as to cover the lower electrode 8. No barrier layer or adhesion layer is formed on the side wall of the lower electrode 8.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described. First, as shown in FIG. 1B, an interlayer insulating film 1 made of, for example, a silicon oxide film is used.
Next, a contact hole 3 is formed by etching.
After a polysilicon layer is formed on the entire surface so as to fill the contact hole 3, the polysilicon layer on the interlayer insulating film 1 is removed by etch back or CMP. Thus, a polysilicon plug 4 is formed. Or,
An amorphous silicon layer may be formed instead of the polysilicon layer and crystallized by heating. The silicon embedded as a plug in the contact hole may be polysilicon or amorphous silicon as long as it contains impurities and is conductive.

A silicon nitride film (Si ₃ N ₄ layer) 2 is formed on the interlayer insulating film 1 in which the plug 4 made of silicon is embedded by, for example, a low pressure CVD method. Si ₃ N ₄
The layer 2 functions as an etching stopper layer. Si
_A first oxide film 6 on the ₃ N ₄ layer 2 and a first oxide film 6
A second oxide film 6 'having a lower etching rate than the second oxide film 6' is stacked. The first oxide film 6 is a sacrificial film for forming a cylindrical capacitor electrode, and has a thickness approximately equal to the height of the capacitor electrode. The second oxide film 6 'is the first oxide film 6
And is formed sufficiently thinner than the first oxide film 6.

In order to make the etching rates of the first oxide film 6 and the second oxide film 6 ′ different, for example, the first oxide film 6 is made of a PSG (phospho) containing phosphorus or boron.
(silicate glass) or BPSG (b
oro-phosphosilicate glass
s), an NSG (nondop) is formed on the second oxide film 6 ′.
ed natural silica glass
s) may be used. Further, instead of the second oxide film 6 ', a layer having a small etching selectivity to the first oxide film 6, such as a silicon nitride film, may be formed.

Next, as shown in FIG. 2A, the second oxide film 6 'is etched using a resist (not shown) as a mask to provide an opening. After removing the resist, the first oxide film 6 is etched using the patterned second oxide film 6 ′ as a mask to expose the upper surface of the plug 4. The etching of the first oxide film 6 and the second oxide film 6 ′ is preferably performed by anisotropic dry etching such as reactive ion etching (RIE).

Next, as shown in FIG. 2B, isotropic etching is performed in the openings formed in the first oxide film 6 using hydrofluoric acid or the like. At this time, since there is a difference in the etching selectivity between the first oxide film 6 and the second oxide film 6 ′,
The side wall portion of the first oxide film 6 is etched more (overhang) than the side wall portion of the oxide film 6 ′,
The opening has a narrow trench.

Subsequently, as shown in FIG. 3A, a laminated film of a Ti layer and a TiN layer (hereinafter referred to as Ti / TiN) is formed by a highly directional film forming method such as collimated sputtering.
(TiN layer) is formed. This film formation is performed while preventing the Ti / TiN layer from being deposited on the side wall of the opening provided in the first oxide film 6. The Ti / TiN layer deposited on the upper surface of the interlayer insulating film 1 and the plug 4 functions as a barrier layer 5. Further, the Ti / TiN layer deposited on the upper and side surfaces of the second oxide film 6 ′ is formed by the second oxide film 6 ′ and the lower electrode 8.
Functions as an adhesion layer 7 with the metal material.

After forming the Ti / TiN layer, heat treatment at about 650 ° C., preferably RTA (rapid thermal)
annealing) to make the polysilicon plug 4
React with the Ti layer to form silicide. Thereby, contact resistance between polysilicon plug 4 and a capacitor electrode formed in an upper layer can be reduced. In addition, this heat treatment densifies the TiN layer,
The function as the adhesion layer 7 is improved.

Next, as shown in FIG. 3B, a tungsten layer (W layer) or a tungsten nitride layer (WN layer) serving as a lower electrode of the capacitor electrode is formed on the entire surface including the side wall of the first oxide film 6. ) 8 is formed. The W or WN layer 8 can be formed by sputtering or metal CVD. Here, a sacrificial film (second oxide film 6 ')
Since the adhesion layer 7 made of a Ti / TiN layer is formed on the upper part of the substrate, delamination with the W or WN layer 8 is prevented.

Next, as shown in FIG. 4A, CMP is performed on the entire surface until the second oxide film 6 'is removed. This C
By the MP process, the adhesion layer 7 and the W or WN layer 8 formed on the upper and side surfaces of the second oxide film 6 'are removed. As a result, the barrier layer 5 is formed only on the bottom portion that is in contact with the polysilicon plug 4, and the cylinder-type lower electrode 8 without the adhesion layer is formed on the side wall. Subsequently, FIG.
As shown in (B), the first oxide film 6 between the electrodes is removed by wet etching using, for example, hydrofluoric acid.

Alternatively, FIGS. 4A and 4B
In the step shown in FIG. 5, the opening above the polysilicon plug 4 is buried using, for example, a silicon oxide film (not shown), and the CMP is performed.
Instead, the entire surface may be etched back. The entire surface is etched back until the second oxide film 6 ′ is removed, and the adhesion layer 7 formed on the upper and side surfaces of the second oxide film 6 ′ is formed.
And the W or WN layer 8 are removed, and the cylindrical lower electrode 8 is removed.
To form Thereafter, the first oxide film 6 and the buried oxide film (not shown) between the electrodes are removed by, for example, wet etching using hydrofluoric acid. As a result, FIG.
The structure is as shown in FIG.

Either when the second oxide film 6 'is removed by CMP or when the entire surface is etched back,
When a tungsten (W) layer is used as the lower electrode, after exposing the side wall of the lower electrode 8, a nitriding treatment is performed on the surface to form an oxidation prevention layer (not shown). Next, FIG.
As shown in FIG. 2A, after a Ta ₂ O ₅ layer is deposited as the capacitor insulating film 9, in order to reduce the leak current of the Ta ₂ O ₅ layer, the capacitor insulating film 9 is placed in an O ₂ or O ₃ atmosphere at 500 to 600 ° C. To perform annealing. Subsequently, a metal film such as Ti is deposited as the upper electrode 10 by, for example, sputtering. After that, leaving the desired region, the upper electrode 1
0, the capacitor insulating film 9 and the Si ₃ N ₄ layer 2 are removed to form the storage node electrode of the present embodiment.

According to the method of forming a semiconductor memory device of the present embodiment, a cylinder type capacitor having the barrier layer 5 only under the electrode and having no adhesion layer on the side wall of the electrode can be formed. It is possible to reduce the loss and the leak current on the electrode side wall.

(Embodiment 2) In this embodiment, the opening of the oxide film for forming the cylinder type lower electrode is formed in an inversely tapered shape, thereby preventing the adhesion layer from being deposited on the side wall of the opening. In the first embodiment, as shown in FIG. 2A, the first oxide film 6 is etched using the second oxide film 6 ′ as a mask.
No second oxide film is formed as shown in FIG.

Hereinafter, a method for manufacturing the semiconductor memory device according to the present embodiment will be described. First, a contact hole 3 is provided in an interlayer insulating film 1 as in the first embodiment, and a polysilicon plug 4 is formed in the contact hole 3. An Si ₃ N ₄ layer 2 is formed as an etching stopper layer on the interlayer insulating film 1 including the contact hole 3. An oxide film 6 serving as a sacrificial film for forming a cylinder electrode is formed thereon. Next, as shown in FIG. 5A, the oxide film 6 is etched using a resist (not shown) as a mask, and an opening reaching the contact hole 3 is formed. This etching is performed under conditions where sputtering on the side wall of the opening is unlikely to occur (for example, by reducing the ratio of a halogen-based gas, etc.).
(Conditions for weakening the side wall protection). Thereby, the cross section of the opening has an inversely tapered shape.

After that, as in the step shown in FIG. 3A of the first embodiment, except for the side wall of the opening provided in the oxide film 6, T
An i / TiN layer is formed. The Ti / TiN layer is formed by a highly directional film forming method such as collimated sputtering. The Ti / TiN layer deposited on the bottom of the opening (the upper surface of the polysilicon plug 4) becomes the barrier layer 5,
The Ti / TiN layer deposited on the surface of oxide film 6 becomes an adhesion layer. Subsequently, a heat treatment (RTA) at about 650 ° C. is performed to react the surface of the polysilicon plug 4 with the Ti layer to form silicide, thereby reducing the contact resistance on the polysilicon plug 4. In this heat treatment step, the densification of the TiN layer as the adhesion layer is also performed.

Further, similarly to the step shown in FIG.
A tungsten layer (W layer) or a tungsten nitride layer (WN layer) 8 serving as a lower electrode of the capacitor electrode is formed on the entire surface including the side wall of the oxide film 6 by sputtering or metal CVD. Here, since the upper portion of the oxide film 6 is covered with the Ti / TiN layer serving as an adhesion layer, delamination of the W or WN layer 8 is prevented. FIG.
In the same manner as in the steps shown in FIGS. 3A and 3B, the adhesion layer and the W or WN layer 8 on the surface of the oxide film 6 are removed by CMP or whole-surface etch-back to form a cylindrical lower electrode 8. Further, the oxide film 6 between the electrodes (the oxide film 6 and the buried oxide film in the case of the whole etch back) is removed.

Thereafter, as shown in FIG. 5B, for example, a Ta ₂ O ₅ layer is deposited as a capacitor insulating film 9 on the lower electrode 8 made of W or WN,
Annealing in O ₂ or O ₃ atmosphere at Ta ₂ O
Reduce the leakage current of _five layers. Subsequently, a metal film such as Ti is deposited as the upper electrode 10 by, for example, sputtering. After that, the upper electrode 10,
The capacitor insulating film 9 and the Si ₃ N ₄ layer 2 are removed to form a storage node electrode. According to the manufacturing method of the semiconductor memory device of the present embodiment, the cylinder type capacitor having the barrier layer 5 only under the electrode and having no adhesion layer on the side wall of the electrode can be formed. As a result, the capacity loss of the capacitor,
It is possible to reduce the leak current on the electrode side wall.

(Embodiment 3) FIG. 6A is a sectional view showing a storage node electrode portion of a semiconductor memory device of this embodiment. A contact hole 3 is provided in the interlayer insulating film 1, and a polysilicon plug 4 is formed in the contact hole 3. A cylindrical lower electrode 8 is formed above the polysilicon plug 4 with a barrier layer 5 interposed therebetween. A capacitor insulating film 9 and an upper electrode 10 are formed so as to cover the lower electrode 8. No barrier layer or adhesion layer is formed on the side wall of the lower electrode 8.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described. First, as shown in FIG. 6B, an interlayer insulating film 1 made of, for example, a silicon oxide film is formed.
Next, a contact hole 3 is formed by etching.
After a polysilicon layer is formed on the entire surface so as to fill the contact hole 3, the polysilicon layer on the interlayer insulating film 1 is removed by etch back or CMP. Thus, a polysilicon plug 4 is formed. Or,
An amorphous silicon layer may be formed instead of the polysilicon layer and crystallized by heating. The silicon embedded as a plug in the contact hole may be polysilicon or amorphous silicon as long as it contains impurities and is conductive.

A Ti layer and a TiN layer (hereinafter, referred to as an upper layer) are formed on the interlayer insulating film 1 in which the plugs 4 made of silicon are embedded.
(Ti / TiN layer) are laminated to form the adhesion layer 5. A silicon nitride film (Si ₃ N ₄ layer) as an etching stopper layer on the adhesion layer 5 by, for example, a low pressure CVD method.
2 ′ is formed, and an oxide film 6 is formed on the Si ₃ N ₄ layer 2 ′. Oxide film 6 is a sacrificial film for forming a cylindrical capacitor electrode, and has a thickness approximately equal to the height of the capacitor electrode. On the oxide film 6, a TiN layer serving as an adhesion layer 7 between the oxide film 6 and the lower electrode 8 is formed by a method such as sputtering. Thereafter, heat treatment at about 650 ° C., preferably RTA, is performed to react the surface of the polysilicon plug 4 with the Ti layer of the barrier layer 5 to form silicide.
Thereby, the contact resistance between polysilicon plug 4 and the capacitor electrode formed in the upper layer is reduced.

Next, as shown in FIG. 7A, the adhesive layer 7 is etched using a resist (not shown) as a mask, and then the resist is removed. The oxide film 6 and the Si ₃ N ₄ layer 2 ′ are etched by using the patterned adhesion layer 7 as a mask to expose the barrier layer 5 on the upper surface of the plug 4. The etching of the oxide film 6 and the Si ₃ N ₄ layer 2 ′ is preferably performed by anisotropic dry etching such as reactive ion etching (RIE).

Next, as shown in FIG.
A tungsten layer (W layer) or a tungsten nitride layer (WN layer) 8 serving as a lower electrode of a capacitor electrode is formed on the entire surface including the side wall of the substrate. The W or WN layer 8 is formed by
It can be performed by sputtering or metal CVD. Here, the upper surface of the polysilicon plug 4 and the exposed portion of the interlayer insulating film 1 are made of Ti / T
covered with an iN layer, a polysilicon plug 4
And the lower electrode material is prevented from reacting. The oxide film 6
Since the adhesion layer 7 is formed on the upper layer, delamination between the oxide film 6 and the W or WN layer 8 is prevented.

Next, as shown in FIG.
CMP is performed on the entire surface until is removed. By this CMP step, the W or WN layer 8 formed on the adhesion layer 7 is removed. Subsequently, as shown in FIG. 8B, the oxide film 6, the Si ₃ N ₄ layer 2 ′ and the barrier layer 5 are etched using the lower electrode 8 as a mask. As a result, the barrier layer 5 is formed only on the bottom portion that is in contact with the polysilicon plug 4, and the cylinder-type lower electrode 8 without the adhesion layer is formed on the side wall.

Alternatively, FIGS. 8A and 8B
In the step shown in FIG. 5, the opening above the polysilicon plug 4 is buried using, for example, a silicon oxide film (not shown), and the CMP is performed.
Instead, the entire surface may be etched back. Adhesion layer 7
By performing a full etch back until is removed,
The W or WN layer 8 above the adhesion layer is removed to form a cylindrical lower electrode 8. Thereafter, using the lower electrode 8 as a mask, the oxide film 6, a buried oxide film (not shown), Si ₃ N
_{The four} layers 2 ′ and the barrier layer 5 are etched. Thus, a structure as shown in FIG. 8B is obtained.

In the case where the adhesion layer 7 is removed by CMP or the whole surface is etched back, when a tungsten (W) layer is used as the lower electrode, after the sidewall of the lower electrode 8 is exposed, An oxidation preventing layer (not shown) is formed by performing nitriding on the surface. Next, as shown in FIG. 6A, for example, a Ta ₂ O ₅ layer is deposited as a capacitor insulating film 9 on a lower electrode made of W or WN.
Annealing is performed in an O ₂ or O ₃ atmosphere at 500 to 600 ° C. to reduce the leak current of the Ta ₂ O ₅ layer. Subsequently, a metal film such as Ti is deposited as the upper electrode 10 by, for example, sputtering. Thereafter, by removing the upper electrode 10 and the capacitor insulating film 9 while leaving a desired region, the storage node electrode of the present embodiment is formed.

According to the method of manufacturing the semiconductor memory device of the embodiment of the present invention, the barrier layer is provided only under the electrode,
A cylindrical capacitor having no adhesion layer can be formed on the electrode side wall. As a result, it is possible to reduce capacitance loss and leakage current of the capacitor caused by the adhesion layer or the barrier layer on the electrode side wall. In addition, since a barrier layer is formed at the interface between the polysilicon plug that electrically connects the transistor and the capacitor and the lower electrode of the capacitor, the reaction between the plug material (particularly polysilicon) and the electrode material is prevented. You.

According to the semiconductor memory device of the embodiment of the present invention, the capacitance loss and the leak current are reduced, and the effective area of the capacitor can be used effectively. Therefore, the area of the capacitor electrode pair can be reduced, and the height of the cylinder electrode can be reduced. As a result, the aspect ratio of the contact hole formed around the capacitor is reduced, and the memory cell can be miniaturized, so that the capacity of the semiconductor memory device can be increased.

Embodiments of the semiconductor memory device and the method of manufacturing the same according to the present invention are not limited to the above description. For example,
As the capacitor insulating film, in addition to the above Ta ₂ O ₅ , yttrium oxide (Y ₂ O ₃ ), STO (SrTiO ₃ ),
BTO (BaTiO ₃ ) or BSTO (Ba _1-x S
A high dielectric film made of a perovskite oxide such as (r _x TiO ₃ ) may be formed. In addition, various changes can be made without departing from the gist of the present invention.

[0055]

According to the semiconductor memory device of the present invention, it is possible to prevent the loss of capacitance due to the adhesion layer or the barrier layer on the side wall of the electrode and the increase in leakage current of the capacitor insulating film.
On the other hand, since the barrier layer is formed below the capacitor, the reaction between the plug material and the electrode material is prevented. Thereby, the effective area of the capacitor is secured, and the area of the capacitor electrode pair can be reduced, so that the capacity of the semiconductor memory device can be increased. According to the method for manufacturing a semiconductor memory device of the present invention, a barrier layer can be formed only under the electrode without forming an adhesion layer or a barrier layer on the side wall of the cylinder electrode. Accordingly, it is possible to suppress a capacity loss and a leak current in the electrode side wall while preventing a reaction between the plug material and the lower electrode.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view illustrating a storage node electrode portion of a semiconductor memory device according to a first embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to Embodiment 1 of the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to Embodiment 1 of the present invention.

FIGS. 4A and 4B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to Embodiment 1 of the present invention.

FIG. 5A is a cross-sectional view showing a manufacturing step of the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view illustrating a storage node electrode portion of the semiconductor storage device according to the second embodiment of the present invention.

FIG. 6A is a cross-sectional view illustrating a storage node electrode portion of a semiconductor memory device according to a third embodiment of the present invention, and FIG.
FIG. 14 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing the semiconductor storage device according to the third embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to Embodiment 3 of the present invention.

FIGS. 8A and 8B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention.

FIGS. 9A and 9B are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor memory device.

10A is a cross-sectional view illustrating a manufacturing process of a conventional method for manufacturing a semiconductor memory device, and FIG. 10B is a cross-sectional view illustrating a storage node electrode portion of the conventional semiconductor memory device.

FIGS. 11A and 11B are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor memory device.

FIG. 12A is a cross-sectional view illustrating a manufacturing process of a conventional method of manufacturing a semiconductor memory device, and FIG. 12B is a cross-sectional view illustrating a storage node electrode portion of the conventional semiconductor memory device.

[Explanation of symbols]

1 ... interlayer insulation film, 2,2 '... etching stopper layer (Si ₃ N ₄ layers), 3 ... contact hole, 4 ... (polysilicon) plugs, 5 ... barrier layer (Ti / TiN layer),
6 ... (first) oxide film, 6 '... second oxide film, 7 ... adhesion layer (Ti / TiN layer), 8 ... lower electrode (W or WN)
Layers), 9: capacitor insulating film, 10: upper electrode.

Claims (35)

[Claims] A semiconductor substrate on which an active element is formed; an interlayer insulating film formed on the semiconductor substrate; a contact hole provided in the interlayer insulating film and reaching a surface of the active element; A plug formed of a conductor, formed in the hole, a barrier layer formed on the surface of the interlayer insulating film so as to cover at least an upper portion of the plug, and a bottom surface formed on the barrier layer, A cylindrical lower electrode formed of a side surface formed upward from the bottom surface; a capacitor insulating film formed of a dielectric formed on the surface of the lower electrode; and an upper electrode formed on the surface of the capacitor insulating film. A semiconductor memory device having: 2. The semiconductor memory device according to claim 1, wherein said plug is made of silicon, and said lower electrode is made of tungsten. 3. The semiconductor memory device according to claim 1, wherein said plug is made of silicon, and said lower electrode is made of tungsten nitride. 4. The semiconductor memory device according to claim 1, wherein said barrier layer is made of titanium. 5. The semiconductor memory device according to claim 1, wherein said barrier layer comprises a laminated film of titanium and titanium nitride. 6. The semiconductor memory device according to claim 1, wherein said capacitor insulating film is made of tantalum oxide. 7. The semiconductor memory device according to claim 1, wherein said upper electrode is made of titanium. 8. A step of forming an interlayer insulating film on a semiconductor substrate, a step of providing a contact hole reaching the surface of the semiconductor substrate in the interlayer insulating film, and a step of forming a plug made of a conductor in the contact hole. Forming a sacrificial film on the entire surface; providing an opening in the sacrificial film above the contact hole up to the plug surface and having an upper end narrower than the lower end; Forming an adhesion layer on top of the sacrificial film and forming a barrier layer on the bottom of the opening by forming a metal layer of the following; and forming a second metal layer on the entire surface including the side wall of the opening. Forming; forming the cylindrical lower electrode in the opening by removing the adhesion layer and the second metal layer above the adhesion layer; removing the sacrificial film; Electric On the surface of the manufacturing method of the semiconductor memory device having a step of forming a capacitor insulating film made of a dielectric, and forming an upper electrode on the surface of the capacitor insulating film. 9. The step of removing the adhesion layer and the second metal layer above the adhesion layer to form the lower electrode,
Until the adhesion layer is removed, chemical mechanical polishing (C
9. The method for manufacturing a semiconductor memory device according to claim 8, wherein the step (MP) is performed. 10. The step of removing said adhesion layer and said second metal layer above said adhesion layer and forming said lower electrode includes forming a buried sacrificial film in said opening and performing etch-back on the entire surface. 9. The method according to claim 8, wherein the step of removing the sacrificial film is a step of removing the sacrificial film and the buried sacrificial film. 11. The step of forming the sacrificial film over the entire surface includes the step of forming a first sacrificial film and the step of forming a first sacrificial film on the first sacrificial film with a thickness sufficiently greater than that of the first sacrificial film. Forming a second sacrificial film that is thin and has a small etching selectivity, wherein the step of providing the opening in the sacrificial film is performed in such a manner that the diameter of the opening in the second sacrificial film is the first sacrificial film. 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein the step of performing etching is performed so as to be relatively narrower than the diameter of the opening in the sacrificial film. 12. The step of providing the opening in the sacrificial film,
Performing anisotropic etching on the second sacrificial film and the first sacrificial film using a resist as a mask to form an opening reaching the plug surface; performing isotropic etching on the opening; 12. The method according to claim 11, further comprising: etching a side wall of the sacrificial film relatively larger than a side wall of the second sacrificial film. 13. The method of manufacturing a semiconductor memory device according to claim 11, wherein said step of forming an adhesion layer on said sacrificial film is a step of forming said adhesion layer on an upper portion and a side wall of said second sacrificial film. . 14. The first sacrificial film is made of PSG (phosp).
and the second sacrificial layer is made of non-doped silicide (NSG).
12. The method of manufacturing a semiconductor memory device according to claim 11, wherein the method comprises: (cate glass). 15. The first sacrificial film is formed of BPSG (boro).
-Phosphosilicate glass, and the second sacrificial layer is NSG (non-doped).
12. A glass composition comprising:
The manufacturing method of the semiconductor memory device described in the above. 16. The step of removing said adhesion layer and said second metal layer above said adhesion layer and forming said lower electrode comprises chemically mechanical polishing the entire surface until said second sacrificial film is removed. The method of manufacturing a semiconductor memory device according to claim 11, wherein the method is a step of performing (CMP). 17. The method according to claim 8, wherein said plug is made of silicon, and said lower electrode is made of tungsten. 18. The method according to claim 8, wherein said plug is made of silicon, and said lower electrode is made of tungsten nitride. 19. The method according to claim 8, wherein said sacrificial film is made of silicon oxide. 20. The method according to claim 8, wherein said adhesion layer and said barrier layer are made of titanium. 21. The method according to claim 8, wherein the adhesion layer and the barrier layer are formed of a laminated film of titanium and titanium nitride. 22. The method according to claim 8, wherein said capacitor insulating film is made of tantalum oxide. 23. A step of forming an interlayer insulating film on a semiconductor substrate; a step of providing a contact hole reaching the surface of the semiconductor substrate in the interlayer insulating film; and a step of forming a plug made of a conductor in the contact hole. Forming a barrier layer over the entire surface; forming a sacrificial film over the entire upper layer of the barrier layer; forming an adhesive layer over the entire upper surface of the sacrificial film; A step of providing an opening in the adhesion layer, a step of providing an opening reaching the plug surface in the sacrificial film above the contact hole using the adhesion layer as a mask, and forming a metal on the entire surface including the side wall of the opening. Forming a layer; removing the adhesion layer and the metal layer above the adhesion layer to form a cylindrical lower electrode in the opening; and removing the sacrificial film. Removing; removing the barrier layer by etching using the lower electrode as a mask; forming a capacitor insulating film made of a dielectric on the surface of the lower electrode; and forming an upper portion on the surface of the capacitor insulating film. Forming a semiconductor device. 24. The step of removing the adhesion layer and the metal layer above the adhesion layer and forming the lower electrode includes chemically mechanical polishing (CM) until the adhesion layer is removed.
24. The method for manufacturing a semiconductor memory device according to claim 23, wherein the step (P) is performed. 25. The step of removing the adhesion layer and the metal layer above the adhesion layer and forming the lower electrode is a step of forming a buried sacrificial film in the opening and performing etch back on the entire surface. 24. The method according to claim 23, wherein the step of removing the sacrificial film is a step of removing the sacrificial film and the buried sacrificial film. 26. The method according to claim 23, wherein said plug is made of silicon and said lower electrode is made of tungsten. 27. The method according to claim 23, wherein said plug is made of silicon and said lower electrode is made of tungsten nitride. 28. The method according to claim 23, wherein said sacrificial film is made of silicon oxide. 29. The adhesive layer according to claim 23, comprising titanium.
The manufacturing method of the semiconductor memory device described in the above. 30. The method according to claim 23, wherein said adhesion layer is made of titanium nitride. 31. The method for manufacturing a semiconductor memory device according to claim 23, wherein said adhesion layer comprises a laminated film of titanium and titanium nitride. 32. The barrier layer is made of titanium.
4. The method for manufacturing a semiconductor memory device according to item 3. 33. The method according to claim 23, wherein said barrier layer is made of titanium nitride. 34. The method according to claim 23, wherein said barrier layer comprises a laminated film of titanium and titanium nitride. 35. The method according to claim 23, wherein said capacitor insulating film is made of tantalum oxide.