JP4841027B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a rare metal layer and a semiconductor device having a rare metal layer.
[0002]
[Prior art]
In semiconductor integrated circuit devices, higher integration is increasingly required. In a semiconductor memory device using a capacitor, it is necessary to make the capacitor with a three-dimensional three-dimensional structure along with miniaturization of memory cells. A typical example of the three-dimensional structure is a cylinder type capacitor having a cup-shaped lower electrode. By using not only the inner surface of the cup-shaped lower electrode but also the outer surface as the capacitor electrode surface, the electrode area can be increased.
[0003]
A capacitor can be viewed as a combination of a lower electrode, a dielectric film, and an upper electrode. In the three-dimensional structure, the lower electrode has a three-dimensional structure, and a dielectric film and an upper electrode are formed on the surface. For example, a sacrificial film is used to produce a capacitor having a cylinder structure. An opening for forming a cylinder is formed in the sacrificial film, and a lower electrode is formed on the inner surface of the opening. In order to use the outer surface of the cylinder as the capacitor electrode surface, the sacrificial film outside the cylinder is removed after the cylinder-type lower electrode is formed. Thereafter, a dielectric film and an upper electrode are formed.
[0004]
There are various problems to be solved in order to form a fine capacitor structure having a three-dimensional structure with high reliability.
[0005]
In order to reduce the capacitor electrode area and ensure sufficient capacity, the capacitor dielectric film is made of a high dielectric material having a high dielectric constant, such as tantalum oxide (the stoichiometric composition is abbreviated as Ta ₂ O ₅ , TaO). )), It is desirable to form. Here, the high dielectric constant refers to a relative dielectric constant of about 20 or more.
[0006]
When the capacitor dielectric film is formed of a ferroelectric, a nonvolatile memory that can maintain a memory state even when the power supply is disconnected can be configured. Ferroelectric materials include strontium titanate (abbreviated as SrTiO ₃ , STO), barium titanate strontium (abbreviated as Ba _x Sr _1-x TiO ₃ .BST), lead zirconate titanate (Pb _{1- x} Zr _x TiO _3, abbreviated as PZT) or the like is used.
[0007]
These dielectrics are oxides, and it is desirable to perform heat treatment (annealing) in an oxidizing atmosphere containing oxygen after film formation. For this reason, it is desired that the lower electrode be formed of a metal having high oxidation resistance, a metal that maintains conductivity even when oxidized, or an oxide thereof. As such metals, rare metals such as Ru, Ir, and Pt have been studied. The rare metal is a concept including a noble metal.
[0008]
There are several problems when using rare metals as electrodes and wiring. Rare metals have poor adhesion to insulating films such as silicon oxide (abbreviated as SiO ₂ and SiO) and silicon nitride (abbreviated as SiN _x and SiN). The insulating film formed on the rare metal layer easily peels off. In order to enhance the adhesion between the insulating film and the rare metal layer, it has been studied to insert a metal or metal nitride adhesion layer between the rare metal layer and the insulating layer.
[0009]
However, when the metal nitride film is in direct contact with the oxide dielectric, it has the property of depriving the oxide dielectric of oxygen and degrading the dielectric properties of the oxide dielectric. Therefore, it is necessary to remove the adhesion layer in the region where the oxide dielectric film is formed on the rare metal layer.
[0010]
In a highly integrated memory device, the capacitor electrode is formed of an extremely thin rare metal layer. It is difficult to form an extremely thin rare metal layer without defects or pinholes.
[0011]
[Problems to be solved by the invention]
As described above, in a semiconductor memory device, various problems to be solved have arisen as the structure is miniaturized.
[0012]
A first object of the present invention is to provide a semiconductor device manufacturing method capable of preventing destruction and deterioration of other components when forming a cylinder type capacitor.
[0013]
A second object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device suitable for miniaturization.
[0014]
A third object of the present invention is to provide a highly reliable semiconductor device suitable for miniaturization.
[0015]
[Means for Solving the Problems]
According to one aspect of the present invention,
(A) forming a metal or metal compound plug in the first insulating layer disposed on the semiconductor substrate;
(A) forming a second insulating layer on the first insulating layer;
(C) forming an opening through the second insulating layer to expose the plug surface on the bottom surface;
(D) A metal or metal nitride adhesion layer is formed in a cylindrical shape on the inner surface of the opening, and further a rare metal electrode layer of any one of Ru, Ir, and Pt and a protective dielectric covering the inner surface of the electrode layer Forming a film, wherein the protective dielectric film is formed of a material having etching characteristics different from those of the first and second insulating layers and the metal or metal compound;
(E) removing the second insulating layer outside the cylinder by etching with the inner surface of the cylindrical electrode layer covered with the protective dielectric film ;
(F) After the step (e), with the inner surface of the cylindrical electrode layer covered with the protective dielectric film, the exposed adhesion layer is removed by wet etching;
Only contains, in the wet etching, the etching rate of the protective dielectric film manufacturing method of a semiconductor device, wherein the lower than the etching rate of the adhesion layer.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The present inventors have found that when a cylindrical capacitor is made, the electrical contact between the lower electrode and the plug may be impaired. The upper part of the plug has disappeared and the connection with the lower electrode has been lost. As a cause of this, it was considered that the chemical solution penetrates the rare metal layer during wet etching.
[0017]
After the adhesion layer and the lower electrode layer are laminated on the sacrificial film having the opening formed to form the cylindrical lower electrode, the sacrificial film formation and the exposed adhesion layer are removed by wet etching. In this removal step, when the chemical solution permeates from the inside to the outside of the cylinder-type lower electrode, the plug disposed under the cylinder-type lower electrode is dissolved.
[0018]
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
As shown in FIG. 1A, a SiO isolation region 12 is formed on the surface of a Si substrate 11 having a p-type surface region by shallow trench isolation (STI). An insulated gate electrode 13 is formed on the surface of the active region defined by the isolation region 12.
[0020]
As shown in FIG. 1 (B), the insulated gate electrode is formed on the gate insulating film 21 of the SiO layer formed on the Si surface, the lower layer gate electrode 22 of polycrystalline silicon formed thereon, and thereon. An upper gate electrode 23 such as tungsten silicide (abbreviated as WSi), an etch stopper layer 24 such as SiN formed thereon, and silicon nitride (abbreviated as SiN _x , SiN) covering the side wall of the gate electrode, etc. Side wall etch stopper 25. For simplification of illustration, the insulated gate electrode is also shown in a simplified configuration 13 in the following drawings.
[0021]
N-type impurities are ion-implanted using the insulated gate electrode 13 as a mask to form source / drain regions S / D. Thereafter, a first interlayer insulating film 14 made of SiO or the like is formed so as to cover the insulating gate electrode 13. A contact hole is opened at a required portion of the first interlayer insulating film 14 to form a plug 15 of polycrystalline silicon. The plug is formed by deposition by chemical vapor deposition (CVD) and removal of unnecessary portions by chemical mechanical polishing (CMP), etch back, or the like.
[0022]
Thereafter, a second interlayer insulating film 16 such as SiO or BPSG is formed on the entire surface of the substrate. Note that the second interlayer insulating film 16 once deposits an insulating layer to an intermediate level, forms the bit line BL, and then deposits the remaining insulating layer so as to fill the bit line BL.
[0023]
As shown in FIG. 1C, after forming the insulating film 16-1, a required connection hole is formed to expose the surface of the bit line plug. Next, for example, a bit line layer composed of a Ti layer, a TiN layer, and a W layer is formed from below, and an SiN layer is formed on the surface thereof. A resist pattern is formed on the SiN layer, and the SiN layer, W layer, TiN layer, and Ti layer are patterned to form a pattern including the bit line 27 and the etching stopper SiN layer 28.
[0024]
Further, an SiN layer is formed and anisotropic etching such as reactive ion etching (RIE) is performed to form an SiN sidewall etch stopper 29 that protects the bit line sidewall. Thereafter, an insulating film 16-2 such as SiO or BPSG is formed, and the surface is planarized by CMP or the like.
[0025]
In this way, the second interlayer insulating film 16 including the bit line BL is formed. In the second interlayer insulating film 16, the above-described SiN layer 28 is exposed above the bit line.
[0026]
A connection hole that penetrates through the second interlayer insulating film 16 and reaches the storage node plug 15 is formed on the bit line by a self-aligned contact method (SAC). After forming a Ti layer and a TiN layer in the connection hole, W blanket growth by CVD is performed so as to fill the inside of the connection hole. The W layer, TiN layer, and Ti layer on the second interlayer insulating film 16 are removed by CMP or etch back. In this way, the W plug 17 is formed. The plug may be formed of a metal compound such as TiN or WN in addition to a metal such as W.
[0027]
As shown in FIG. 1D, the substrate temperature is set to the SiN film formation temperature, and a mixed gas of ammonia gas and polychlorosilane such as dichlorosilane or polysilane is supplied to the surface of the second interlayer insulating film 16. A SiN layer 31 is formed by CVD. The SiN layer 31 covers the surface of the W plug 17 and has a function as an etch stopper in etching an oxide film formed thereon.
[0028]
As shown in FIG. 2A, after the SiN layer 31 is formed, the SiO layer 32 is formed, and the SiN layer 33 is further formed. The SiN layer 33 functions as an etch stopper in etching a sacrificial film such as an oxide film formed thereon. The SiN layers 31 and 33 are both 40 nm thick, for example, and the SiO layer 32 is 100 nm thick. The first etch stopper layer 31, the intermediate layer 32, and the second etch stopper layer 33 are stacked layers constituting a pedestal in order to enhance the supporting force for the lower electrode of the capacitor to be formed later.
[0029]
The etch stopper layer in the oxide film etching desirably has a selectivity ratio of 10 or more with respect to the oxide film etch rate. In addition to SiN, TaO, niobium oxide (abbreviated as NbO), or the like can be used. When TaO or NbO is used, the film thickness is preferably 10 nm or more. Further, it is possible to use titanium oxide (abbreviated as TiO), alumina or the like.
[0030]
A thick silicon oxide layer 34 is formed on the upper SiN layer 33. The silicon oxide layer 34 is a member that provides a mold for forming the lower electrode of the capacitor together with the insulating layers 31, 32, and 33 serving as a pedestal, and is a sacrificial film that is removed later. For example, it has a thickness tailored to a capacitor of about 800 nm.
[0031]
A resist layer is applied on the silicon oxide layer 34, and exposed and developed to form a resist pattern PR1. The resist pattern PR1 has an opening in a region where a capacitor is formed. The diameter of the opening is about 130 nm, for example.
[0032]
Using the resist pattern PR1 as an etching mask, the silicon oxide layer 34 is anisotropically etched by reactive ion etching (RIE). This etching stops at the upper SiN layer 33. After the SiN layer 33 is etched by switching the etching conditions, the lower SiO layer 32 is etched by silicon oxide etching. This etching of silicon oxide stops at the surface of the lower SiN layer 31.
[0033]
In the etching of silicon oxide, the SiN layer has an etch rate of about 1/10 or less, and even if the SiO layer 32 is completely etched, a sufficient amount of the SiN layer 31 remains. Here, the etching conditions are changed again, the SiN layer 31 is etched, and the surface of the plug 17 is exposed.
[0034]
The resist pattern PR1 is preferably removed by ashing during the period after the etching of the silicon oxide layer 34 is completed and before the etching of the SiN layer 31 is performed. By covering the surface of the plug 17 with the SiN layer 31 during ashing, the oxidation of the plug can be prevented.
[0035]
As shown in FIG. 2B, a TiN layer having a thickness of, for example, 5 nm to 20 nm is formed by CVD in the capacitor opening SN thus formed as an adhesion layer. The CVD of the TiN layer is performed at a film forming temperature of 530 ° C. or higher using, for example, TiCl ₄ and NH ₃ as source gases. By setting the film forming temperature to 530 ° C. or higher, the chlorine concentration remaining in the film can be set to 3 atm% or lower.
[0036]
The adhesion layer is a layer for firmly supporting the lower electrode formed of a rare metal or the like for the pedestal lamination and sacrificial film formation, and a metal such as Ti or Ta, or a metal nitride such as WN, TiN, or TaN is used. it can.
[0037]
On the TiN layer 35, a rare metal layer to be a lower electrode is formed by CVD. For example, a Ru layer 36 having a thickness of about 30 nm is formed using diethylcyclopentalthenium Ru (EtCp) ₂ as a source gas and oxygen as a catalyst. Note that dicyclopentalthenium Ru (Cp) ₂ may be used as a source gas instead of Ru (EtCp) ₂ . Each source gas may be supplied after being dissolved in a solvent such as THF. By setting the film formation temperature to 350 ° C. or lower, reaction-controlled CVD is performed, and film formation with good coverage is performed.
[0038]
Rare metals are not only difficult to oxidize, but also retain electrical conductivity when oxidized. Therefore, the electrode performance is maintained even when annealing is performed in an oxidizing atmosphere. A rare metal oxide may be used instead of the rare metal. This is because the TiN layer 35 is inserted between the Ru layer 36 and the pedestal stack of insulators. The adhesion of the Ru layer 36 to the pedestal is improved.
[0039]
After the Ru layer 36 is formed, a dielectric film 37p having resistance to etching is formed thereon as a protective layer. For example, an amorphous TaO film 37p having a thickness of about 10 nm or less is formed by CVD using Ta (O (C ₂ H ₅ )) ₅ and O 2. The amorphous TaO film has an extremely slow etching rate in etching silicon oxide and TiN, and pinholes are hardly formed. The TaO film 37p covers the inner surface of the cylindrical Ru layer 36 and serves as a protective film that prevents the etchant from entering during wet etching.
[0040]
The TaO film 37p, the Ru layer 36, and the TiN layer 35 deposited on the surface of the silicon oxide layer 34 are removed. In the CMP for this removal, the opening SN is filled with the filling SF in order to prevent dust during processing from remaining in the opening SN and causing damage. As the filling SF, a resist, spin-on-glass (SOG), or the like can be used. When these are applied, a filling layer SF is also formed on the surface of the silicon oxide layer.
[0041]
In this way, after filling the opening with the filling, CMP is performed to remove the filling SF, the TaO film 37p, the Ru layer 36, and the TiN layer 35 on the surface of the silicon oxide layer 34.
[0042]
FIG. 3A shows the structure of the substrate after CMP. The TiN layer 35, the Ru layer 36, the TaO film 37p, and the filling SF are left in the opening SN. The Ru layer 36 serving as the lower electrode has a cup-shaped cylinder shape having a bottom surface and a closed loop-shaped side surface. The inner surface of the Ru layer 36 is covered with a TaO film 37p.
[0043]
As shown in FIG. 3B, the filling SF in the silicon oxide layer 34 and the opening SN is removed. When the filling SF is SOG, the silicon oxide layer 34 and the filling can be simultaneously removed by wet etching. When the filling SF is a resist, after removing the silicon oxide layer 34, the resist remaining in the opening SN is removed by a resist remover, ashing, or the like.
[0044]
The etching of the silicon oxide layer 34 is performed by wet etching with dilute hydrofluoric acid and stopped by the SiN layer 33. By leaving the SiN layer 31, the SiO layer 32, and the SiN layer 33, the lower electrode 36 is supported by a pedestal made up of these three layers under the lower electrode 36, and collapse or the like is prevented.
[0045]
In the above-described embodiment, a TiN layer as an adhesion layer is used between the rare metal layer of the lower electrode and the insulating layer serving as a base. The adhesion layer is not always essential. The cylindrical lower electrode may be formed by omitting the adhesion layer.
[0046]
FIG. 4 shows a configuration in which the adhesion layer is omitted. A rare metal lower electrode 36 is formed by being supported by the SiN layer 31, the silicon oxide layer 32, and the SiN layer 33 that serve as a pedestal. A protective layer 37p such as TaO is formed on the inner surface of the rare metal layer. Also in this configuration, the inner surface of the cylinder-type rare metal layer 36 is covered with the protective layer 37p.
[0047]
For example, as shown in FIG. 4, it is assumed that a displacement occurs, and the position of the cylinder-type lower electrode 36 is displaced from the lower W plug 17. When the TaO film 37p does not exist, when the HF solution oozes out through the thin Ru layer 36, the silicon oxide layer 16 disposed thereunder is etched. Since the TaO film 37p covers the inner surface of the lower electrode 36, the leaching of the solution from the inner surface of the lower electrode to the outside is prevented.
[0048]
As shown in FIG. 5A, the TiN layer 35 formed on the outer surface of the cylinder-type lower electrode 36 is removed. The TiN layer 35 is removed by wet etching using any one of a mixed solution of sulfuric acid and hydrogen peroxide, a mixed solution of hydrochloric acid and hydrogen peroxide, and a mixed solution of hydrogen peroxide and ammonia. If the filling SF is a resist, it will be removed during the wet etching process even if it is not removed in advance. By wet etching, the TiN layer is etched to a position recessed from the surface of the etch stopper film 33. Further below, the TiN layer 35r remains to ensure the support of the pedestal and the cylinder-type lower electrode.
[0049]
Also in this wet etching of the TiN layer, since the protective layer 37p is formed on the inner surface of the lower electrode 36, the defect of the lower electrode 36 and the seepage of the etchant through the pinhole are prevented. In the case where the protective layer 37p is not provided, the W plug 17 is dissolved when the chemical solution oozes out of the lower electrode 36 through a defect of the lower electrode 36 or a pinhole.
[0050]
As shown in FIG. 5B, a TaO capacitor dielectric film 37 f is formed on the surface of the lower electrode 36. The dielectric film 37f covers the exposed surfaces of the lower electrode 36 and the protective film 37p. The thickness of the dielectric film 37f is, for example, about 15 nm. For example, the substrate is heated to a reaction-controlled CVD temperature, and the dielectric film 37f is formed with good coverage by low pressure chemical vapor deposition (LP-CVD) using Ta (O (C ₂ H ₅ )) ₅ and O ₂ . The temperature range in which the reaction is controlled is a temperature lower than 550 ° C., for example.
[0051]
FIG. 6A shows an enlarged dielectric layer on the surface of the Ru layer 36. The Ru layer 36 is formed by CVD and may have irregularities on the growth surface. In the case of having irregularities, electric field concentration occurs in the protruding portion, and dielectric breakdown is likely to occur. On the inner surface of the cylinder-type lower electrode 36, a TaO film 37p used as a protective film and a TaO film 37f formed as a capacitor dielectric film are laminated, and the thickness of the dielectric film 37 as a whole increases. Therefore, even if irregularities are formed on the inner surface of the Ru layer 37, the TaO film 37 thicker than that on the outer surface is formed, so that dielectric breakdown of the dielectric film 37 is efficiently prevented.
[0052]
Returning to FIG. 5B, the TiN adhesion layer 35r is etched to a position recessed from the surface of the etch stopper layer. The reaction-limited TaO film enters the recess and grows to form a TaO film 37x. The TaO film 37x contacts the TiN layer 35 in the recess.
[0053]
The TiN layer 35r has a property of depriving oxygen from the TaO film 37x. Accordingly, the dielectric characteristics of the TaO film 37x in contact with the TiN layer 35r are deteriorated to become an insulating film through which a leak current flows. However, since the TaO film 37x in this region is buried between the lower electrode 36 and the pedestal stack formed of the insulating film, sufficiently thick TaO comes into contact with TiN, which adversely affects the electrical characteristics of the capacitor. Does not reach.
[0054]
As the capacitor dielectric film, in addition to the TaO film, an NbO film, a TiO film, a WO film, an alumina film, an STO film, a BST film, a PZT film, or a combination thereof can also be used.
[0055]
Note that the protective film 37p on the inner surface of the cylinder-type lower electrode 36 may be removed by dry etching using an etchant gas containing CF ₄ before the dielectric film 37f is formed.
[0056]
FIG. 6B shows a state in which the dielectric film 37f is formed after the protective film 37p on the inner surface of the lower electrode 36 is removed. A TaO film 37 f having a substantially uniform thickness is formed on the inner surface and the outer surface of the Ru layer 36. When the growth surface of the Ru layer 36 is smooth, the capacitance can be increased by setting the capacitor dielectric film to a minimum film thickness. The TiN layer 35r is recessed in the pedestal stack, and the TaO film 37x is formed in this recess as in FIG. 5B.
[0057]
As shown in FIG. 7A, after the dielectric film 37f is formed, a Ru layer 38 as an upper electrode is formed. The upper electrode of the capacitor is an electrode that becomes a plate electrode. For example, the Ru layer 38 is formed by CVD using Ru (EtCp) ₂ and O ₂ . The plate electrode may be formed of a rare metal oxide such as RuO, a metal nitride such as TiN or WN, or a metal oxynitride such as TiON or WON in addition to the rare metal.
[0058]
After the Ru upper electrode is formed, the TiN layer is physically deposited. A TiN layer 39 is formed from above by physical deposition. Next, the TaO layer 41 is formed by the same CVD as described above.
[0059]
As shown in FIG. 7B, the TaO layer 41, the TiN layer 39, and the upper electrode layer 38 are patterned. In this patterning, a resist pattern is formed on the TaO layer 41, and the TaO layer 41 is patterned by dry etching based on CF ₄ using this resist pattern as an etching mask. TaO can be etched and can serve as a mask. The resist mask is removed at this stage.
[0060]
Then a TaO layer 41 as a mask, the TiN layer 39 underlying the dry etching using Cl2 and He, patterning the upper electrode 38 by dry etching using Cl ₂ and O _2. In the etching of the TiN layer 39 and the Ru layer 38, since no resist mask exists, the generation of products due to the reaction between evaporated Ru and the resist can be greatly reduced. Thereafter, an interlayer insulating film 42 such as silicon oxide or BPSG is formed to complete the semiconductor device.
[0061]
The intermediate TiN layer 39 can be omitted. The TaO layer 41 may be formed directly on the Ru layer 38. Also in this case, the etching product can be greatly reduced by removing the resist mask immediately after the etching of the TaO layer 41 is completed. In the case where the TiN layer is used, the TiN layer can function as an adhesive layer between the Ru layer and the insulating layer formed thereon as well as serving as a shielding film covering the Ru layer 38. The function as the adhesive layer can also be obtained by a material other than the TiN layer as described above.
[0062]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0063]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent unintended etching from occurring under the capacitor even when wet etching is performed during the manufacturing process.
[0064]
A capacitor capable of efficiently preventing dielectric breakdown is provided by forming a capacitor dielectric film thicker than the outer surface on the inner surface of the cylinder type capacitor lower electrode.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor substrate showing main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor substrate showing the main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor substrate showing the main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to a modification of the embodiment of the present invention.
FIG. 5 is a cross-sectional view of a semiconductor substrate showing the main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor device according to a modification of the embodiment of the present invention.
FIG. 7 is a cross-sectional view of a semiconductor substrate showing the main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
[Explanation of symbols]
11 Semiconductor substrate 12 Shallow trench isolation 13 Insulated gate electrode S / D Source / drain region 15 Lower polycrystalline silicon plug 17 W plug 14, 16 Interlayer insulating film 27 (W / TiN / Ti) bit line 28 SiN layer 29 SiN side Wall etch stoppers 31, 33 SiN layer 32 SiO layer 34 Silicon oxide layer SN Opening 36 Lower electrode 37 Dielectric film 37p Protective dielectric film 37f Capacitor dielectric film 38 Upper electrode 39 TiN layer 41 TaO film 42 Interlayer insulating film

Claims (4)

(A) forming a metal or metal compound plug in the first insulating layer disposed on the semiconductor substrate;
(A) forming a second insulating layer on the first insulating layer;
(C) forming an opening through the second insulating layer to expose the plug surface on the bottom surface;
(D) A metal or metal nitride adhesion layer is formed in a cylindrical shape on the inner surface of the opening, and further a rare metal electrode layer of any one of Ru, Ir, and Pt and a protective dielectric covering the inner surface of the electrode layer Forming a film, wherein the protective dielectric film is formed of a material having etching characteristics different from those of the first and second insulating layers and the metal or metal compound;
(E) removing the second insulating layer outside the cylinder by etching with the inner surface of the cylindrical electrode layer covered with the protective dielectric film ;
(F) After the step (e), with the inner surface of the cylindrical electrode layer covered with the protective dielectric film, the exposed adhesion layer is removed by wet etching;
Unrealized, the in the wet etching, the etching rate of the protective dielectric film manufacturing method of a semiconductor device, wherein the lower than the etching rate of the adhesion layer. Further, ( g ) A pedestal stack including a first etch stopper layer, an intermediate layer, and a second etch stopper layer is formed on the first insulating layer between the steps (a) and (b). Including steps,
In the step (c), the opening is formed by etching the second insulating layer and the pedestal stack,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (e), the second insulating layer outside the cylinder is wet-etched using the second etch stopper layer as an etch stopper. The protective dielectric film, a method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that an amorphous TaO film. The adhesion layer, Ti, Ta, WN, the method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that either TiN or TaN,.

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