JP2006121009A - Semiconductor storage device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor storage device, with which the semiconductor storage device is formed more easily, wherein electric charges as information are not easily slip, and to provide the semiconductor storage device which has electric charge holding performance. <P>SOLUTION: A polysilicon film is partially removed, leaving a portion disposed in a region sandwiched between adjacent side-wall insulating films etc. Then the side-wall insulating films and a silicon oxide film are subjected to dry etching by using fluorocarbon-based gas. At this time, sputtering effect is enhanced and then projecting portions are reduced gradually on both the sides of a hollow of the polysilicon film. The projecting portions of the polysilicon film on both the sides of the hollow are completely removed, in a state wherein the side-wall insulating films etc., are removed, and the upper end portion of the polysilicon film 9b that serves as a floating gate electrode is formed into a gentle projecting shape. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device including a predetermined electrode for accumulating charges as information and a manufacturing method thereof.

  As the semiconductor memory device, a nonvolatile semiconductor memory device represented by a flash memory and a volatile semiconductor memory device represented by a dynamic random access memory (hereinafter referred to as “DRAM”) are known. Yes. In a nonvolatile semiconductor memory device, memory cell transistors each having a floating gate electrode and a control gate electrode are arranged in a matrix as memory cell transistors constituting a memory cell. The charge as information is stored in the floating gate electrode. On the other hand, in a volatile semiconductor memory device, capacitors having a dielectric film interposed between a storage node and a cell plate are arranged in a matrix with switching transistors. The charge as information is stored in the storage node of the capacitor.

  A polysilicon film is generally used as a material for the floating gate electrode or storage node in which such charge as information is stored, and the polysilicon film is processed into a predetermined shape. At this time, if the end of the formed floating gate electrode or storage node is angular, charges tend to concentrate on the corner. When charges are concentrated at the corners of the floating gate electrode, the charges are likely to escape from the corners toward the insulating film interposed between the floating gate electrode and the control gate electrode. In addition, when charges are concentrated at the corners of the storage nodes, the charges are likely to escape from the corners of the storage nodes toward the dielectric film. As described above, there is a problem that the reliability as the semiconductor memory device is impaired when the charge as information is released from the floating gate electrode or from the storage node.

  In order to solve such a problem, for example, Patent Document 1 proposes a method of rounding the corners of the floating gate electrode. That is, first, after the floating gate electrode and the control gate electrode are formed, the semiconductor substrate is immersed in an acid such as hydrochloric acid, so that a natural oxide film is formed on the side wall portion of the floating gate electrode and the side wall portion and the upper surface portion of the control gate electrode, respectively. Is formed. Next, by performing an annealing process in an ammonia atmosphere, the natural oxide film formed on the sidewall of the floating gate electrode or the like is changed to a silicon oxynitride film. In this way, a silicon oxynitride film is selectively formed on the side wall portion of the floating gate electrode, etc., and on the side wall portion of the insulating film (tunnel oxide film) located between the floating gate electrode and the control gate electrode. A silicon oxynitride film is not formed.

In this state, annealing is performed under an oxidizing atmosphere, so that the floating gate electrode end portion and the control gate electrode end portion that are in contact with the insulating film not covered with the silicon oxynitride film are respectively used. By gradually growing the oxide film, each corner of the floating gate electrode and the control gate electrode is rounded. Also in Patent Document 2, a method is proposed in which the corners of the floating gate electrode are rounded by performing thermal oxidation after patterning the conductive film to be the floating gate electrode.
Japanese Patent Laid-Open No. 11-154711 JP-A-10-125812

  However, the conventional method for manufacturing a semiconductor memory device has the following problems. As described above, in order to round the corners of the floating gate electrode or the like, the oxidation process, the nitridation process, and the oxidation process must be sequentially performed, and additional processes are added and each process is managed to obtain a desired shape. There was a problem that became complicated.

  In recent years, an AG (assist gate) -AND type flash memory has been proposed in which a semiconductor memory device is miniaturized. A conventional oxidation process is used to round the corner of the floating gate of the AG-AND type flash memory. However, there is a problem that it cannot be easily rounded due to the structure caused by the manufacturing process. This will be described. In the AG-AND flash memory, the bit line of the memory cell transistor is not a diffusion layer but an inversion layer formed on the semiconductor substrate when a predetermined voltage is applied to the assist gate electrode. A plurality of assist gate electrodes are formed at a predetermined interval, and the floating gate electrode is located in a region sandwiched between adjacent assist gate electrodes.

  The floating gate electrode is formed by etching the entire surface of the polysilicon film filling the region sandwiched between the silicon oxide films covering each of the assist gate electrodes. At this time, the surface shape of the formed polysilicon film may be reflected to cause a depression near the center of the upper surface portion of the polysilicon film remaining as the floating gate electrode. After that, if the polysilicon film is oxidized to remove the silicon oxide film covering the assist gate electrode and round the corners of the exposed polysilicon film, the entire surface of the exposed polysilicon film is oxidized, resulting in depressions. There is a problem in that the upper surface portion of the polysilicon film having a thickness cannot be rounded well. In addition, if an attempt is made to partially promote the oxidation of the upper surface portion of the polysilicon film and a part of the oxide film formed on the surface of the polysilicon film is to be removed, there is a problem that the manufacturing process becomes complicated. .

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor memory device that more easily forms a semiconductor memory device in which charge as information is not easily lost. Another object is to provide a semiconductor memory device having high charge retention characteristics manufactured by such a manufacturing method.

  The semiconductor memory device according to the present invention is a semiconductor memory device in which memory cells are arranged in a matrix. The memory cell includes a plurality of assist gate electrodes, a columnar floating gate electrode, an insulating film, and a control gate electrode. The plurality of assist gate electrodes are formed on the main surface of the semiconductor substrate with a first gate insulating film interposed therebetween and spaced apart from each other. The columnar floating gate electrode is formed on a region of the semiconductor substrate sandwiched between adjacent assist gate electrodes with a second gate insulating film interposed therebetween, and has opposite side surfaces and an upper surface. The insulating film is formed so as to cover the floating gate electrode. The control gate electrode is formed on the floating gate electrode with an insulating film interposed. The corners are rounded at the upper end of the floating gate electrode.

  A method for manufacturing a semiconductor memory device according to the present invention is a method for manufacturing a semiconductor memory device in which memory cells are arranged in a matrix, and includes the following steps. A plurality of assist gate electrodes are formed on the main surface of the semiconductor substrate at intervals. A columnar second conductive layer serving as a floating gate electrode is formed in a region of the semiconductor substrate sandwiched between adjacent assist gate electrodes. A first insulating film is formed so as to cover the columnar second conductive layer. A third conductive layer to be a control gate electrode is formed on the first insulating film. By subjecting the third conductive layer and the second conductive layer to predetermined processing, a control gate electrode and a floating gate electrode are formed, respectively. In the step of forming the columnar second conductive layer, the upper end portion of the columnar second conductive layer is rounded by etching.

  Another method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a semiconductor memory device including a memory cell including a first electrode for accumulating charge as information, and includes the following steps. . A first conductive layer to be a first electrode is formed on the main surface of the semiconductor substrate. A first electrode is formed by processing the first conductive layer. An insulating film is formed on the first electrode. A second electrode is formed on the first electrode with an insulating film interposed. The step of forming the first electrode includes a patterning step of forming the first conductive layer in a predetermined shape, and a step of rounding the corners by etching the portion of the first conductive layer patterned in the predetermined shape. ing.

  According to the semiconductor memory device of the present invention, the corners are rounded at the upper end of the floating gate electrode of the memory cell having the assist gate electrode, so that it is accumulated in the floating gate electrode as compared with the conventional semiconductor memory device. It is possible to suppress the portion where the charge as information is concentrated and the charge from being released into the insulating film. As a result, the charge retention characteristics can be improved and the reliability of the semiconductor memory device can be improved.

  Further, according to the method of manufacturing a semiconductor memory device according to the present invention, in the step of forming the columnar second conductive layer serving as the floating gate electrode, the upper end portion of the columnar second conductive layer is rounded by performing etching. Thus, the corners of the floating gate electrode can be easily rounded as compared with the conventional manufacturing method.

  Furthermore, according to another method of manufacturing a semiconductor memory device according to the present invention, in the step of forming the first electrode, the corners are rounded by etching the portion of the first conductive layer patterned into a predetermined shape. Thus, as compared with the conventional manufacturing method, the corners of the first electrode where charges are accumulated can be easily rounded.

Embodiment 1
An AG-AND type flash memory will be described as the semiconductor memory device according to the first embodiment of the present invention. In the AG-AND type flash memory, as shown in FIG. 1 (cross-sectional view corresponding to cross-sectional line II in FIG. 13), a plurality of assist gate electrodes 3 are spaced apart from each other on the main surface of the semiconductor substrate 1. It is formed apart. Each assist gate electrode 3 is formed on the semiconductor substrate 1 so as to extend in one direction (perpendicular to the paper surface) with the gate insulating film 2 interposed therebetween. A silicon nitride film 4 is formed on the upper surface of the assist gate electrode 3.

  A floating gate electrode 9 c is formed in each region of the semiconductor substrate 1 sandwiched between adjacent assist gate electrodes 3. An ONO (Oxide-Nitride-Oxide) film 11 is formed so as to cover the floating gate electrode 9c. A control gate electrode 14 is formed on the ONO film 11 in a direction orthogonal to one direction (parallel to the paper surface). The control gate electrode 14 is composed of the polysilicon film 12 and the tungsten silicide film 13. One memory cell transistor is formed by the floating gate electrode 9c and the control gate electrode 14 located immediately above the floating gate electrode 9c. A silicon oxide film 15 is formed so as to cover the control gate electrode 14.

  By applying a predetermined voltage to the assist gate electrode 3, an inversion layer is formed in the region of the semiconductor substrate 1 located immediately below the assist gate electrode 3. This inversion layer functions as a bit line including the source and drain of the memory cell transistor. On the other hand, the inversion layer is not formed in the region of the semiconductor substrate 1 by not applying a voltage to the assist gate electrode 3 or by applying a predetermined negative voltage. It will be electrically separated.

  Next, an information write operation, a read operation, and an erase operation will be described. First, in the information write operation, as shown in FIG. 2, for example, a voltage of about 15 V is applied to the word line (in this case, WL128) to which the selected memory cell transistor is connected, and the other word lines are For example, a voltage of about −2V is applied. In addition, a voltage of about 5 V, for example, is applied to the assist gate electrode 3 (AG0) for forming the source in the selected memory cell transistor, and a voltage of, for example, about 8 V is applied to the assist gate electrode 3 (AG2) for forming the drain. The As a result, an inversion layer serving as a source / drain is formed on the surface of the semiconductor substrate 1 located immediately below these assist gate electrodes 3.

  On the other hand, a voltage of about −2 V, for example, is applied to the assist gate electrode 3 (AG3) other than those described above, and an inversion layer is formed on the surface of the semiconductor substrate 1 located immediately below these assist gate electrodes 3. Instead, electrical isolation is performed between the selected memory cell transistor and the non-selected memory cell transistor. Further, a voltage of about 1 V, for example, is applied to the assist gate electrode 3 (AG1). Further, a voltage of about 4.5 V, for example, is applied to the bit lines (GBL1, GBL3) connected to the inversion layer serving as the drain in the selected memory cell transistor. For example, a voltage of about 0 V is applied to the bit line (GBL2) connected to the inversion layer serving as the source in the selected memory cell transistor, while the inversion layer serving as the source in the non-selected memory cell. A voltage of about 2 V, for example, is applied to the bit line (GBL0) connected to, in order to prevent writing.

  Thereby, in the selected memory cell transistor, a write current flows from the drain to the source, and the charge accumulated in the inversion layer on the source side is injected into the floating gate electrode through the gate insulating film. On the other hand, in a non-selected memory cell transistor, no current flows from the drain to the source (marked by x), and no charge is injected into the floating gate electrode. By the operation as described above, information is selectively written into a predetermined memory cell transistor.

  Next, in the information reading operation, an operation opposite to the above-described writing operation is performed. As shown in FIG. 3, a voltage of about 2 to 5 V, for example, is applied to the word line (in this case, WL128) to which the selected memory cell transistor is connected, and a voltage of about −2 V, for example, is applied to the other word lines. Is applied. Further, for example, a voltage of about 4V is applied to the assist gate electrode 3 (AG2, AG1) for forming the source / drain in the selected memory cell transistor. Thereby, the source / drain in the selected memory cell transistor is formed. On the other hand, a voltage of about −2 V, for example, is applied to the assist gate electrode 3 (AG3) for source / drain formation in the unselected memory cell transistor. Thereby, in the non-selected memory cell transistor, the inversion layer serving as the source / drain is not formed. As a result, electrical separation between the selected memory cell transistor and the non-selected memory cell transistor is realized.

  In addition, for example, a voltage of about 1.2 V is applied to the bit lines (GBL1, GBL3) to which the inversion layer serving as the drain in the selected memory cell transistor is connected, while the other bit lines (GBL0, GBL2) For example, a voltage of about 0V is applied. Furthermore, a voltage of about 0 V, for example, is applied to the bit line connected to the inversion layer serving as the source in the selected memory cell transistor. Here, the threshold voltage of the selected memory cell transistor changes depending on the state of the charge stored in the floating gate electrode. Therefore, the data of the memory cell transistor can be determined from the state of the current flowing between the source and drain of the selected memory cell. With the above operation, information is read from a predetermined memory cell transistor.

  Next, in the information erasing operation, a negative voltage (for example, about −16 V) is applied to the word line to be selected, while a positive voltage is applied to the semiconductor substrate 1. Note that a voltage of about 0 V is applied to the assist gate electrode 3, and no inversion layer is formed. As a result, charges are released from the floating gate electrode toward the semiconductor substrate 1 by FN (Fowlor Nordheim) tunnel emission. By the operation as described above, information in a plurality of memory cells is erased at once.

  In the above-described AG-AND type flash memory, corners are rounded at the upper end portion in contact with the ONO film 11 in the floating gate electrode 9c in which charges as information are stored, and the upper surface of the floating gate electrode 9c is formed on both opposing side surfaces. It is formed in a gentle convex shape from one side surface to the other side surface. Moreover, the upper surface and both side surfaces are smoothly connected. As a result, as will be described later, as compared with the conventional AG-AND type flash memory, there is no portion where the charge as information stored in the floating gate electrode 9c is concentrated, and the charge is prevented from flowing out to the ONO film 11. can do. As a result, the charge retention characteristics can be improved and the reliability of the semiconductor memory device can be improved.

Embodiment 2
Next, a manufacturing method of the above-described AG-AND type flash memory will be described. Here, the manufacturing process of the memory cell region will be described, and the description of the peripheral circuit region will be omitted. First, as shown in FIG. 4, the gate insulating film 2 is formed on the main surface of the semiconductor substrate 1. A polysilicon film (not shown) serving as an assist gate electrode is formed on the gate insulating film 2. A silicon nitride film (not shown) is formed on the polysilicon film. A silicon oxide film (not shown) using TEOS (Tetra Ethyl Ortho Silicate) as a material is formed on the silicon nitride film. A plurality of assist gate electrodes 3 are formed at predetermined intervals by applying predetermined photolithography and processing on the silicon oxide film. A silicon nitride film 4 and a silicon oxide film 5 are left above each assist gate electrode 3.

  Next, as shown in FIG. 5, a thermal oxide film 6 is formed on the side surface of the assist gate electrode 3 by performing a thermal oxidation process. Next, a silicon oxide film (not shown) having a predetermined thickness is further formed on the semiconductor substrate 1 so as to cover the silicon oxide film 5 and the like. By performing anisotropic etching on the silicon oxide film, sidewall insulating films 7 are formed on the side surfaces of the assist gate electrode 3, the side surfaces of the silicon nitride film 4, and the side surfaces of the silicon oxide film 5, as shown in FIG. The Next, as shown in FIG. 7, a thermal oxide film 8 is formed on the surface of the semiconductor substrate 1 exposed by performing a thermal oxidation process. Next, as shown in FIG. 8, a polysilicon film 9 having a predetermined thickness is formed so as to fill a region of the semiconductor substrate 1 sandwiched between adjacent sidewall insulating films 7 and the like. Thereafter, a resist pattern (not shown) is formed so as to cover a predetermined portion other than the memory cell region.

  Next, as shown in FIG. 9, by etching the polysilicon film 9 exposed in the memory cell region, a portion of the polysilicon film 9 located in a region sandwiched between adjacent sidewall insulating films 7 ( The portions of the other polysilicon film 9 are removed leaving the polysilicon film 9a). At this time, the surface shape of the initially formed polysilicon film 9 is reflected, and a recess 10 is generated in a portion located near the center between the adjacent sidewall insulating films 7 on the upper surface of the remaining polysilicon film 9a. ing. Next, dry etching is performed on the sidewall insulating film 7 and the silicon oxide film 5 using a fluorocarbon-based gas. At this time, by increasing the power of the electrode located on the side on which the semiconductor substrate 1 is placed in an etching apparatus (not shown) to enhance the sputtering effect, a recess in the polysilicon film 9a is obtained as shown in FIG. The protruding portions on both sides of 10 are gradually scraped. That is, sputter etching is performed when the sidewall insulating film 7 and the like are removed.

  As shown in FIG. 11, when the sidewall insulating film 7 and the silicon oxide film 5 located above the silicon nitride film 4 are finally removed, portions of the protruding polysilicon film 9a on both sides of the recess 10 are formed. Is completely scraped off. Thereby, the corners are rounded at the upper end portion of the polysilicon film 9b to be the floating gate electrode 9c, and the upper surface of the floating gate electrode 9c is formed in a gentle convex shape as will be described later.

  Next, as shown in FIG. 12, the ONO film 11 is formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film. A polysilicon film 12 and a tungsten silicide film 13 to be a control gate electrode are formed on the ONO film 11. A silicon oxide film 15 is formed on the tungsten silicide film 13. A mask for forming a control gate electrode is formed by subjecting the silicon oxide film 15 to predetermined photoengraving and processing, and by performing predetermined etching using this as a mask, as shown in FIGS. The tungsten silicide film 13 and the polysilicon film 12 (polysilicon film 12a) and the tungsten silicide film 13 located between the adjacent control gate electrodes are formed, leaving a portion of the tungsten silicide film 13 (tungsten silicide film 13a) and a portion of the polysilicon film 12 (polysilicon film 12a). The portion of the polysilicon film 12 is removed, and the ONO film 11 is exposed.

  Next, as shown in FIG. 15, the exposed ONO film 11 is anisotropically etched to expose the polysilicon film 9b. Next, as shown in FIG. 16, by performing anisotropic etching on the exposed polysilicon film 9b, the portion of the polysilicon film 9b located between the adjacent control gate electrodes 14 is removed. As a result, the portion of the polysilicon film 9b left immediately below the control gate electrode 14 becomes the floating gate electrode 9c (see FIG. 1). In this way, the main part of the memory cell region is formed.

  Next, the effects of the semiconductor memory device manufacturing method described above will be described in comparison with a conventional manufacturing method. In the conventional manufacturing method as a comparative example, the semiconductor memory device (memory cell region) is formed as follows. First, after the step shown in FIG. 9, when the sidewall insulating film 7 and the silicon oxide film 5 are removed, substantially only the sidewall insulating film 7 and the silicon oxide film 5 are left with the polysilicon film 9a left. Removed. Accordingly, there are still protruding portions on both sides of the recess in the polysilicon film. Next, as shown in FIG. 17, an ONO film 111 is formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film on the exposed surface of the polysilicon film 109a. At this time, the thickness of the ONO film 111 in the portion located in the depression of the polysilicon film 109a is thicker than the thickness of the other portions.

  Next, as shown in FIG. 18, a polysilicon film 112, a tungsten silicide film 113, and a silicon oxide film 114 are formed on the ONO film 111, respectively. Thereafter, when the control gate electrode is formed, the tungsten silicide film 113 and the polysilicon film 112 located between the adjacent control gate electrodes are removed, and the ONO film 111 is formed as shown in FIG. Exposed.

  Next, as shown in FIG. 20, the exposed ONO film 111 is anisotropically etched to expose the polysilicon film 109b. At this time, the ONO film 111b may remain as a residue because the thickness of the ONO film 111 in the portion located in the depression 110 of the polysilicon film 109a is thicker than the thickness of the other portions. When anisotropic etching is performed on the portion of the polysilicon film 109a located between the adjacent control gate electrodes with such an ONO film 111b left, as shown in FIG. 21, the remaining ONO film is left. Using the film 111b as a mask, the portion of the polysilicon film 109a located immediately below it remains without being etched.

  For this reason, the floating gate electrodes of adjacent memory transistors are electrically short-circuited by the remaining portion of the polysilicon film 109a, and the desired function as a semiconductor memory device may not be achieved. In addition, due to the depression generated on the upper surface of the polysilicon film of the floating gate electrode, the charge concentrates on the portion of the polysilicon film protruding on both sides of the depression, and the information charge is released from the portion to the ONO film, The reliability as a semiconductor memory device may be impaired.

  On the other hand, in the method for manufacturing the semiconductor memory device according to the present invention described above, the sputtering effect is obtained when the sidewall insulating film 7 and the silicon oxide film 5 covering the assist gate electrode 3 are removed by etching (sputter etching). The raised portions of the exposed polysilicon film 9a on both sides of the recess 10 can be gradually scraped off. As a result, the polysilicon film 9b to be the floating gate electrode is finally formed in a gentle convex shape. As a result, there is no portion where the charge accumulated in the floating gate electrode 9b is concentrated, and it is possible to prevent the charge from escaping to the ONO film 11. As a result, the charge retention characteristics can be improved and the reliability of the semiconductor memory device can be improved.

  Further, since the polysilicon film 9b is formed in a gentle convex shape, an ONO film 11 having a uniform thickness is formed on the polysilicon film 9b and is located between adjacent control gate electrodes. When the exposed ONO film 11 is anisotropically etched to expose the polysilicon film 9b, a residue of the polysilicon film 9b is not generated. As a result, when the polysilicon film 9b is removed, there is no portion left unetched as in the conventional case, and the adjacent floating gate electrodes can be prevented from being electrically short-circuited. . As a result, a desired function as a semiconductor memory device can be ensured and reliability can be improved.

  In the above-described manufacturing method, when the sidewall insulating film or the like is removed by etching, the protruding effect of the polysilicon film 9a is gradually removed by increasing the sputtering effect, so that the rounded gently The case of forming a convex floating gate electrode has been described as an example, but in addition to this, the corner (upper end portion) of the polysilicon film that becomes the floating gate electrode can also be obtained by the method according to the following modification. Can be rounded.

Modification 1
First, after removing the sidewall insulating film 7 and the silicon oxide film 5 after the step shown in FIG. 9, the pressure is increased or the power applied to the substrate-side electrode is decreased as compared with the corresponding conditions described above. As shown in FIG. 22, the polysilicon film 9a having the depression 10 is formed by etching only the side wall insulating film 7 and the like without sputtering the polysilicon film 9a to be the floating gate electrode. Exposed. Next, by sputtering the exposed polysilicon film 9a using argon gas (Ar), the corners of the polysilicon film 9a can be easily rounded as shown in FIG.

Modification 2
As shown in FIG. 22, the semiconductor substrate 1 is immersed in hydrofluoric acid or acid-alkaline chemical solution after exposing the polysilicon film 9a having the recess 10 as shown in FIG. In addition, the corners of the polysilicon film 9a can be rounded relatively easily.

Embodiment 3
In the above-described embodiment, the AG-AND type flash memory has been described as an example of the semiconductor memory device. Here, as another form of flash memory, an AND type, NAND type and NOR type flash memory will be described as an example. First, as shown in FIG. 24, in the memory cell of the AND type flash memory, the control gate electrode of the memory cell transistor arranged in the row direction becomes the word line WL. A plurality of memory cell transistors T1, T2, etc. arranged in the column direction are connected in parallel, the drain of each memory cell transistor is connected to the sub-bit line, and the source is connected to the source line. The sub bit line is connected to the main bit line BL via a selection transistor, and the source line is connected to a common source line via a selection transistor.

  Next, as shown in FIG. 25, in the memory cell of the NAND flash memory, the control gate electrode of the memory cell transistor arranged in the row direction becomes the word line WL. A plurality of memory cell transistors arranged in the column direction are connected in series by connecting the sources and drains of memory cell transistors adjacent in the column direction. Of the series of memory cell transistors connected in series, the source of the memory cell transistor located on one end side is connected to the common source line via the selection transistor. On the other hand, the drain of the memory cell transistor located on the other end side of the series of memory cell transistors is connected to the bit line BL via the selection transistor.

  Next, as shown in FIG. 26, in the memory cell of the NOR type flash memory, the control gate electrode of the memory cell transistor arranged in the row direction becomes a word line. The drains of the memory cell transistors T1, T2, etc. arranged in the column direction are connected to the common bit line. The sources of the memory cell transistors arranged in the row direction are connected to a common source line.

  In these flash memories, information is written to a specific memory cell transistor by applying predetermined voltages to the source, drain, control gate electrode and semiconductor substrate of the memory cell transistor, and injecting electrons into the floating gate electrode. It is done by doing. The read operation is performed by applying a predetermined voltage to the source, drain, control gate electrode and semiconductor substrate of the memory cell transistor and determining the magnitude of the current flowing between the drain and source. The erasing operation is performed by applying predetermined voltages to the source, drain, control gate electrode and semiconductor substrate of the memory cell transistor to draw out the charge injected into the floating gate electrode.

  Also in the floating gate electrode that accumulates the charge as the information, the corners are rounded, so that it is possible to prevent the charge from escaping from the floating gate electrode to the ONO film. As a result, the charge retention characteristics can be improved and the reliability of the semiconductor memory device can be improved.

  Next, as a method for manufacturing such a flash memory, first, a method for manufacturing an AND type flash memory will be described. As shown in FIG. 27, a trench isolation region 21 for element isolation is formed in a predetermined region of the semiconductor substrate 1. Thereafter, a gate insulating film 20 is formed on the main surface of the semiconductor substrate 1. Next, as shown in FIG. 28, a polysilicon film 22 is formed on the semiconductor substrate 1. Next, as shown in FIG. 29, the polysilicon film 22 is subjected to predetermined photoengraving and processing, thereby exposing the surface of a predetermined region of the semiconductor substrate 1 and a part of the floating gate electrode (polysilicon film 22a). ) Is formed. Source / drain regions 27 a and 27 b are formed on the exposed surface of the semiconductor substrate 1.

  Next, as shown in FIG. 30, an insulating film 28 such as a silicon oxide film is formed so as to cover the exposed surface of the semiconductor substrate 1. Next, as shown in FIG. 31, a polysilicon film 23 is further formed so as to cover the polysilicon film 22a. Next, as shown in FIG. 32, the polysilicon film 23 is subjected to predetermined photoengraving and processing to form the remaining portion (polysilicon film 23a) to be a floating gate electrode. Next, by applying isotropic etching to the polysilicon film 23a without applying power using fluorine (F) gas, the corners of the polysilicon film 23a are rounded as shown in FIG.

  Next, an ONO film is formed so as to cover the polysilicon film 23a with rounded corners. A polysilicon film serving as a control gate electrode is formed on the semiconductor substrate 1 so as to cover the ONO film. Thereafter, by processing the polysilicon film, the ONO film and the polysilicon film, as shown in FIGS. 34 and 35, the floating gate electrode 24 composed of the polysilicon films 22a and 23a and the control composed of the polysilicon film are performed. A gate electrode 26 is formed. In this manner, a memory cell transistor having the source / drain 27a, 27b, the floating gate electrode 24 and the control gate electrode 26 in the AND type flash memory is formed.

  In the manufacturing method described above, the corners of the polysilicon film 23a are rounded by performing isotropic etching on the polysilicon film 23a serving as a floating gate electrode. As a result, after the etching of the polysilicon film 23a and the like, the corners of the polysilicon film 23a can be subsequently rounded without taking out the semiconductor substrate 1 from the etching apparatus, which is easier than the conventional manufacturing method in which the oxidation treatment is performed. The corners of the floating gate electrode 24 can be rounded.

  Next, the NAND type flash memory and the NOR type flash memory are basically the same in the process of the memory cell except that the wiring pattern connected to the memory cell is different. And a method for manufacturing a NOR type flash memory will be described together. First, as shown in FIG. 36, a trench isolation region 21 for element isolation is formed in a predetermined region of the semiconductor substrate 1. Thereafter, a gate insulating film 30 is formed on the main surface of the semiconductor substrate 1. Next, as shown in FIG. 37, a polysilicon film 31 is formed on the semiconductor substrate 1. Next, as shown in FIG. 38, the polysilicon film 31 is subjected to predetermined photolithography and processing to form a part of the floating gate electrode (polysilicon film 31a). Next, by applying isotropic etching to the polysilicon film 31a without applying power using fluorine (F) gas, the corners of the polysilicon film 31a are rounded as shown in FIG.

  Next, an ONO film is formed so as to cover the polysilicon film 31a with rounded corners. A polysilicon film serving as a control gate electrode is formed on the semiconductor substrate 1 so as to cover the ONO film. Thereafter, by processing the polysilicon film, the ONO film, and the polysilicon film, as shown in FIGS. 40 and 41, the floating gate electrode 32 made of the polysilicon film 31a and the control gate electrode made of the polysilicon film 34 is formed. Thereafter, NAND type or NOR type flash memories are respectively formed by forming predetermined wirings connected to the memory cells.

  Also in the manufacturing method described above, as in the case of the AND type flash memory, the corners of the polysilicon film 31a are rounded by performing isotropic etching on the polysilicon film 31a serving as the floating gate electrode. Thereby, after the etching of the polysilicon film 31a and the like, the corners of the polysilicon film 31a can be subsequently rounded without taking out the semiconductor substrate 1 from the etching apparatus, which is easy compared with the conventional manufacturing method in which the oxidation treatment is performed. The corners of the floating gate electrode 32 can be rounded.

  In the above-described method for manufacturing AND, NAND, and NOR flash memories, an example of isotropic etching using a fluorine-based gas to round the corners of the polysilicon film to be the floating gate electrode has been described. . In addition to this, the corners of the polysilicon film can be rounded by a method according to the following modification.

Modification 1
After patterning the polysilicon films 23a and 31a to be floating gate electrodes, the polysilicon films 23a and 31a are sputtered using argon gas (Ar) to easily round the corners of the polysilicon films 23a and 31a. Can do.

Modification 2
Further, after patterning the polysilicon films 23a and 31a to be the floating gate electrodes, a relatively thin polysilicon film is formed so as to cover the polysilicon films 23a and 31a, and etching (etch back) is performed on the polysilicon films 23a and 31a. The corners of the polysilicon films 23a and 31a can be rounded.

Modification 3
Alternatively, the corners of the polysilicon films 23a and 31a can be rounded relatively easily by immersing the semiconductor substrate in hydrofluoric acid or acid-alkali chemical solution after patterning the polysilicon films 23a and 31a to be the floating gate electrodes. .

  In each of the above-described embodiments, the flash memory which is a nonvolatile semiconductor memory device is described as an example of the semiconductor memory device. Semiconductor memory devices include volatile semiconductor memory devices typified by DRAM in addition to nonvolatile semiconductor memory devices. As shown in FIG. 42, the memory cell of the DRAM is composed of a capacitor C and a switching transistor T. The switching transistor T includes a gate electrode 41 and a pair of source / drain regions 41 a and 41 b, and is formed on the surface of a semiconductor substrate partitioned by an element isolation insulating film 40. An interlayer insulating film 43 is formed so as to cover the switching transistor T, and a capacitor C is formed on the interlayer insulating film 43.

  The capacitor C includes a storage node 45, a dielectric film 46, and a cell plate 47, and electric charge as information is stored in the storage node 45 of the capacitor C. The storage node 45 is electrically connected to one of the pair of source / drain regions 41a and 41b of the switching transistor via the storage node plug 44.

  Similar to the floating gate electrode of the flash memory, the storage node 45 is formed by subjecting a polysilicon film formed on the semiconductor substrate to predetermined photolithography and processing. Therefore, as described above, the corners of the storage node 45 are easily rounded by performing isotropic etching using fluorine (F) gas, sputtering using argon gas, etch back, or wet etching. Can do. As a result, it is possible to prevent the charge as accumulated information from flowing out from the storage node 45 to the dielectric film 46, and to improve the memory retention characteristic.

  The embodiment disclosed this time is merely an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a cross-sectional view of an AG-AND type flash memory as a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram for explaining a write operation of the AG-AND type flash memory shown in FIG. 1 in the embodiment. FIG. 2 is a circuit diagram for explaining a read operation of the AG-AND type flash memory shown in FIG. 1 in the embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the AG-AND type flash memory which concerns on Embodiment 2 of this invention. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a plan view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross sectional view taken along a cross sectional line XIV-XIV shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 24 is a cross-sectional view showing a step of a method of manufacturing a semiconductor memory device as a comparative example in the embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 24 is a cross-sectional view showing a step of a method of manufacturing a semiconductor memory device according to a variation in the embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 6 is a circuit diagram of a memory cell in an AND type flash memory according to a third embodiment of the present invention. 3 is a circuit diagram of a memory cell in a NAND flash memory in the same embodiment. FIG. 3 is a circuit diagram of a memory cell in a NOR type flash memory in the same embodiment. FIG. FIG. 19 is a cross-sectional view showing a step of a method of manufacturing an AND type flash memory in the embodiment. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the same embodiment. FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28 in the same embodiment. FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in the same embodiment. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment. FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in the same embodiment. FIG. 35 is a cross sectional view taken along a cross sectional line XXXV-XXXV shown in FIG. 34 in the same embodiment. 4 is a cross-sectional view showing a step of a method for manufacturing a NAND-type or NOR-type flash memory in the embodiment. FIG. FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the same embodiment. FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the same embodiment. FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38 in the same embodiment. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment. FIG. 41 is a cross sectional view taken along a cross sectional line XLI-XLI shown in FIG. 40 in the embodiment. In the same embodiment, it is sectional drawing of the memory cell of DRAM which concerns on a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2,20 Gate insulating film, 3, 9, 9a, 9b, 12, 22, 22a, 23, 31 Polysilicon film, 4 Silicon nitride film, 5,15 Silicon oxide film, 6,8 Thermal oxide film 7 Side wall insulating film, 9c, 24, 32 Floating gate electrode, 10 depression, 11, 25, 33 ONO film, 13 Tungsten silicide film, 14, 26, 34 Control gate electrode, 21 Trench isolation region, 27a, 27b, 42a, 42b Source / drain region, 28 insulating film, 40 element isolation region, 41 gate electrode, 43 interlayer insulating film, 44 storage node plug, 45 storage node, 46 dielectric film, 47 cell plate.

Claims (13)

A semiconductor memory device in which memory cells are arranged in a matrix,
The memory cell is
A plurality of assist gate electrodes formed on the main surface of the semiconductor substrate and spaced apart from each other by interposing a first gate insulating film;
A columnar floating gate electrode formed on a region of the semiconductor substrate sandwiched between adjacent assist gate electrodes with a second gate insulating film interposed therebetween and having opposite side surfaces and an upper surface;
An insulating film formed to cover the floating gate electrode;
A control gate electrode formed on the floating gate electrode with the insulating film interposed therebetween,
A semiconductor memory device in which corners are rounded at an upper end portion of the floating gate electrode.   The semiconductor memory device according to claim 1, wherein the upper surface of the floating gate electrode is formed in a gentle convex shape from one side surface of the opposite side surfaces to the other side surface.   The semiconductor memory device according to claim 1, wherein the upper surface and each side surface are smoothly connected. A method of manufacturing a semiconductor memory device in which memory cells are arranged in a matrix,
Forming a plurality of assist gate electrodes spaced apart from each other on a main surface of the semiconductor substrate;
Forming a columnar second conductive layer to be a floating gate electrode in a region of the semiconductor substrate sandwiched between adjacent assist gate electrodes;
Forming a first insulating film so as to cover the columnar second conductive layer;
Forming a third conductive layer to be a control gate electrode on the first insulating film; and applying predetermined processing to the third conductive layer and the second conductive layer to thereby form a control gate electrode and a floating gate electrode, respectively. Forming a process,
In the step of forming the columnar second conductive layer, an upper end portion of the columnar second conductive layer is rounded by performing etching. The step of forming the assist gate electrode includes:
Forming a first conductive layer to be an assist gate electrode;
Forming a second insulating film having a predetermined thickness on the first conductive layer;
Forming a plurality of assist gate electrodes spaced apart from each other by exposing the surface of the semiconductor substrate by performing predetermined processing on the second insulating film and the first conductive layer;
Removing a portion of the second insulating film located on the assist gate electrode,
5. The step of forming the columnar second conductive layer is sputter-etched simultaneously with the step of removing the portion of the second insulating film located on the assist gate electrode as the etching. Manufacturing method of the semiconductor memory device of FIG.   The method of manufacturing a semiconductor memory device according to claim 4, wherein in the step of forming the columnar second conductive layer, either isotropic dry etching or wet etching is performed as the etching. A method of manufacturing a semiconductor memory device including a memory cell including a first electrode for accumulating charge as information,
Forming a first conductive layer to be a first electrode on a main surface of a semiconductor substrate;
Forming a first electrode by processing the first conductive layer;
Forming an insulating film on the first electrode;
Forming a second electrode with the insulating film interposed on the first electrode,
The step of forming the first electrode includes:
A patterning step of forming the first conductive layer into a predetermined shape;
And a step of rounding corners by etching a portion of the first conductive layer patterned into a predetermined shape.   8. The method of manufacturing a semiconductor memory device according to claim 7, wherein isotropic dry etching is performed as the etching in the step of rounding the corners.   8. The method of manufacturing a semiconductor memory device according to claim 7, wherein wet etching is performed as the etching in the step of rounding the corners. The first electrode is formed as a floating gate electrode of a memory cell transistor in the memory cell;
The method of manufacturing a semiconductor memory device according to claim 7, wherein the second electrode is formed as a control gate electrode of the memory cell transistor.   11. The method of manufacturing a semiconductor memory device according to claim 10, wherein a plurality of the memory cell transistors are formed to be connected in series.   11. The method of manufacturing a semiconductor memory device according to claim 10, wherein a plurality of the memory cell transistors are formed to be connected in parallel. The first electrode is formed as a storage node of a capacitor of a dynamic random access memory in a memory cell;
The method of manufacturing a semiconductor memory device according to claim 7, wherein the second electrode is formed as a cell plate of the capacitor.

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