JPH11289021A - Semiconductor integrated-circuit device and its manufacture as well as microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a read characteristic and a memory holding characteristic, by a method wherein, as information storage means, a means which stores a positive electric charge, a means which stores a negative electric charge and a means which does not store an electric charge are installed. SOLUTION: Respective prescribed potentials are applied to a source region 8, a drain region 9 and a control gate 15. Then, a state that a positive electric charge is stored in a trap inside a gate insulating film, a state that a negative electric charge is stored in the trap inside the gate insulating film, a state that a negative electric charge is stored in the trap inside the gate insulating film and in a floating gate 11, and a state that an electric charge is not stored in the floating gate 11 and in the trap inside the gate insulating film, can be generated selectively. As a result, the information storage number of one flash EEPROM cell becomes a quaternary value, the information of two bits can be stored in one cell, and the large capacity of a memory can be achieved. When the quaternary value is constituted in this manner, a memory is held surely, and a read characteristic is made good.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEPROM.
OM (electrically erasable and programmableread o
The present invention relates to a semiconductor integrated circuit device having an nly memory, a method of manufacturing the same, and a microcomputer, and more particularly to a technology effective when applied to a multi-valued technology of a flash EEPROM (hereinafter also referred to as a flash memory).

[0002]

2. Description of the Related Art A flash memory is known as one of nonvolatile storage elements. As flash memory, F
LOTOX (floating-gate tunnel oxide) type or MNO
An S (metal nitride oxide semiconductor) type or the like is known.

In the FLOTOX type, a tunnel oxide film (first gate insulating film) and a floating gate (floating gate: F) are formed on a channel portion formed in a surface portion of a semiconductor substrate.
G), an interlayer insulating film (second gate insulating film) and a control gate (control gate: CG) are sequentially stacked, and a charge is accumulated in the floating gate by applying a high voltage, or the charge is stored in the channel portion. When released, a charge storage state and an erase state are generated, and writing and reading of 1-bit information are performed using the charge storage state and the erase state.

The MNOS type has a structure in which charges are accumulated in traps near an interface between two insulating films composed of an oxide film (silicon dioxide film) and a nitride film (nitride film).

For flash memories, for example,
Published by the Industrial Research Committee, "Electronic Materials", April 1993, P32-P35
It is described in. This document also describes a block diagram of a 16M flash memory and a NOR, NAND, DINOR, and AND memory array as a configuration for reducing the memory size.

A multi-level flash memory using a single memory cell with a plurality of bits is described in "Nikkei Micro Devices", November 1997, P124-P1 issued by Nikkei BP.
31 "Multi-level flash memory has begun commercialization". The readout principle and operation of the multi-valued technology are described.

Also, "Nikkei Micro Devices", February 1997, published by Nikkei BP, P62 to P71, "High-capacity flash memory in which multi-valued and three-dimensional cells are indispensable" has eight values, three bits / cell and 16 bits. Value, experimental data of 4 bits / cell are described.

[0008] Further, in the "Electronic Materials", January 1997 issue, P47 to P51, published by the Industrial Research Institute, the development of a multi-valued technology of a flash memory to a microcomputer (microcomputer) is described.

[0009]

It is becoming difficult to increase the capacity of the flash memory due to the limit of fine processing and the limit of scaling due to reliability characteristics. Therefore, as one of the techniques for increasing the capacity of a memory, a multi-valued technology for holding a plurality of bits of data in one memory cell has been developed.

In the conventional multi-value technique, multi-value is obtained by generating an erase state and a plurality of charge accumulation states. The plurality of charge storage states are generated by, for example, differences in the amount of electrons stored in the floating gate.

However, in this method, as described in the above-mentioned document, it is difficult to control the distribution width of the accumulated charge with respect to each threshold voltage, and it is difficult to control the variation of the threshold value.

An object of the present invention is to provide a multilevel flash EEPROM (semiconductor integrated circuit device) having good read characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a multilevel flash EEPROM (semiconductor integrated circuit device) having good memory retention characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a microcomputer having a flash EEPROM having good memory retention characteristics and excellent read characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A semiconductor integrated circuit device having a nonvolatile storage element, wherein the number of information stored in one cell of the nonvolatile storage element is three or more, wherein the information storage means stores a positive charge. Means for accumulating negative charges, and means for not accumulating charges.

A semiconductor integrated circuit device having a non-volatile memory element, comprising: a pair of source and drain regions formed in a surface layer of an active region of a semiconductor substrate; and a channel portion between the source and drain regions A gate insulating film formed of a multilayer tunnel insulating film formed on the gate insulating film and capable of storing charges in traps near the film interface; a floating gate formed on the gate insulating film and capable of storing charges; And a control gate formed with an insulating film interposed therebetween. By applying a predetermined potential to each of the source region, the drain region, and the control gate, positive charges are accumulated in traps in the gate insulating film. A state in which negative charges are accumulated in traps in the gate insulating film; a trap in the gate insulating film; State to accumulate a negative charge Yu gate, having the nonvolatile memory element is configured to selectively generate a state of not storing charge in the trap of the floating gate and the gate insulating lining.

The means for storing positive charges stores positive charges in traps in the gate insulating film, and the means for storing negative charges stores or stores negative charges in traps in the gate insulating film. Negative charges are stored in the traps in the gate insulating film and the floating gate.

The gate insulating film is composed of a silicon dioxide film and a nitride film formed sequentially on the active region, or a silicon dioxide film and a nitride film and a silicon dioxide film.

The floating gate has a two-layer structure composed of a lower floating gate film and an upper floating gate film. The lower floating gate film has the same pattern as the gate insulating film. And the capacitance between the control gate and the lower floating gate film is larger than the capacitance between the lower floating gate film and the semiconductor substrate.

A diffusion layer constituting a source line electrically contacting the source region and a diffusion layer constituting a bit line electrically contacting the drain region are provided in the active region.

In the semiconductor integrated circuit device having the above configuration,
By applying a predetermined potential to each of the source region, the drain region, and the control gate, a state in which positive charges are accumulated in traps in the gate insulating film, and negative charges are trapped in traps in the gate insulating film. A state in which a charge is accumulated, a state in which negative charges are accumulated in the traps in the gate insulating film and the floating gate, and a state in which charges are not accumulated in the traps in the floating gate and the gate insulating film are selectively generated. The storage element can store 2-bit information.

Such a semiconductor integrated circuit device is manufactured by the following method.

An electric charge is accumulated in a pair of source and drain regions formed in the surface layer of the active region of the semiconductor substrate, and in a trap formed near the interface between the source region and the drain region on the channel between the source region and the drain region. A gate insulating film made of a multi-layered tunnel insulating film, and a floating gate formed on the gate insulating film and capable of storing electric charge,
A control gate formed on the floating gate with an interlayer insulating film interposed therebetween, and applying a predetermined potential to each of the source region, the drain region, and the control gate to generate a trap in the gate insulating film. A state in which a positive charge is stored, a state in which a negative charge is stored in a trap in the gate insulating film, a state in which a negative charge is stored in the trap and the floating gate in the gate insulating film,
A method of manufacturing a semiconductor integrated circuit device having a nonvolatile memory element configured to selectively generate a state in which no charge is accumulated in a trap in the floating gate and a trap in the gate insulating film. A step of preparing a semiconductor substrate having at least an active region; a step of forming a first gate insulating film constituting a tunnel insulating film for forming the gate insulating film on the active region; Forming a second gate insulating film constituting a tunnel insulating film on the film to form a vicinity of an interface for accumulating charges, and forming a floating gate forming conductor film on the second gate insulating film Performing a step of forming an interlayer insulating film on the floating gate forming conductor film; forming a control gate forming conductor film on the interlayer insulating film; Forming an insulating film on the body layer,
Etching the insulating film and the control gate forming conductor film thereunder to form a control gate on which an insulating film is to be formed; and using the insulating film and the control gate as a mask to form the interlayer insulating film and the floating gate. Forming a gate insulating film including an interlayer insulating film, a floating gate, and the first and second gate insulating films by sequentially etching the conductive film and the first and second gate insulating films; Forming a semiconductor region serving as a source region or a drain region in the active region on both ends of the multilayer film using a multilayer film including the floating gate, the interlayer insulating film, the control gate, and the insulating film as a mask; Forming sidewalls made of an insulating film on both end surfaces of the multilayer film.

A third gate insulating film is formed on the second gate insulating film forming film.
Is formed. The first gate insulating film forming film is formed of a silicon dioxide film, the second gate insulating film forming film is formed of a nitride film, and the third gate insulating film forming film is formed of a silicon dioxide film.

(2) The semiconductor integrated circuit device having the structure of the means (1) is manufactured by the following method.

An electric charge is accumulated in a pair of source and drain regions formed on the surface layer of the active region of the semiconductor substrate, and on a channel formed between the source region and the drain region and near a film interface. A gate insulating film made of a multi-layered tunnel insulating film, and a floating gate formed on the gate insulating film and capable of storing electric charge,
A control gate formed on the floating gate with an interlayer insulating film interposed therebetween, wherein the floating gate has a two-layer structure including a lower floating gate film and an upper floating gate film, and the lower floating gate film is In the same pattern as the insulating film, the upper floating gate film has a larger area than the lower floating gate film, and the capacitance between the control gate and the upper floating gate film is larger than the capacitance between the lower floating gate film and the semiconductor substrate. A state in which positive charges are accumulated in traps in the gate insulating film by applying a predetermined potential to the source region, the drain region, and the control gate, respectively, and negative charges are accumulated in traps in the gate insulating film. State,
Nonvolatile memory configured to selectively generate a state in which negative charges are stored in traps and floating gates in the gate insulating film, and a state in which no charges are stored in traps in the floating gates and traps in the gate insulating film. A method of manufacturing a semiconductor integrated circuit device having an element, comprising: forming a first gate insulating film constituting a tunnel insulating film for forming the gate insulating film on the active region; Forming a second gate insulating film forming film constituting a tunnel insulating film on the gate insulating film forming film and forming an area near an interface for accumulating electric charges; and forming a second gate insulating film forming film on the second gate insulating film forming film. Forming a lower floating gate film forming conductor film, forming a protective film on the lower floating gate film forming conductor film, forming the lower floating gate film forming conductor film on the lower floating gate film forming conductor film; Forming a lower floating gate film and a second gate insulating film by etching the second gate insulating film forming film in the same pattern, and selectively forming the gate mask by selectively etching the nitride film; Etching the lower floating gate film forming conductor film and the second gate insulating film forming film by using the gate mask to form a lower floating gate film and a second gate insulating film; Forming a semiconductor region serving as a source region or a drain region in the active region on both ends of the lower floating gate film using the insulating film, the lower floating gate film, and the gate mask as masks; Forming side walls on the end surfaces of the film, the lower floating gate film, and the gate mask on the side of the source region and the drain region; Forming a floating gate composed of a lower floating gate film and an upper floating gate film by forming an upper floating gate film having a larger area than the lower floating gate film on the lower floating gate film after removing the mask, Forming an interlayer insulating film so as to cover the upper floating gate film and forming a control gate on the interlayer insulating film.

A third gate insulating film is formed on the second gate insulating film forming film.
Is formed. The first gate insulating film forming film is formed of a silicon dioxide film, the second gate insulating film forming film is formed of a nitride film, and the third gate insulating film forming film is formed of a silicon dioxide film.

(3) In the configuration of the means (1) or (2), by applying a predetermined potential to each of the source region, the drain region and the control gate, the trap in the gate insulating film is reduced. A state in which positive charges are stored, a state in which negative charges are stored in traps in the gate insulating film, a state in which negative charges are stored in traps and the floating gate in the gate insulating film, the floating gate and the gate A structure in which a state in which no charge is accumulated in a trap in an insulating film is selectively generated, and a plurality of states having different negative charge amounts are generated in the floating gate, and a trap in the gate insulating film is generated. Wherein the semiconductor integrated circuit device is configured to generate a plurality of states having different positive charge amounts.

(4) A microcomputer having a control unit and a memory unit, wherein a part or all of the memory unit is any one of the means (1), (2) and (3). Of nonvolatile storage elements.

According to the means (1), (a) a state in which positive charges are accumulated in traps in the gate insulating film by applying a predetermined potential to each of the source region, the drain region, and the control gate; A state where negative charges are stored in traps in the gate insulating film, a state where negative charges are stored in traps and floating gates in the gate insulating film,
Since a state in which no charge is accumulated in the trap in the floating gate and the gate insulating film can be selectively generated,
The number of information stored in one cell of the flash EEPROM becomes quaternary, and two bits of information can be stored in one cell, so that the capacity of the memory can be increased.

(B) The four values can be obtained by applying different potentials, and the difference in the amount of charge stored in the same state is not used as in the prior art, so that the memory retention characteristics are improved and the read characteristics are improved. That is, the means for forming the four values is:
Means for storing no charge, means for storing positive charge, means for storing negative charge in traps in the gate insulating film, means for storing negative charges in traps and floating gates in the gate insulating film, and retains memory. And readout characteristics are improved.

(C) When the gate insulating film is composed of a silicon dioxide film, a nitride film and a silicon dioxide film, leakage of electric charge from the floating gate to the control gate via the interlayer insulating film can be suppressed.

(D) The floating gate is formed of a lower floating gate film and an upper floating gate film, and the lower floating gate film has the same pattern as the gate insulating film, and the upper floating gate film has an area larger than that of the lower floating gate film. The capacitance between the control gate and the lower floating gate film is larger than the capacitance between the lower floating gate film and the semiconductor substrate, the capacitance coupling ratio is increased, and the electric field of the floating gate can be increased. The voltage can be reduced, and the voltage of the element can be reduced.

The means (2) can provide the same effect as the means (1).

According to the means of (3), the floating gate is configured to generate a plurality of states having different negative charge amounts, and the trap in the gate insulating film is configured to have a positive state. Since a plurality of states having different charge amounts are generated, the number of information stored per cell can be made larger than four values, and the capacity of the flash EEPROM can be increased.

According to the means (4), since the number of information stored in one cell of the flash EEPROM constituting the memory section becomes four or more, the capacity of the memory section can be increased. Further, the reliability of the memory section is also high, and the reliability of the microcomputer can be improved.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) In Embodiment 1, an example in which the present invention is applied to a flash EEPROM (flash memory) as a nonvolatile storage element will be described.

FIGS. 1 to 17 are diagrams relating to a flash EEPROM according to an embodiment (Embodiment 1) of the present invention.

The flash EEPROM of the first embodiment
Is incorporated in the microcomputer shown in FIG. 5, for example. The microcomputer is composed of one microcomputer chip 40. The microcomputer chip 40 is formed on the semiconductor substrate 1 made of rectangular silicon, and includes the control unit 41 and the arithmetic unit 4.
2, a memory unit 43, an input unit 44, an output unit 45, and the like. Further, an electrode pad 46 is arranged on the periphery of the microcomputer chip 40.

In the first embodiment, the memory section 43 is constituted by a flash EEPROM.

A flash EEPROM is, for example, shown in FIG.
Has an AND type memory array configuration.

In the AND type memory array configuration, a plurality (1 to n) of flash EEPROMs (FM: FM1 to FM1)
FMn) are connected in parallel to form one block, and the drain of the first flash memory (FM1) of this block is connected to the global bit (global data) line 50.
Is connected to the source of a block selection transistor 52 connected to the contact 51 of the block transistor via the drain.

The source of the last flash memory (FMn) in one block is connected to the drain of a block select transistor 57 connected to the contact 56 of the global source line 55 via the source.

Each block of flash memory FM (F
The drains of M1 to FMn) are connected to a local bit (local data) line 59, and the sources are connected to a local source line 58.

The control gate of each flash memory FM is connected to each word line.

In the normal case, that is, when the number of information stored in one cell of the flash memory is binary (1 bit), 6
In the case of a 4M flash memory, the number of memory cells (word lines) in one block is 128. In the case of the first embodiment, however, the number of information stored in one cell of the flash memory is four values (two bits) as described later. Therefore, the number of memory cells (word lines) is halved to 64.

As a result, the area of the memory section 43 can be reduced or the capacity of the memory can be increased.

Although not shown, the control unit 41 includes:
A control circuit for writing, erasing, and reading the four values is also incorporated.

Before describing the structure of the flash memory constituting the memory section 43, the features of the flash memory of the present invention will be briefly described.

In the flash memory of the present invention, the number of information stored in a single memory cell is three or more.

In the flash memory of the present invention, the information storage means has a means for storing positive charges, a means for storing negative charges, and a means for not storing charges. That is, electric charges can be accumulated in a pair of source and drain regions formed in the surface layer of the active region of the semiconductor substrate, and in a trap formed near a film interface formed on a channel between the source region and the drain region. A gate insulating film formed of a multilayer tunnel insulating film, a floating gate formed on the gate insulating film and capable of storing electric charge, and a control gate formed on the floating gate via an interlayer insulating film; The means for accumulating positive charges accumulates positive charges in traps in the gate insulating film, and the means for accumulating negative charges accumulates negative charges in traps in the gate insulating film or the gate insulating film. Negative charges are stored in traps in the film and the floating gate.

Further, depending on the form in which a potential is applied to each of the source region, the drain region, and the control gate, a plurality of states having different negative charge amounts can be generated in the floating gate. In the trap in the gate insulating film, a plurality of states having different positive charge amounts can be generated, so that the configuration can be made more multi-valued.

Next, the structure of the flash memory 20 will be described.

The flash memory 20 according to the first embodiment includes:
As shown in FIG. 3, it is formed in an active region of a semiconductor substrate 1 made of, for example, p-type silicon (Si). In this figure and the following similar figures, wells are omitted for convenience of explanation. That is, flash memory 20 is formed in, for example, a p-type well having a double well structure.

In the surface layer of the active region of the semiconductor substrate 1,
A gate insulating film 21 made of a multilayer tunnel insulating film is formed. The gate insulating film 21 made of a multilayer tunnel insulating film is composed of a thin gate oxide film 3, a gate nitride film 4, and a thin gate oxide film 5 sequentially stacked on the semiconductor substrate 1, and the oxide film is formed of silicon dioxide by thermal oxidation. (S
iO ₂ ) film. The gate nitride film 4 is made of Si ₃ N ₄
It is formed of a film (nitride film). As an example of the thickness of each film, the thin gate oxide film 3 is about 3 nm, the gate nitride film 4 is about 10 nm, and the thin gate oxide film 5 is 5 nm.
nm.

Further, n-type semiconductor regions are formed in the surface layer portions of the semiconductor substrate 1 at both ends of the gate insulating film 21, respectively. One of the semiconductor regions is a source region 8
And the other is the drain region 9.

The surface portion immediately below the gate insulating film 21 between the source region 8 and the drain region 9 becomes a channel portion.

[0061] The channel portion, the source region 8, the drain region 9, a field insulating film 1 made of SiO ₂ film formed on the inner side of the element isolation insulating film 2 made of SiO ₂ film
2 is formed in the area inside. Element isolation insulating film 2
And an example of the thickness of the field insulating film 12 is as follows:
The element isolation insulating film 2 has a thickness of about 400 nm, and the field insulating film 12 has a thickness of about 200 nm.

In the semiconductor region under the field insulating film 12, an n-type region having a high impurity concentration is provided by diffusion to form wiring layers 18 and 19. One of the wiring layers 1
8 contacts the source region 8 to become a local source line 58, and the other wiring layer 19 contacts the drain region 9 to become a local bit line 59.

On the gate insulating film 21, a lower floating gate film 6, which has the same shape as the gate insulating film 21 and overlaps with the gate insulating film 21, is formed. This lower floating gate film 6
For example, it is formed of polysilicon of about 100 nm. Insulating film spacers 10 are provided on the end surfaces of the source region 8 and the drain region 9 of the gate insulating film 21 and the lower floating gate film 6. The insulating film spacer 10 is formed between the raised end of the field insulating film 12 and electrically insulates the lower floating gate film 6 from the source region 8, the wiring layer 18, the drain region 9, and the wiring layer 19. We are trying to separate.

On the lower floating gate film 6, the insulating film spacer 10, and the field insulating film 12, an upper floating gate film 13 longer than the lower floating gate film 6 is provided. The upper floating gate film 13 has the same width as the lower floating gate film 6, but has a longer length. The upper floating gate film 13 is, for example, 4
The thickness is about 0 nm.

This is because the capacitance between the lower and upper portions of the floating gate formed by the lower floating gate film 6 and the upper floating gate film 13 is changed to change the capacitance coupling ratio. Therefore, if the capacitance coupling ratio is not changed, the floating gate does not need to have a two-layer structure.

An interlayer insulating film 14 is provided so as to cover the upper floating gate film 13. This interlayer insulating film 14 is composed of, for example, a SiN film / SiO ₂ film / SiN film / SiO ₂ film formed by CVD (vapor phase chemical growth). The lowermost SiO ₂ film is about 5 nm, the other SiO ₂ films are about 3 nm, and the SiN film is about 10 nm, which is about 30 nm in total.

A control gate 15 is provided on the interlayer insulating film 14 and the element isolation insulating film 2. The control gate 15 extends to be a word line. The control gate 15 is formed of, for example, a polycide film whose upper layer is formed of a silicide layer made of tungsten silicide (WSi) and a polysilicon film below this silicide layer. The silicide layer has a thickness of about 150 nm, and the polysilicon film has a thickness of about 100 nm.

By the lower floating gate film 6 and the upper floating gate film 13, a floating gate (floating gate:
FG) 11 are formed.

The upper floating gate film 13 has a larger area than the lower floating gate film 6 and the capacitance between the upper floating gate film 13 and the control gate 15 is larger than the capacitance between the lower floating gate film 6 and the semiconductor substrate 1. The capacitance coupling ratio increases, the electric field of the floating gate 11 can be increased, and the voltage applied to the control gate 15 can be reduced. As a result, a lower voltage of the flash memory device can be achieved.

On the control gate 15, a memory cell protection insulating film 16 is formed. An interlayer insulating film 17 is provided on the memory cell protection insulating film 16.

On the interlayer insulating film 17, a global bit line 50 made of metal wiring of Al or the like is provided.

FIG. 4 is a schematic plan view showing the floating gate 11 (the lower floating gate film 6 and the upper floating gate film 13) and the control gate 15 in one cell portion of the flash memory. The width (W) of the lower floating gate film 6 and that of the upper floating gate film 13 are the same, but the length is longer than the length (L ₁ ) of the lower floating gate film 6 (L ₁ ). L
₂ ) is longer.

The width of a single memory cell 30 is W _C ,
The length is L _C.

Here, as an example of the dimensions of each part, W _C
Is about 0.8 μm, L _C is about 1.6 μm, and W is 0.4
μm, L ₁ is about 0.4 μm, and L ₂ is about 1.2 μm.

Next, such a flash memory 20
Will be described with reference to FIGS. 7 to 17.

First, a semiconductor substrate 1 made of single crystal silicon is prepared, and then, as shown in FIG. 7, the main surface of the semiconductor substrate 1 other than the region where the memory cell is formed is subjected to a conventional selective thermal oxidation treatment. A thick element isolation insulating film 2 made of a silicon film (SiO ₂ film) is formed. The thickness of the isolation insulating film 2 is, for example, about 400 nm.

Next, as shown in FIG. 7, a thin gate oxide film 3 is formed as a first gate insulating film constituting a tunnel insulating film for forming a gate insulating film 21. The thin gate oxide film 3 is formed on the surface of the semiconductor substrate 1 by a thermal oxidation SiO ₂ film. Thin gate oxide film 3
Is about 3 nm, for example.

Next, a gate nitride film 4 made of a nitride film (Si ₃ N ₄ film) is formed as a second gate insulating film forming film constituting a tunnel insulating film on the first gate insulating film. As a result, an area (trap) near the interface where charges are accumulated is formed between the thin gate oxide film 3 and the gate nitride film 4.

If only the vicinity of the interface for storing charges is formed, only the thin gate oxide film 3 and the gate nitride film 4 may be used. In the first embodiment, however, in order to suppress the leakage of charges to the control gate, As shown in FIG. 8, a third gate insulating film forming film is formed. This film is a thin gate oxide film 5 made of a SiO ₂ film.

Thin gate oxide film 3 and gate nitride film 4
Is formed by a CVD apparatus, a plasma CVD apparatus, or the like.

For example, the thickness of the thin gate oxide film 3 is 3
The thickness of the gate nitride film 4 is about 10 nm, and the thickness of the thin gate oxide film 5 is about 5 nm.

The thin gate oxide film 3 and the gate nitride film 4
The gate insulating film 21 having a multilayer structure is formed by the thin gate oxide film 5.

Next, as shown in FIG. 9, the gate nitride film 4 and the thin gate oxide film 5 are formed by a CVD apparatus.
A conductive film 6a for forming a floating gate and a protective film 23 made of a nitride film are sequentially formed on a second insulating film for forming a gate insulating film made of. The thickness of the protective film 23 is, for example, 12
It becomes about 0 nm.

[0084] Then, the protective film 23 and protective film 23 are sequentially selectively etching the following layers, the width W as shown in FIG. 4, the length L ₁ of the protective film 23, the lower the floating gate layer 6, A thin gate oxide film 5 and a gate nitride film 4 are formed. At this time, the thin gate oxide film 3 is etched to an intermediate depth.

Next, as shown in FIG.
3. Using the inter-element isolation insulating film 2 as a mask, a source region 8 and a drain region 9 are formed in the surface layer of the semiconductor substrate 1 by implantation (implantation) and diffusion (annealing) of an n-type determining impurity such as arsenic.

Next, as shown in FIG. 11, an insulating film 24 is formed over the entire main surface of the semiconductor substrate 1.

Next, as shown in FIG. 12, the insulating film 24 is etched by anisotropic etching to form a gate nitride film 4, a thin gate oxide film 5, and a lower floating gate film 6.
Then, a side wall (insulating film spacer) 10 is formed on the end face on the source region 8 and drain region 9 side.

Next, n-type determining impurities such as arsenic are implanted (implanted) into the surface layer of the semiconductor substrate 1 by using the protective film 23, the insulating film spacer 10, and the element isolation insulating film 2 as a mask.
Then, by performing diffusion (annealing), wiring layers 18 and 19 made of high concentration n-type are formed (see FIG. 12). These wiring layers 18 and 19 are in contact with the source region 8 and the drain region 9 and are used as local source lines 58 and local bit lines 59. By the above-described processing, as shown in FIG.
A field insulating film 12 having a thickness of about nm is formed.

Next, the protective film 23 is removed, and the upper floating gate film 13 covering the lower floating gate film 6 and the insulating film spacer 10 and extending to the outside of the insulating film spacer 10 is formed. It is formed by selective etching (see FIG. 14). The upper floating gate film 13 is made of a polysilicon film and has a thickness of, for example, about 40 nm.

The upper floating gate film 13 has a pattern as shown in FIG. 4, having a width W and a length L ₂ .

Thus, a floating gate (floating gate: FG) 11 is formed by the lower floating gate film 6 and the upper floating gate film 13.

Next, the entire main surface of the semiconductor substrate 1 is subjected to CVD.
The interlayer insulating film 14 is formed by the method (see FIG. 15).
The interlayer insulating film 14 is composed of, for example, a SiN film / SiO ₂ film / SiN film / SiO ₂ film. Lowermost Si
O ₂ film is about 5 nm, other SiO ₂ films are about 3 nm, S
The iN film has a thickness of about 10 nm, and has a total thickness of about 30 nm.

Next, a control gate 15 is formed on the interlayer insulating film 14, the element isolation insulating film 2 and the like by the CVD method and the subsequent heat treatment and etching (see FIG. 16). The control gate 15 is formed of, for example, a polycide film whose upper layer is formed of a silicide layer made of tungsten silicide (WSi) and a polysilicon film below this silicide layer. The silicide layer is, for example, about 150 nm, and the polysilicon film is 100
nm. The control gate 15 extends to be a word line. The width of the control gate 15 is also W, which is the same as the width (W) of the floating gate 11, for example, 0.4 μm.
It has become about.

Next, as shown in FIG. 17, a memory cell protective insulating film 16 is formed over the entire main surface of the semiconductor substrate 1.

Although not shown in FIG. 17, an interlayer insulating film 17 is provided on the main surface of semiconductor substrate 1.
A contact hole is formed, and a metal film for forming a wiring is formed, patterned, and the like, and a global bit line 50 and the like are formed on the interlayer insulating film 17. Although not shown, a final passivation film is provided on the main surface of the semiconductor substrate 1 to protect each circuit formed on the main surface of the semiconductor substrate 1. Each insulating film is formed by CVD
It is a SiO ₂ film or a Si ₃ N ₄ film by a method or the like, or a composite film thereof.

Next, the semiconductor substrate 1 is cut lengthwise and widthwise to form a microcomputer chip 40 as shown in FIG.
Will be manufactured in large numbers.

Next, a state where the number of information stored in one memory cell becomes four values in the flash memory 20 of the first embodiment will be described.

FIGS. 1A to 1D are schematic diagrams showing an erased / written state of a flash memory according to the present invention, and FIG. 2 is a graph showing a quaternary information holding mode per cell in the flash memory. .

The flash memory 20 according to the first embodiment has an MNOS (MONOS) structure in which charges are stored in traps in the gate insulating film and a FLOTOX structure in which charges are stored in the floating gate. I have.

That is, a trap for storing a positive charge or a negative charge exists near the interface between the thin gate oxide film 3 and the gate nitride film 4 (MNOS structure), and the floating gate 11
Can accumulate electric charges (FLOTOX structure).

The amount of charge stored in the floating gate 11 is changed by changing the applied voltage. this is,
This can also be done in the trap.

FIGS. 1A to 1D show a state in which the number of information stored in one memory cell is quaternary.

FIG. 1A shows an erased state.
A high negative voltage (for example, -5 to -10
By applying V), holes (holes) 26 are accumulated near the interface (trap) between the thin gate oxide film 3 and the gate nitride film 4 from the semiconductor substrate (silicon substrate) 1 side over the entire channel. .

[0104] In this erased state, as shown in FIG. 2, the potential of the memory cell on the left side of the reference potential V ₁ will be is positioned, the 2 bit information (0, 0).

FIG. 1B shows a write state (1), in which a low positive voltage (for example,
By applying a voltage of about 5 V, negative charges accumulated in the floating gate 11 having the FLOTOX structure are released toward the semiconductor substrate 1 and trapped by MNOS (the interface between the thin gate oxide film 3 and the gate nitride film 4). (Nearby), the positive charge or the negative charge is released to the semiconductor substrate 1 side, so that no charge is stored.

In the case of this write state (1), as shown in FIG. 2, the potential of the memory cell is located between the reference potential V ₁ and the reference potential V ₂ , and (0,
1).

FIG. 1C shows a write state (2). By applying a positive voltage (for example, about 10 V) higher than that in the write state (1) to the control gate 15, this time, Accumulates electrons 27 from the semiconductor substrate 1 side in the entire surface of the channel in traps (near the interface between the thin gate oxide film 3 and the gate nitride film 4) in the MNOS portion.

In the write state (2), as shown in FIG. 2, the potential of the memory cell is located between the reference potential V ₂ and the reference potential V ₂ .
0).

FIG. 1D shows the write state (3), in which a high positive voltage is applied to the control gate 15 or the write time is lengthened to change the electrons 27 to MNO.
S trap (thin gate oxide film 3 and gate nitride film 4)
And the floating gate 11 of the FLOTOX structure
And the state in which the electrons 27 are stored in the largest amount.

[0110] In the case of the write state (2), as shown in FIG. 2, it will be the potential of the memory cell is located at a position higher than the reference potential V _3, with 2 bit information (1, 1)
become.

Therefore, by detecting the reading of the potentials of the memory cells separately based on the reference potentials V _1, V _{2 and} V ₃ , it is possible to store four-level information in one memory cell.

According to the first embodiment, the following effects can be obtained.

(1) Source region 8 and drain region 9
A state where positive charges are stored in traps in the gate insulating film 21 by applying a predetermined potential to the control gate 15, a state where negative charges are stored in traps in the gate insulating film 21, A state in which negative charges are accumulated in the trap and floating gate 11 in the cell 21 and a state in which electric charges are not accumulated in the trap in the floating gate 11 and the trap 21 in the gate insulating film 21 can be selectively generated. Has four values, and one cell can store two bits of information, thereby increasing the capacity of the memory.

(2) According to the above (1), the flash EE
The area of the PROM can be reduced.

(3) The four values can be obtained by applying different potentials, and the difference in the amount of charge stored in the same state is not used as in the prior art, so that the memory retention characteristics are improved and the read characteristics are improved. . That is, the means for forming the four values is:
Means for not storing charges, means for storing positive charges, means for storing negative charges in traps in the gate insulating film 21,
This serves as a means for accumulating negative charges in the trap and the floating gate 11 in the gate insulating film 21, so that memory retention is ensured and read characteristics are improved.

(4) Since the gate insulating film 21 is composed of a silicon dioxide film, a nitride film and a silicon dioxide film, the floating gate 11
4, leakage of electric charge to the control gate 15 can be suppressed.

(5) The floating gate 11 is formed by the lower floating gate film 6 and the upper floating gate film 13, and the lower floating gate film 6 has the same pattern as the gate insulating film 21, and the upper floating gate film 13 is lower floating. The capacitance between the control gate 15 and the lower floating gate film 6 is larger than the capacitance between the lower floating gate film 6 and the semiconductor substrate 1, the capacitance coupling ratio increases, and the electric field of the floating gate 11 increases. , The voltage applied to the control gate 15 can be reduced, and the voltage of the device can be reduced.

(6) Flash EEPROM of Embodiment 1
In the microcomputer in which the memory unit 43 is configured by the OM, the number of stored information per memory cell is four or more, so that the capacity of the memory unit can be increased. Also,
The reliability of the memory unit 43 is also high, and the reliability of the microcomputer can be improved. Further, downsizing of the microcomputer chip can be achieved.

Note that the flash memory 2 of the first embodiment
0, the potential applied to the control gate 15 or the like is changed to generate a plurality of states with different amounts of negative charges in the floating gate 11, and the number of information stored per memory cell is quaternary. More multi-valued configurations are possible. This multi-level configuration can be performed by generating a plurality of states having different positive charge amounts in traps in the gate insulating film 21, and by using the multi-level configuration in the floating gate 11 together. Further, multi-value can be achieved. As a result, 3-bit or 4-bit conversion is possible.

(Embodiment 2) FIGS. 18 to 27 show a flash EEP according to another embodiment (Embodiment 2) of the present invention.
FIG. 3 is a diagram related to a ROM.

The flash memory 20 of the second embodiment is
As in the flash memory 20 of the first embodiment, the charge storage locations have an MNOS (MONOS) structure in which charges are stored in traps in the gate insulating film, and a FLOTOX structure in which charges are stored in the floating gate. .

That is, a trap for storing a positive charge or a negative charge exists near the interface between the thin gate oxide film and the gate nitride film (MNOS structure), so that the charge can be stored in the floating gate ( FLOTOX structure).

Further, by controlling the potential applied to the control gate and the like, the MNOS section and the FL
A plurality of states having different charge amounts can be respectively generated in the OTOX section, and the number of information stored per memory cell can be made larger than four values.

The flash memory according to the second embodiment has a structure suitable for an array configuration such as NOR, NAND, DiNOR, and the like. In these configurations, the memory cells have the same structure but different wirings.

Next, the structure of the flash memory 20 according to the second embodiment will be described with reference to FIG.
In the second embodiment, a NOR type configuration will be described.

The flash memory 20 according to the second embodiment includes:
For example, a semiconductor substrate 1 made of p-type silicon (Si)
Is formed.

In the surface portion of the active region of the semiconductor substrate 1,
A gate insulating film 21 made of a multilayer tunnel insulating film is formed. The gate insulating film 21 is composed of a thin gate oxide film 3, a gate nitride film 4, and a thin gate oxide film 5 sequentially stacked on the semiconductor substrate 1, and the oxide film is a silicon dioxide (SiO ₂ ) film formed by thermal oxidation. ing. Gate nitride film 4 is formed of a Si ₃ N ₄ film (nitride film). As an example of the thickness of each film, the thin gate oxide film 3 is about 3 nm, the gate nitride film 4 is about 10 nm,
The thickness of the thin gate oxide film 5 is about 5 nm, which is the same as in the first embodiment.

On the gate insulating film 21, the floating gate 11, the interlayer insulating film 14, the control gate 15, the insulating film 7
Are laminated.

The floating gate 11 is formed of polysilicon of about 100 nm. The interlayer insulating film 14 is composed of, for example, a SiN film / SiO ₂ film / SiN film / SiO ₂ film formed by a CVD method. Lowermost Si
O ₂ film is about 5 nm, other SiO ₂ films are about 3 nm, S
The iN film has a thickness of about 10 nm, and has a total thickness of about 30 nm. The control gate 15 is formed of, for example, a polycide film whose upper layer is formed of a silicide layer made of tungsten silicide (WSi) and a polysilicon film below this silicide layer. The silicide layer is, for example, 15
The thickness is about 0 nm, and the thickness of the polysilicon film is about 100 nm.
The insulating film 7 is formed of a SiO ₂ film or the like by a CVD method.

The gate insulating film 21, the floating gate 11,
The interlayer insulating film 14, the control gate 15, and the insulating film 7 have a laminated structure of the same rectangular pattern.

Further, sidewalls (insulating film spacers) 10 are provided at both ends of the gate insulating film 21, the floating gate 11, the interlayer insulating film 14, the control gate 15, and the insulating film 7. This insulating film spacer 10 is formed of, for example, a SiO ₂ film by a CVD method, and extends, for example, in the gate length direction. The extension length (overhang length) is, for example, about 0.3 nm.

Further, n-type semiconductor regions are formed in the surface layer portions of the semiconductor substrate 1 at both ends of the gate insulating film 21, respectively. One of the semiconductor regions is a source region 8 and the other is a drain region 9. Then, a surface portion directly below the gate insulating film 21 between the source region 8 and the drain region 9 becomes a channel portion.

A high impurity concentration n-type region is provided from the outer end portion of the insulating film spacer 10 to the outside to form wiring layers 18 and 19. One of the wiring layers 18 is in contact with the source region 8 to be a local source line 58, and the other wiring layer 19 is in contact with the drain region 9 to be a local bit line 59.

The source region 8 and the drain region 9
Are formed by implanting and diffusing impurities using the insulating film 7 as a mask, and the wiring layers 18 and 19 are formed at the time of forming the insulating film 7 and the insulating film spacers 10 at both ends thereof.
Since it is formed by impurity implantation and diffusion using as a mask, it is formed with high precision.

The surface of the semiconductor substrate 1, the insulating film 7 and the insulating film spacer 10 are covered with a memory cell protective insulating film 16. The memory cell protective insulating film 16 is covered with an interlayer insulating film 17. Further, the interlayer insulating film 1
A bit line (data) 35 made of metal wiring of Al or the like is provided on 7. This bit line 35 is connected to the wiring layer 1 through a conductor 36 filled in a contact hole.
9 (local bit line 59).

FIG. 19 shows a cell size (length f) of a memory cell.
_C , width h _C ) and the size (length f, width h) of the gate insulating film 21, the floating gate 11, and the like. That is,
The size of the trap region of the gate insulating film 21 or the charge storage region formed by the floating gate 11 is a length f and a width h. For example, the length f is about 0.6 nm and the width h is about 1.2 nm. The length f _C of the memory cell is about 1.2 nm,
The width h _C is about 1.6 nm.

The flash memory 20 of the second embodiment is
It has the same effect as the flash memory 20 of the first embodiment.

That is, in the flash memory 20 according to the second embodiment, the source region 8 and the drain region 9
a state where positive charges are stored in traps in the gate insulating film 21 by applying a predetermined potential to each of the control gates 15 of about nm, a state where negative charges are stored in traps in the gate insulating film 21, Gate insulating film 21
A state in which negative charges are stored in traps in the floating gate 11 and a state in which charges are not stored in the floating gate 11 and traps in the gate insulating film 21 are selectively generated to generate one memory cell (nonvolatile storage element). ) Can store 2-bit information.

Next, such a flash memory 20
Will be described with reference to FIGS. 20 to 27.

First, after preparing a semiconductor substrate 1 made of single crystal silicon, as shown in FIG.
A thin gate oxide film 3 is formed as a first gate insulating film constituting a tunnel insulating film for forming the gate insulating film 1. The thin gate oxide film 3 is formed on the surface of the semiconductor substrate 1 by a thermal oxidation SiO ₂ film. The thickness of the thin gate oxide film 3 is, for example, about 3 nm.

Next, a gate nitride film 4 made of a nitride film (Si ₃ N ₄ film) is formed on the first gate insulating film as a second gate insulating film forming film constituting a tunnel insulating film. As a result, an area (trap) near the interface where charges are accumulated is formed between the thin gate oxide film 3 and the gate nitride film 4.

If only the vicinity of the interface for accumulating charges is formed, only the thin gate oxide film 3 and the gate nitride film 4 may be used. However, in the second embodiment, in order to suppress the leakage of charges to the control gate, As shown in FIG. 21, a third gate insulating film forming film is formed. This film is a thin gate oxide film 5 made of a SiO ₂ film.

Thin gate oxide film 3 and gate nitride film 4
Is formed by a CVD apparatus, a plasma CVD apparatus, or the like.

For example, the thickness of the thin gate oxide film 3 is 3
The thickness of the gate nitride film 4 is about 10 nm, and the thickness of the thin gate oxide film 5 is about 5 nm.

Next, as shown in FIG. 22, a conductive film 11a for forming a floating gate and an interlayer insulating film 14 are formed on the second gate insulating film comprising the gate nitride film 4 and the thin gate oxide film 5 by a CVD apparatus. Are sequentially formed. The floating gate forming conductor film 11a is made of polysilicon and has a thickness of, for example, about 100 nm. The interlayer insulating film 14 is composed of, for example, a SiN film / SiO ₂ film / SiN film / SiO ₂ film. The lowest SiO ₂ film is 5
nm, the other SiO ₂ film is about 3 nm, and the SiN film is 1 nm.
It is about 0 nm, which is about 30 nm in total.

Next, as shown in FIG. 23, a control gate forming conductor film 15a and an insulating film 7 are formed on the interlayer insulating film 14 by a CVD apparatus. The control gate forming conductor film 15a is formed of, for example, a polycide film whose upper layer is formed of a silicide layer made of tungsten silicide (WSi) and a polysilicon film below this silicide layer. The silicide layer is, for example, 150 n
m, and the thickness of the polysilicon film is about 100 nm. The insulating film 7 is formed of a SiO ₂ film.

Next, as shown in FIG. 24, the insulating film 7 and the control gate forming conductor film 15a thereunder are formed.
Is etched to form a control gate 15 on which the insulating film 7 rides.

Next, as shown in FIG. 25, using the insulating film 7 and the control gate 15 as a mask, the lower interlayer insulating film 14, the floating gate forming conductor film 11a, the thin gate oxide film 5, the gate nitride film 4 , The thin gate oxide film 3 is sequentially etched to form an interlayer insulating film 14, a floating gate 11, a thin gate oxide film 5, a gate nitride film 4, a thin gate oxide film 3.
To form A gate insulating film 21 is formed by the thin gate oxide film 3, the gate nitride film 4, and the thin gate oxide film 5.

Next, as shown in FIG. 25, the gate insulating film 21 (thin gate oxide film 3, gate nitride film 4, thin gate oxide film 5), floating gate 11, interlayer insulating film 1
4, the n-type source region 8 is implanted (implanted) and diffused (annealed) with an n-type determining impurity into the active region surface layer of the semiconductor substrate 1 at both ends of the multilayer film including the control gate 15 and the insulating film 7. A drain region 9 is formed.

Next, as shown in FIG. 26, after forming an insulating film 24 made of a SiO ₂ film over the entire main surface of the semiconductor substrate 1, the insulating film 24 is anisotropically etched to form the gate insulating film 21. Then, a side wall (insulating film spacer) 10 is formed on the end face of the multilayer film composed of the insulating film 7 on the side of the source region 8 and the drain region 9 (see FIG. 27). The overhang length of the insulating film spacer 10 is, for example, 0.1 mm.
It is about 3 mm.

Next, the insulating film 7 and the insulating film spacer 1
0 is used as a mask, n-type determining impurity implantation (implantation) and diffusion (annealing) are performed on the main surface of the semiconductor substrate 1,
Wiring layers 18 and 19 made of a high concentration n-type diffusion layer are formed.

Thereafter, as shown in FIG. 18, a memory cell protection insulating film 16 is formed over the entire main surface of the semiconductor substrate 1.
Then, the interlayer insulating film 1 is formed on the memory cell protective insulating film 16.
7, a contact hole is formed, and a metal film for forming a wiring is formed and patterned, and a bit line 35 and a conductor 36 connecting the bit line 35 and the wiring layer 19 are formed on the interlayer insulating film 17. Are formed.

Although not shown, a final passivation film is provided on the main surface of the semiconductor substrate 1 to protect each circuit formed on the main surface of the semiconductor substrate 1. Each of the insulating films is made of a SiO ₂ film or Si
₃ N ₄ film or has its composite membrane.

Next, the semiconductor substrate 1 is cut vertically and horizontally to form a microcomputer chip.

The flash memory 20 according to the second embodiment has the same effects as the flash memory 20 according to the first embodiment.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

The present invention can be applied to a semiconductor integrated circuit device having at least a nonvolatile memory element.

[0158]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A state where positive charges are accumulated in traps in the gate insulating film by applying predetermined potentials to the source region, the drain region, and the control gate, respectively, and a negative charge is applied to traps in the gate insulating film. Can be selectively generated in a state in which negative charge is stored in traps and floating gates in the gate insulating film and a state in which no charge is stored in traps in the floating gate and gate insulating film. EEPROM 1
The number of information stored in the cell becomes four values, and two bits of information can be stored in one cell, so that the capacity of the memory can be increased.

(2) The four values can be obtained by applying different potentials, and the difference in charge accumulation amount in the same state is not used as in the prior art, so that the memory retention characteristics are improved and the read characteristics are improved.

(3) The floating gate is formed by the lower floating gate film and the upper floating gate film, and the area of the upper floating gate film is made larger than that of the lower floating gate film, and the capacitance between the control gate and the lower floating gate film is increased. Since the capacitance is larger than the capacitance between the film and the semiconductor substrate, the capacitance coupling ratio increases, the electric field of the floating gate can be increased, and the voltage applied to the control gate can be reduced. This allows
Low voltage of the element can be achieved.

(4) A plurality of states with different amounts of negative charges are generated in the floating gate, and a plurality of states with different amounts of positive charges are generated in the trap of the gate insulating film. It is possible to increase the number of values to be larger than the value, and to achieve a larger capacity or a smaller size of the flash EEPROM.

(5) In the manufacture of the flash EEPROM of the present invention, it is possible to manufacture the flash EEPROM at a low cost because no new special processing technique is required.

(6) In a microcomputer in which the flash EEPROM of the present invention is incorporated in a memory unit, the number of information stored per cell of the flash EEPROM constituting the memory unit is four or more, so that the capacity of the memory unit is increased. Can be achieved. Further, the reliability of the memory section is also high, and the reliability of the microcomputer can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a principle of an erase / write state of a flash memory according to the present invention.

FIG. 2 is a graph showing a quaternary information storage mode distribution per cell in a flash memory according to the present invention.

FIG. 3 is a cross-sectional view showing one cell portion of a flash memory according to an embodiment (Embodiment 1) of the present invention;

FIG. 4 is a schematic plan view showing a floating gate and a control gate in one cell portion of the flash memory according to the first embodiment.

FIG. 5 is a schematic plan view showing an internal configuration of a microcomputer chip in which the flash memory according to the first embodiment is incorporated.

FIG. 6 is an equivalent circuit diagram of an AND-type memory cell constituting a memory unit in the microcomputer chip of the first embodiment.

FIG. 7 is a cross-sectional view of a part of the main surface of the semiconductor substrate in which a thin gate oxide film is formed in the manufacture of the flash memory according to the first embodiment.

FIG. 8 is a cross-sectional view of a part where a thin gate oxide film and a gate nitride film are formed in the manufacture of the flash memory according to the first embodiment.

FIG. 9 is a cross-sectional view of a part of the lower floating gate film forming conductor film and the protective film formed in the manufacture of the flash memory according to the first embodiment;

FIG. 10 is a partial cross-sectional view in which a source region and a drain region are formed in the manufacture of the flash memory according to the first embodiment;

FIG. 11 is a cross-sectional view of a part of the flash memory according to the first embodiment in which an insulating film for forming a sidewall is formed.

FIG. 12 is a cross-sectional view of a part of a side wall formed in the manufacture of the flash memory according to the first embodiment;

FIG. 13 is a cross-sectional view of a part of the manufacturing process of the flash memory according to the first embodiment, in which wiring layers forming local bit lines and local source lines are formed;

FIG. 14 is a cross-sectional view of a part in which an upper floating gate film is formed to form a floating gate in the manufacture of the flash memory according to the first embodiment.

FIG. 15 is a cross-sectional view of a part of the flash memory according to the first embodiment in which an interlayer insulating film is formed.

FIG. 16 is a cross-sectional view of a portion where a control gate is formed in the manufacture of the flash memory according to the first embodiment.

FIG. 17 is a cross-sectional view of a part of the flash memory according to the first embodiment in which a memory cell protection insulating film is formed.

FIG. 18 is a cross-sectional view showing one cell portion of a flash memory according to another embodiment (Embodiment 2) of the present invention.

FIG. 19 is a schematic plan view showing a floating gate and a control gate of one cell portion of the flash memory according to the second embodiment.

FIG. 20 is a cross-sectional view of a part of a semiconductor substrate in which a thin gate oxide film is formed on a main surface in manufacturing the flash memory according to the second embodiment;

FIG. 21 is a cross-sectional view of a part of the thin film gate oxide film, the gate nitride film, and the thin film gate oxide film formed in the manufacture of the flash memory according to the first embodiment;

FIG. 22 is a cross-sectional view of a part in which a floating gate forming conductor film and an interlayer insulating film are formed on the thin gate oxide film in the manufacture of the flash memory according to the first embodiment.

FIG. 23 is a cross-sectional view of a part in which a control gate forming conductor film and an insulating film are formed on the interlayer insulating film in the manufacture of the flash memory of the first embodiment.

FIG. 24 is a cross-sectional view of a part of the flash memory according to the first embodiment in which an insulating film and a control gate are formed.

FIG. 25 is a cross-sectional view illustrating a method for manufacturing a flash memory according to the first embodiment.
FIG. 5 is a partial cross-sectional view in which an interlayer insulating film, a control gate, and an insulating film are selectively formed.

FIG. 26 is a cross-sectional view of a part of the main surface of the semiconductor substrate on which an insulating film for forming a side wall is formed in the manufacture of the flash memory according to the first embodiment;

FIG. 27 is a cross-sectional view of a part of the flash memory according to the first embodiment in which side walls are formed.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulating film 3 thin gate oxide film 4 gate nitride film 5 thin gate oxide film
6 ... Lower floating gate film, 6a ... Lower floating gate film forming conductor film, 8 ... Source region, 9 ... Drain region, 10 ... Side wall (insulating film spacer), 11 ... Floating gate, 12 ... Field insulating film, 13 ... Upper floating gate film, 14 ... interlayer insulating film, 15 ... control gate, 16 ... memory cell protection insulating film, 17 ... interlayer insulating film, 18, 19 ... wiring layer, 20 ... flash memory, 21 ... gate insulating film, 23 ... Protective film,
24 insulating film, 30 memory cell, 40 microcomputer chip, 41 control unit, 42 arithmetic unit, 43 ...
Memory unit, 44 input unit, 45 output unit, 46 electrode pad, 50 global bit line, 51 contact,
52: Block select transistor, 55: Global source line, 56: Contact, 57: Block select transistor, 58: Local bit line, 59: Local source line.

Claims (13)

[Claims] 1. A semiconductor integrated circuit device having a nonvolatile memory element, wherein the number of information stored in one cell of the nonvolatile memory element is three or more, wherein the information storage means stores a positive charge. A semiconductor integrated circuit device comprising: means for storing negative charges; and means for not storing charges. 2. A pair of source and drain regions formed in a surface portion of an active region of a semiconductor substrate, and electric charges are trapped near a film interface formed on a channel portion between the source and drain regions. A gate insulating film composed of a multilayer tunnel insulating film capable of accumulating electric charges, a floating gate formed on the gate insulating film and capable of accumulating electric charges, and a control gate formed on the floating gate via an interlayer insulating film. The means for accumulating positive charges accumulates positive charges in traps in the gate insulating film, and the means for accumulating negative charges accumulates or accumulates negative charges in traps in the gate insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein a negative charge is stored in a trap in said gate insulating film and in said floating gate. 3. A semiconductor integrated circuit device having a nonvolatile memory element, comprising: a pair of source and drain regions formed in a surface layer of an active region of a semiconductor substrate; A gate insulating film formed of a multilayer tunnel insulating film formed on the channel portion and capable of storing charges in traps near the film interface; a floating gate formed on the gate insulating film and capable of storing charges; And a control gate formed through an interlayer insulating film, and by applying a predetermined potential to each of the source region, the drain region, and the control gate, a positive charge is applied to a trap in the gate insulating film. , A state in which negative charges are stored in traps in the gate insulating film, a trap in the gate insulating film and A semiconductor having a nonvolatile memory element configured to selectively generate a state in which negative charge is stored in a floating gate and a state in which no charge is stored in traps in the floating gate and the gate insulating film. Integrated circuit device. 4. The semiconductor device according to claim 1, wherein the gate insulating film is formed of a silicon dioxide film and a nitride film, or a silicon dioxide film, a nitride film, and a silicon dioxide film formed sequentially on the active region. The semiconductor integrated circuit device according to claim 2 or 3. 5. The floating gate has a two-layer structure including a lower floating gate film and an upper floating gate film, wherein the lower floating gate film has the same pattern as the gate insulating film, and the upper floating gate film is a lower floating gate film. 5. The semiconductor device according to claim 2, wherein the area between the lower floating gate film and the control gate is larger than the capacitance between the lower floating gate film and the semiconductor substrate. 6. Item 13. The semiconductor integrated circuit device according to Item 1. 6. The semiconductor integrated circuit device according to claim 2, wherein a predetermined potential is applied to each of the source region, the drain region, and the control gate, so that the potential in the gate insulating film is reduced. A state where positive charges are stored in traps, a state where negative charges are stored in traps in the gate insulating film, a state where negative charges are stored in traps and floating gates in the gate insulating film, the floating gate and A semiconductor integrated circuit device having a configuration in which a state in which no charge is accumulated in a trap in the gate insulating film is selectively generated so that two bits of information can be stored in one nonvolatile memory element. 7. The semiconductor integrated circuit device according to claim 2, wherein a predetermined potential is applied to each of said source region, said drain region, and said control gate, whereby said gate insulating film has A state where positive charges are stored in traps, a state where negative charges are stored in traps in the gate insulating film, a state where negative charges are stored in traps and floating gates in the gate insulating film, the floating gate and A state in which no charge is accumulated in traps in the gate insulating film is selectively generated, and in the case of the floating gate, the potential of the control gate is changed to change a state in which the amount of negative charge is different in the floating gate into a plurality of states. A semiconductor integrated circuit device configured to generate the signal. 8. The semiconductor integrated circuit device according to claim 2, wherein a predetermined potential is applied to each of the source region, the drain region, and the control gate, so that the potential in the gate insulating film is reduced. A state where positive charges are stored in traps, a state where negative charges are stored in traps in the gate insulating film, a state where negative charges are stored in traps and floating gates in the gate insulating film, the floating gate and A structure in which a state in which no charge is accumulated in a trap in the gate insulating film is selectively generated, and a plurality of states having different negative charge amounts are generated in the floating gate, and a plurality of states are formed in the gate insulating film. A semiconductor integrated circuit device wherein a plurality of states having different amounts of positive charges are generated in the trap. 9. A pair of source and drain regions formed in a surface layer of an active region of a semiconductor substrate, and electric charges are trapped near a film interface formed on a channel portion between the source and drain regions. A gate insulating film composed of a multilayer tunnel insulating film capable of accumulating electric charges, a floating gate formed on the gate insulating film and capable of accumulating electric charges, and a control gate formed on the floating gate via an interlayer insulating film. A state in which positive electric charges are accumulated in traps in the gate insulating film by applying predetermined potentials to the source region, the drain region, and the control gate, respectively. A state where negative charges are stored in the trap and floating gate in the gate insulating film, And a method of manufacturing a semiconductor integrated circuit device having a nonvolatile memory element configured to selectively generate a state in which no charge is accumulated in a trap in the gate insulating film, wherein at least an active region is formed on a part of the surface. Preparing a semiconductor substrate having: a step of forming a first gate insulating film constituting a tunnel insulating film for forming the gate insulating film on the active region; and forming a first gate insulating film on the first gate insulating film. Forming a second gate insulating film constituting the tunnel insulating film to form a vicinity of an interface for accumulating charges, and forming a floating gate forming conductor film on the second gate insulating film. Forming an interlayer insulating film on the floating gate forming conductor film; forming a control gate forming conductive film on the interlayer insulating film; A step of forming an edge film; a step of etching the insulating film and the control gate forming conductor film thereunder to form a control gate on which an insulating film rides; and a step of using the insulating film and the control gate as a mask to form the interlayer. An insulating film, the floating gate forming conductor film, and the first and second gate insulating films are sequentially etched to form an interlayer insulating film, a floating gate, and a gate insulating film including the first and second gate insulating films. Performing the step of: forming the gate insulating film, the floating gate, the interlayer insulating film,
Forming a semiconductor region serving as a source region or a drain region in the active region on both ends of the multilayer film using the multilayer film formed of the control gate and the insulating film as a mask; Forming a side wall of the semiconductor integrated circuit device. 10. A pair of source and drain regions formed in a surface layer portion of an active region of a semiconductor substrate, and electric charges are trapped near a film interface formed on a channel portion between the source region and the drain region. A gate insulating film composed of a multilayer tunnel insulating film capable of accumulating electric charges, a floating gate formed on the gate insulating film and capable of accumulating electric charges, and a control gate formed on the floating gate via an interlayer insulating film. Wherein the floating gate has a two-layer structure comprising a lower floating gate film and an upper floating gate film, the lower floating gate film has the same pattern as the gate insulating film, and the upper floating gate film is The area between the control gate and the control gate is larger than the capacity between the lower floating gate film and the semiconductor substrate, the source region and the A state where positive electric charges are accumulated in traps in the gate insulating film, a state where negative electric charges are accumulated in traps in the gate insulating film, by applying a predetermined potential to the drain region and the control gate, respectively, A nonvolatile memory element configured to selectively generate a state in which negative charges are stored in traps in the gate insulating film and the floating gate and a state in which no charges are stored in the floating gate and traps in the gate insulating film. Forming a first gate insulating film constituting a tunnel insulating film for forming the gate insulating film on the active region; and forming the first gate on the active region. Forming a second gate insulating film forming film constituting a tunnel insulating film on the insulating film forming film and forming an area near an interface for accumulating charges; Forming a lower floating gate film forming conductor film on the second gate insulating film forming film; forming a protective film on the lower floating gate film forming conductor film; Conductor film for forming lower floating gate film and second conductive film
Forming the lower floating gate film and the second gate insulating film by etching the gate insulating film forming film in the same pattern, and masking the second gate insulating film, the lower floating gate film, and the gate mask. Forming a semiconductor region serving as a source region or a drain region in the active region on both ends of the lower floating gate film; and forming the source of the second gate insulating film, the lower floating gate film, and the gate mask. Forming a side wall on the end surface on the side of the region and the drain region; forming an upper floating gate film having a larger area than the lower floating gate film on the lower floating gate film after removing the gate mask; Forming a floating gate composed of a film and an upper floating gate film; forming an interlayer insulating film so as to cover the upper floating gate film And a step of forming a control gate on the interlayer insulating film. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein a third gate insulating film forming film is formed on the second gate insulating film forming film. . 12. The first gate insulating film forming film is formed of a silicon dioxide film, the second gate insulating film forming film is formed of a nitride film, and the third gate insulating film forming film is formed of silicon dioxide. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device is formed of a film. 13. A microcomputer having a control unit and a memory unit, wherein a part or all of the memory unit is constituted by the nonvolatile memory element according to any one of claims 1 to 8. And a microcomputer.