JP2004193598A - Nonvolatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new nonvolatile semiconductor memory device and its manufacturing method with respect to the miniaturization, high-performance and improved yielding of a virtual grounding memory cell using a three-layer polysilicon gate. <P>SOLUTION: Of end faces of a floating gate 115b, two end faces that are in directions vertical to a word line 117a and a channel are formed in the memory cell such that they partly get over the upper part of a third gate 109a through an insulating film 110a. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and more particularly, to a method for achieving high performance, high integration, and improved yield.

  Flash memory is excellent in portability and shock resistance, and can be erased electrically collectively. In recent years, flash memory has been rapidly demanded as a file for small portable information devices such as portable personal computers, digital still cameras, and video cameras. Is expanding. In order to expand the market, it is essential to reduce bit cost by reducing the memory cell area and to perform high-speed writing corresponding to short-time downloading of content. A memory cell method for realizing this is proposed. One of them is a virtual ground type memory cell using a three-layered polysilicon gate (for example, see Patent Document 1 or Patent Document 2). As shown in FIG. 15, the memory cell includes a well 202 in a silicon substrate 201, source / drain diffusion layer regions 203 and 203 'in the well, and a first polysilicon film formed on the well. The gate includes a floating gate 204 serving as a gate, a control gate 205 serving as a second gate, and a third gate 206 having at least one function of an erase gate and a gate controlling a split channel. Insulating films 207, 208, 209, 210, and 211 separate the polysilicon gates 204, 205, and 206, and the polysilicon gate and the well 202, respectively. The control gate 205 is connected in the row direction to form a word line. The source and drain diffusion layers 203 and 203 'are of a virtual ground type which shares the diffusion layers of adjacent memory cells, thereby reducing the pitch in the row direction. The third gate 206 is arranged perpendicular to the channel and perpendicular to the word line 205. At the time of writing, independent positive voltages are respectively applied to the word line 205, the drain 203, and the third gate 206, and the well 202 and the source 203 'are set to 0V. As a result, hot electrons are generated in the channel at the boundary between the third gate and the floating gate, and injected into the floating gate 204. Thereby, the threshold value of the memory cell increases. At the time of erasing, a positive voltage is applied to the third gate 206, a negative voltage is applied to the word line 205, and the source 203 ', the drain 203, and the well 202 are set to 0V. As a result, electrons are emitted from the floating gate 204 to the third gate 206, and the threshold value decreases. Alternatively, a negative voltage is applied to the word line 205, and the third gate 206, the source 203 ′, the drain 203, and the well 202 are set to 0V. As a result, electrons are emitted from the floating gate 204 to the well 202, and the threshold value decreases. By changing the threshold voltage of such a memory cell transistor, "0" or "1" of information is determined.

JP 2001-028428 A

JP-A-2001-085541

However, when trying to increase the capacity of the above-mentioned nonvolatile semiconductor memory device, a new problem has arisen.
The first is to reduce the internal operating voltage at the time of writing / erasing a memory cell, particularly at the time of erasing. Generally, in a flash memory, the following relational expression holds between the control gate voltage Vcg and the floating gate Vfg.

Vfg = Vcg · C2 / (C1 + C2 + Cag + Cfg) (1) where C1 is the capacitance of the insulating film (tunnel insulating film) between the floating gate and the Si substrate, and C2 is the insulating film between the floating gate and the control gate. (Poly-Si interlayer insulating film) Capacitance, Cag is the insulating film capacitance between the floating gate and the third gate, and Cfg is the insulating film capacitance between the floating gates existing under the adjacent word lines. C2 / (C1 + C2 + Cag + Cfg) is called the coupling ratio. In order to efficiently transmit the voltage applied to the control gate to the floating gate and perform writing / erasing with a lower internal voltage, it is necessary to increase the coupling ratio. To do so, (1) increase the capacitance C2 of the poly-Si interlayer insulating film, (2) increase the thickness between the third gate and the floating gate to reduce Cag, and (3) make the floating gate have a U-shaped cross section. Alternatively, it is important to reduce the cross-sectional area as a fin type and reduce the capacitance Cfg between the floating gate insulating films facing each other. To increase C2, it is necessary to increase the surface area of the floating gate. However, in the above-described known example, there is a problem that the surface area of the floating gate 204 is small and it is difficult to reduce the operating voltage. This problem is particularly important in an erasing operation in which a high voltage is applied to the insulating film 210 between the floating gate and the Si substrate, and electrons accumulated in the floating gate due to a tunnel phenomenon are released to the substrate. Also, in a so-called multi-value storage type flash memory in which two bits of data are stored in one memory cell, it is necessary to increase the difference between the memory cell threshold voltage in the written state and the erased state. In order to reduce the operation time, it is essential to improve the coupling ratio.

  The second is a reduction in variation in writing and miniaturization of the third gate. Among the above known examples, Patent Document 2 discusses various methods of forming a virtual ground type memory cell using a three-layer polysilicon gate. In the method of forming the floating gate 204 after forming the third gate 206, when the tunnel insulating film 210 is formed by thermal oxidation, the lower end of the previously formed third gate 206 is oxidized and the gate of the same portion is oxidized. There is a problem that a so-called gate bird's beak occurs in which the oxide film thickness is increased. This is because the gate oxide film at the lower end of the third gate is removed in the cleaning step when forming the tunnel insulating film, and the lower end of the third gate polysilicon film is oxidized. The extension of the gate bird's beak causes variation in the threshold voltage of the MOS transistor formed by the third gate, which causes a problem of increasing the variation in writing between memory cells. When the write variation between memory cells increases, in a multi-value storage type flash memory, the number of times of verifying whether or not a desired threshold state has been reached increases, and the write time of the chip increases. . Also, when the gate oxide film thickness of the third gate increases due to the extension of the gate bird's beak, the punch-through resistance of the MOS transistor formed by the third gate decreases, and it becomes difficult to reduce the gate length.

  Third is miniaturization of word lines. Generally, in a large-capacity flash memory, a memory cell is miniaturized by patterning a word line with a minimum processing dimension. For this purpose, it is necessary to secure a sufficient focus margin in a lithography process when patterning a word line. For this purpose, it is necessary to reduce the base step as much as possible.

  As described above, development of a new nonvolatile semiconductor memory device and a method of manufacturing the same to solve the problems related to miniaturization and higher performance of a virtual ground type memory cell using a three-layered polysilicon gate have been desired.

  An object of the present invention is to provide a new nonvolatile semiconductor memory device related to miniaturization, higher performance and improved yield of a virtual ground type memory cell using a three-layered polysilicon gate, and a method of manufacturing the same.

  The object is to form a well of a first conductivity type formed in a silicon substrate, a source / drain diffusion layer region of a second conductivity type formed in the well, and to be formed in a direction perpendicular to the diffusion layer region. A channel, a floating gate which is a first gate formed on the silicon substrate via an insulating film, a control gate which is a second gate formed via the floating gate and the insulating film, A memory cell having a word line formed by connecting the gates and a third gate formed through the silicon substrate, the floating gate, the control gate, and the insulating film, and having a different function from the floating gate and the control gate is included. In the nonvolatile semiconductor memory device, one of the two ends of the floating gate which is present in a direction perpendicular to the control gate rides on the upper part of the third gate via an insulating film. It is achieved by Uni arrangement.

The floating gate is disposed in a gap between the third gates, and does not completely fill the gap.
The floating gate has a surface area of A in the side wall in the third gate space, B in the bottom in the third gate space, C in the flat part in the upper part of the third gate, and D in the side wall in the upper part of the third gate. When you do
A> B + C + D
It is.
The third gate is a gate for controlling the split channel.
Alternatively, the third gate has both functions of an erase gate and a gate for controlling the split channel.
Preferably, the insulating film between the third gate and the well is the same as the gate insulating film in the peripheral circuit low-voltage system.
It is preferable that the material and the thickness of the third gate be the same as those of the peripheral circuit.

Further, the object is to form a first conductivity type well formed in a silicon substrate, a second conductivity type source / drain diffusion layer region formed in the well, and to be formed in a direction perpendicular to the diffusion layer region. A floating gate which is a first gate formed on the silicon substrate via an insulating film, a control gate which is a second gate formed via the floating gate and the insulating film, A memory cell having a word line formed by connecting the control gate and a third gate formed through the silicon substrate, the floating gate, the control gate and the insulating film, and having different functions from the floating gate and the control gate. In the nonvolatile semiconductor memory device which is one of the elements, a contact hole for connecting a word line and a metal wiring is arranged on a member having the same material and thickness as the third gate via an insulating film. Ri is achieved.
In this case, it is preferable that the member is a polysilicon film.

Further, the object is to form a well of a first conductivity type formed in a silicon substrate, a source / drain diffusion layer region of a second conductivity type formed in the well, and a vertical direction with respect to the diffusion layer region. A floating gate which is a first gate formed on the silicon substrate via an insulating film, a control gate which is a second gate formed via the floating gate and the insulating film, A memory cell having a word line formed by connecting the control gate and a third gate formed through the silicon substrate, the floating gate, the control gate and the insulating film, and having a different function from the floating gate and the control gate. In the nonvolatile semiconductor memory device which is one of the constituent elements, this is achieved by forming the second conductivity type impurity region in the silicon substrate below the binding portion that binds the plurality of third gates.
At this time, the source / drain diffusion layer region of the second conductivity type, the impurity region of the second conductivity type, and the diffusion layer region of the selection transistor for selecting the source / drain diffusion layer region of the second conductivity type are connected. .

  Further, the object is to form a well of a first conductivity type formed in a silicon substrate, a source / drain diffusion layer region of a second conductivity type formed in the well, and a vertical direction with respect to the diffusion layer region. A floating gate which is a first gate formed on the silicon substrate via an insulating film, a control gate which is a second gate formed via the floating gate and the insulating film, A memory cell having a word line formed by connecting the control gate and a third gate formed through the silicon substrate, the floating gate, the control gate and the insulating film, and having a different function from the floating gate and the control gate. In a method for manufacturing a nonvolatile semiconductor memory device as one of the constituent elements, a step of forming a plurality of wells on a semiconductor substrate and a step of forming first and second gate insulating films having different thicknesses on the wells. Forming a first polysilicon film on the first and second gate insulating films, patterning the first polysilicon film to form a line and space in a first direction, Forming a third gate insulating film in a space, forming a second polysilicon film, patterning the second polysilicon film in a first direction, forming a polysilicon interlayer insulating film, Forming a third polysilicon film, patterning the third polysilicon film and the second polysilicon in a second direction orthogonal to the first direction, and patterning the first polysilicon film again It is achieved by including a step.

At this time, the step of patterning the first polysilicon film to form a line and space in the first direction is performed only in the memory cell array portion.
At this time, it is preferable that the first and third gate insulating films have a larger thickness than the first gate insulating film.
After forming a line and space in the first direction by the first polysilicon film, a sidewall of an insulating film is formed on a side wall of the polysilicon film, and then a third gate oxide film is formed. Is preferred.

Further, the first polysilicon film is patterned such that the line portions are bound at the end of the line and space in the first direction.
In this case, a second conductivity type impurity is introduced below the binding portion of the first polysilicon film pattern before patterning.
At this time, the first direction patterning of the second polysilicon film is performed on the line of the first polysilicon film pattern.
Alternatively, the first direction patterning of the second polysilicon film is performed so as to be embedded in the space of the first polysilicon film pattern.

The effects obtained by typical aspects of the invention disclosed in the present application are as follows.
It is possible to reduce the memory cell area of the nonvolatile semiconductor memory device.
The operation speed of the nonvolatile semiconductor memory device can be improved.
The yield of the nonvolatile semiconductor memory device can be improved.

  Embodiments of the present invention will be specifically described below.

<Example 1>
First Embodiment A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration of a memory array in which flash memory cells are arranged in rows and columns, FIG. 2 is a plan view of the memory cell array, and FIG. 3 is a diagram showing AA ′, BB ′, and C− in FIG. 4 to 6 are cross-sectional views showing manufacturing steps of a memory cell and a peripheral circuit, and FIGS. 16 to 18 are cross-sectional views taken along the line E′-E of FIG. 5 shows a manufacturing process of the part.

  In FIG. 1, GDL represents a global data line, LDL represents a local data line, and the present memory cell array has a hierarchical data line structure. WL is a word line, and AG is a third gate (Assist Gate). ST is a gate wiring of the selection transistor, and SL is a common source line.

  As shown in FIGS. 3 and 6 (e), this memory cell includes a source / drain diffusion layer 113 in a p-type well 104 formed in a silicon substrate 101, a floating gate 115b serving as a first gate, and a second gate. , And a third gate 109a. The control gate 117a of each memory cell is connected in the row direction to form a word line. The floating gate 115b and the well 103 are in the gate insulating film 114, the third gate 109a and the well 103 are in the gate insulating film 108, the floating gate 115b and the third gate 109a are in the insulating film 114a, and the floating gate 115b and the word line 117a. Is separated from the insulating film 116a, and the third gate 109a and the word line 117a are separated from each other by the insulating film 110a. The source / drain diffusion layer 113 is arranged perpendicular to the word line 117a, and exists as a local source line and a local data line connecting the source / drain of the memory cell in the column direction. That is, the present non-volatile semiconductor storage device is constituted by a so-called contactless type array having no contact hole for each memory cell. A channel is formed in a direction perpendicular to the diffusion layer 113.

  Two end surfaces of the third gate 109a are opposed to two end surfaces of the floating gate 115b, which are perpendicular to the word line 117a and the channel, respectively, via the insulating film 114a. The floating gate 115b is arranged in a gap between the third gate 109a existing in a direction perpendicular to the word line 117a and the channel. Further, the floating gate 115b exists symmetrically with respect to the third gate 109a, and the third gate 109a exists symmetrically with respect to the floating gate 115b.

  In this embodiment, the pair of diffusion layers 113 forming the source / drain have an asymmetric positional relationship with respect to the floating gate pattern 115b, and one of the diffusion layers has an offset structure that does not overlap with the floating gate. I have. In addition, the third gate 109a and the diffusion layer 113 exist so that their respective parts overlap.

  Next, write, erase, and read operations will be described with reference to FIGS. 7 to 9 and Table 1.

  First, when writing the selected cell PSC1 of FIG. 7, a large positive voltage, for example, about 13.5 V, is applied to the word line WLm, and a low voltage of about 1.1 V is applied to the third gate AGo. Further, about 4.5 V is applied to the global data line GDLm, and this is supplied to the local data line LDLmR via the selection transistor ST1. The source LDLm + 1L and the p well are kept at 0V. As a result, a channel is formed in the well below the third gate 109a, hot electrons are generated in the channel at the end of the floating gate on the source side, and electrons are injected into the floating gate. That is, the third gate 109a functions as a gate for controlling a channel existing therebelow. According to this memory cell, generation and injection efficiency of hot electrons are increased as compared with the conventional NOR type flash memory, and writing can be performed in a region where the channel current is small. Therefore, with an internal power supply having the same current supply capability as a flash memory chip that performs writing by the tunnel phenomenon, parallel writing of a large number of memory cells on the order of kilobytes or more can be performed, and the write throughput can be improved.

  At the time of erasing, as shown in FIG. 8, a large negative voltage, for example, -18 V is applied to the word line WLm. At this time, the third gates AGe and AGo, all the source / drain diffusion layers DL, and the well are kept at 0V. Alternatively, a large negative voltage, for example, −16 V is applied to the word line WLm, and a positive voltage, for example, 2 V is applied to the well, and the third gates AGe and AGo and all the source / drain diffusion layers DL are kept at 0 V. As a result, a Fowler-Nordheim tunnel current flows from the floating gate to the well, and electrons accumulated in the floating gate are released.

  When reading the information of the cell RSC1 in FIG. 9, a voltage corresponding to the multi-valued threshold level is applied to the word line WLm, and a voltage of about 3.5 V is applied to the third gate AGo. Further, about 1 V is applied to the global data line GDLm, and this is supplied to the local data line LDLmR via the selection transistor ST1. The source LDLm + 1L and the p well are kept at 0V.

  The difference between the first embodiment and the prior art is that, as shown in FIG. 3A, of the end surfaces of the floating gate 115b, two end surfaces existing in a direction perpendicular to the word line 117a and the channel, respectively, are the second end surfaces. The point is that it is arranged so as to ride on the upper part of the three gates 109a via the insulating film 110a. The thickness of the floating gate 115b is set to a value that does not completely fill the third gate space. By adopting such a fin-shaped floating gate, the cross-sectional area of the cross section parallel to the word line is reduced, the insulating film capacitance between the floating gates facing between adjacent word lines is reduced, and the floating gate It is possible to increase the surface area. As a result, the word line pitch is reduced with miniaturization, and even if the distance between word lines is reduced, the coupling ratio of the memory cell is improved, and the internal operating voltage at the time of writing / erasing can be reduced. Further, since the capacitance of the insulating film between the floating gates facing each other between the adjacent word lines is small, the shift of the read threshold value caused by the difference between the threshold value of the adjacent bit in the written state or the erased state is reduced. It is possible to do. For this reason, in a multi-valued memory in which the threshold state is set to four or more levels and one or more memory cells store data of two bits or more, it is possible to compress each threshold distribution. As a result, the amount of change in the threshold value for writing / erasing can be reduced. As a result, the data retention characteristics can be improved by shortening the writing / erasing time, operating at a low voltage, and alleviating the neglected electric field.

At this time, as shown in FIG. 14, the floating gate 115b has a surface area of A on the side wall in the third gate space, B on the bottom in the third gate space, and a flat portion on the third gate space. When C and the side wall portion above the third gate are D,
A> B + C + D The relationship represented by the expression (2) is established. In order to reduce the size of the memory cell, it is necessary to reduce the line and space of the third gate. Under these conditions, B and C are made small and A or D is made large in order to increase the floating gate surface area. There is a need. The increase in D increases the capacitance of the insulating film between the floating gates facing between the adjacent word lines. Therefore, the area relationship expressed by the expression (2), in which the area A of the side wall portion in the third gate space is made large and the area of the other portions is made as small as possible, is achieved by miniaturization of the memory cell having the third gate and improvement of the operation speed. This is effective for improving data retention characteristics.

  After the formation of the third gate, a sidewall of the insulating film is formed on the side wall of the third gate before forming a floating gate insulating film (so-called tunnel insulating film). Thereby, gate bird's beak extending to the lower end of the third gate 109a is suppressed, and the gate length of the third gate can be reduced. In addition, variation in the threshold value of the MOS transistor formed by the third gate can be reduced, and variation in the writing speed between the memory cells can be suppressed. As a result, the number of times of verification at the time of chip writing is reduced, and the writing throughput can be improved.

  Further, the space formed at the time of the third gate patterning is arranged only in the memory mat where the floating gate is arranged. For this reason, the step of the base under the formation of the word line 117a is reduced, the focus margin of lithography at the time of patterning the word line is improved, and the pitch of the word line can be reduced.

Next, a method for manufacturing the present memory cell will be described with reference to FIGS.
The nonvolatile semiconductor memory device includes a memory cell region in which a plurality of memory cells for storing information are arranged in a matrix, and a peripheral circuit for selecting a bit for rewriting or reading or for generating a necessary voltage inside a chip. Is constituted by a peripheral circuit region in which a plurality of MOS transistors are arranged. The peripheral circuit area is divided into a low voltage section to which only a relatively small voltage such as a power supply voltage such as 3.3 V is applied and a high voltage section to which a high voltage required for rewriting such as 18 V is applied. As shown in FIG. 6E, both the low voltage section and the high voltage section are composed of a plurality of NMOS transistors and PMOS transistors formed on P wells 104b, 104c and N wells 105a, 105b. The memory cell is formed on the P well 104a. 4 to 6 are sectional views parallel to the word lines of the memory cells and perpendicular to the gate lines of the peripheral circuit MOS transistors.

The manufacturing method is as follows.
First, a shallow trench isolation region 102 for isolating a selection transistor and a peripheral circuit MOS transistor was formed on a p-type Si substrate 101 having a plane orientation of (100). Next, P-well regions 104a, 104b, 104c, N-well regions 105a, 105b, and an isolation region 103 between wells were formed by ion implantation (FIG. 4A). Next, after performing channel ion implantation (not shown in the figure) for adjusting the threshold value of the memory cell and the peripheral circuit MOS transistor, the diffusion layer (125 in FIG. 2) below the third gate unit (125 in FIG. 2) is formed. Ion implantation for forming 124) in FIG. 2 was performed. By this ion implantation, the diffusion layer wiring 113 of the memory cell and the diffusion layer 120a of the selection transistor can be electrically connected. (FIGS. 16 to 18). Next, a silicon oxide film 106 serving as a gate insulating film of a high voltage portion in the peripheral circuit region was formed to a thickness of about 23 nm by thermal oxidation (FIG. 4B). Thereafter, a photoresist pattern was formed, and the silicon oxide film 106 was left only in the high voltage portion of the peripheral circuit region by the wet etching method (the silicon oxide film 106 becomes 106a) (FIG. 4C). Then, after removing the photoresist pattern, thermal oxidation is performed by a thermal oxidation method to form a gate insulating film of the peripheral MOS transistor and an insulating film for separating the well from the third gate of the memory cell in the low voltage portion of the peripheral circuit region and the memory cell region. The film 108 was formed to a thickness of 9 nm. At this time, the thermal oxide film thickness of the high voltage portion in the peripheral circuit region became 25 nm (the silicon oxide film 106a became 106b) (FIG. 4 (d)). Thereafter, a polysilicon film 109 and a silicon oxide film 110 to be electrodes of the peripheral MOS transistor and the third gate of the memory cell were sequentially deposited (FIG. 4E). Subsequently, the silicon oxide film 110 and the polysilicon film 109 were patterned using lithography and dry etching techniques (the silicon oxide film 110 and the polysilicon film 109 become 110a, 110b and 109a, 109b, respectively). At this time, the pattern arrangement was such that the silicon oxide film 110 and the polysilicon film 109 in all regions other than the memory cells remained without being etched. All the spaces formed by this patterning have the same dimensions. This is because the word line polycide film formed in a later step is uniformly buried in the third gate space in the chip to form a flat step (FIG. 4 (f)).

  Next, a silicon oxide film 111 is deposited by a low pressure chemical vapor deposition method (FIG. 5A), and this is anisotropically etched and left only on the side wall of the third gate pattern 109 (the silicon oxide film 111 is 111a). (FIG. 5B). In this film, the third gate oxide film recedes in the cleaning process before the formation of the tunnel insulating film, and as a result, the gate bird's beak is elongated to increase the variation in writing between cells, and the short channel characteristic of the third gate MOS is reduced. It is a protective film for suppressing the reduction. The thickness of the silicon oxide film 111 is set such that the silicon oxide film 111 is completely removed in the cleaning step immediately before the formation of the tunnel insulating film, but the amount of overetching is extremely small. Thereafter, oblique ion implantation of arsenic and oblique ion implantation of boron were performed from different directions to form a source / drain diffusion layer region 113 and a punch-through stopper layer 112 of the memory cell (FIG. 5C). Here, the diffusion layer 124 under the third gate is connected to the source / drain diffusion layer region 113 of the memory cell (FIG. 17C). Next, an insulating film 114 for separating between the floating gate and the well and between the floating gate and the third gate was formed by a thermal oxidation method. The oxide film thickness on the well was 9 nm. At this time, an oxide film 114a of about 20 nm was grown on the third gate side wall (FIG. 5D). Thereafter, a polysilicon film 115 serving as a floating gate is deposited so that the third gate space is not completely filled (FIG. 5E), and is patterned in a direction parallel to the third gate by lithography and dry etching. (Polysilicon 115 becomes 115a). At this time, the end of the floating gate pattern 115a runs over the third gate 109a via the silicon oxide film 110a (FIG. 5F).

  Next, a stacked film of a silicon oxide film / silicon nitride film / silicon oxide film for separating a floating gate and a word line, a so-called ONO film 116, and a stacked film of polysilicon and a tungsten silicide film for a word line, a so-called polycide film 117, Silicon oxide films 118 were sequentially deposited. At this time, the thickness of the polysilicon film as a lower layer of the polycide film 117 was adjusted so that the memory cell space formed in FIG. 4F was completely filled and the surface of the polycide film 117 was almost flat (FIG. 6). (a)). Next, the silicon oxide film 118 and the polycide film 117 were patterned by a known lithography and dry etching technique with a minimum processing dimension to form word lines (the silicon oxide film 118 and the polycide film 117 become 118a and 117a). Further, the ONO film 116 and the polysilicon film pattern 116a were processed using the word line 117a as a mask to complete the floating gate (the ONO film 116 and the polysilicon film pattern 115a become 116a and 115b, respectively) (FIG. 6B). . Thereafter, the silicon oxide film 110b and the polysilicon film 109b in the peripheral circuit portion were patterned by lithography and dry etching techniques to form gate electrodes of the peripheral circuit MOS transistors (the silicon oxide film 110b and the polysilicon film 109b were 110c and 109c, respectively). (FIG. 6 (c)). This step also forms the gate of the selection transistor. Further, as shown in FIG. 2, the polysilicon film 109b and the silicon oxide film 110b are patterned outside the word line at the end of the memory mat. Next, after the low concentration source / drain regions 119a, 119b, 120a, and 120b of the peripheral circuit MOS transistor are formed by ion implantation (FIG. 6D), a side wall 121 of a silicon oxide film is formed. High-concentration source / drain regions 122a, 122b, 123a, and 123b of the circuit MOS transistor were formed (FIG. 6E). As a result, the diffusion layer 124 under the third gate, the source / drain diffusion layer region 113 of the memory cell, and the diffusion layer 120b of the selection transistor are connected, and the source / drain of the memory cell is connected to the diffusion layer of the selection transistor ( FIG. 18 (d)). Thereafter, although not shown in the figure, after depositing an interlayer insulating film, word lines, gate electrodes of peripheral MOS transistors, and contact holes (128 in FIG. 2) reaching the source / drain regions are formed in the interlayer insulating film. Next, a metal film was deposited and processed to form a first-layer metal wiring (129 in FIG. 2). Further, an interlayer insulating film was formed, and a through-hole was formed in the interlayer insulating film (130 in FIG. 2). Then, a second-layer metal wiring (131 in FIG. 2) mainly serving as a global bit line was formed. Further, an interlayer insulating film was deposited, and holes were formed. After that, a third-layer metal wiring was formed, and a passivation film was formed to complete a nonvolatile semiconductor memory device.

  FIG. 10 is a result showing the write / erase characteristics of the memory cell formed according to the present invention. FIG. 3 also shows the characteristics of the memory cell formed by the method disclosed in Patent Document 2 for comparison. The floating gate has a fin shape to reduce the cross-sectional area, reduce the insulating film capacitance between the opposing floating gates, and extend the end of the floating gate to the top of the third gate, resulting in an increase in the surface area. , The coupling ratio increased from 0.52 to 0.60. As a result, when writing and erasing were performed at the same voltage, the speed increased.

  When the threshold distribution after writing of the memory cell formed by this method was measured, the threshold difference between the fastest bit and the slowest bit was 2.1 V. On the other hand, in the prior art in which the sidewall was not formed on the third gate side wall, a large variation of 4.7 V was observed in the writing threshold distribution. Also, when the cut-off characteristic of the split gate MOS transistor constituted by the third gate was measured under the write operation condition, the cut-off was possible in the present invention even when the third gate length was 0.20 μm. In the prior art, punch-through occurred at 0.25 μm, and cut-off was difficult. In order to elucidate the difference between the writing variation and the cut-off characteristic between the present invention and the prior art described above, the cross-sectional shapes of both were observed with a scanning electron microscope. As shown in FIG. While the gate bird's beak extends at the lower end of the third gate, it has been clarified that the bird's beak is suppressed from elongating as shown in FIG. 11 (b) in the present invention.

  Further, in the memory cell formed according to the present invention, the disconnection and short circuit of the word line, which occurred at the end of the memory cell array, were greatly reduced as compared with the prior art, and the yield was improved. This is because, as a result of patterning the third gate serving as a base of the word line into a line and space only in the memory cell array portion, a contact hole region connecting the word line and the metal wiring is deposited on the third gate 109a and over the third gate 109a. This is because the height of the word line surface in the same region as in the memory cell is the same as that of the memory cell. As a result, the lithographic focus margin of the word line to be patterned with the minimum processing size was increased, and the yield was improved.

  According to the first embodiment, there is an effect that the write / erase speed of the nonvolatile semiconductor memory device can be increased. Further, there is an effect that the memory cell area can be reduced. Further, there is an effect that the yield can be improved.

<Example 2>
Next, a second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that after forming the third gate pattern 109a, the diffusion layer 113 of the memory cell is formed first, and then the sidewall spacer 111a is formed. The planar arrangement of the flash memory cells, the cross-sectional structure after completion, and the array structure are the same as in the first embodiment, and are omitted here.

  The method for manufacturing the memory cell is as follows. First, by the same method as shown in FIGS. 4A to 4F of the first embodiment, a shallow trench element isolation region 102, P well regions 104a, 104b, 104c, and N well regions 105a, 105b, a separation region 103 between wells, gate insulating films 106a and 108, a polysilicon film 109a to be a third gate electrode of the memory cell, and a silicon oxide film 110a were formed. At this time, as in the first embodiment, the pattern arrangement was such that the silicon oxide film 110 and the polysilicon film 109 in all regions other than the memory cells remained without being etched. All the spaces formed by the main patterning had the same dimensions (FIG. 12A).

Next, oblique ion implantation of arsenic and oblique ion implantation of boron were performed from different directions to form a source / drain diffusion layer region 113 and a punch-through stopper layer 112 of the memory cell (FIG. 12B). Next, a silicon oxide film 111 is deposited by a low pressure chemical vapor deposition method (FIG. 12C), and this is anisotropically etched and left only on the side wall of the third gate pattern 109 (the silicon oxide film 111a has a thickness of 111a). (FIG. 12D). In this film, the third gate oxide film recedes in the cleaning process before the formation of the tunnel insulating film, and as a result, the gate bird's beak is elongated to increase the variation in writing between cells, and the short channel characteristic of the third gate MOS is reduced. It is a protective film for suppressing the reduction. The thickness of the silicon oxide film 111 is completely removed in the cleaning step immediately before the formation of the tunnel insulating film, as in Example 1, but the amount of over-etching is set to be very small.
Thereafter, the steps after the formation of the gate insulating film 114 were performed by the same method as in FIGS. 5 (d) to 6 (e) of Example 1 to complete a memory cell (not shown).

  According to the present invention, as in the first embodiment, the writing / erasing speed can be improved as compared with the prior art. In addition, write variations between memory cells were reduced, and the write throughput of the chip was improved. Further, the cut-off characteristic of the split gate MOS transistor formed by the third gate is improved, and the gate length of the third gate can be reduced. Also, the yield was improved.

<Example 3>
Next, a third embodiment of the present invention will be described with reference to FIG. The difference from the second embodiment is that the tunnel insulating film is formed without completely removing the silicon oxide film sidewall formed on the side wall of the third gate pattern 109 in the cleaning process.

The method for manufacturing the memory cell is as follows. After the source / drain diffusion layer region 113 and the channel stopper layer 112 of the memory cell are formed by the same steps as in FIG. 12B of the second embodiment (FIG. 13A), silicon is formed by low pressure chemical vapor deposition. An oxide film 111 is deposited (FIG. 13B), and this is anisotropically etched to leave only on the side wall of the third gate pattern 109 (the silicon oxide film 111 becomes 111a) (FIG. 13C). . The thickness of this film was set to be thicker than in the first or second embodiment, and was set so as not to be removed in the cleaning step immediately before the formation of the tunnel insulating film. Like the first and second embodiments, the present silicon oxide film 111a prevents the gate bird's beak from elongating in the case of the tunnel insulating film, increasing the variation in writing between cells, and deteriorating the short-channel characteristics of the third gate MOS. In addition to being a protective film for suppressing, it also has a function of an insulating film for separating the third gate 109a and the floating gate 115b.
Next, after forming a tunnel insulating film 114 and a polysilicon film 115 serving as a floating gate (FIG. 13D), the steps after FIG. 5F of the first embodiment are performed to complete the memory cell (FIG. Zu).

According to the present invention, as in the case of the first embodiment or the second embodiment, the writing / erasing speed can be improved as compared with the prior art. In addition, write variations between memory cells were reduced, and the write throughput of the chip was improved. Further, the cut-off characteristic of the split gate MOS transistor formed by the third gate is improved, and the gate length of the third gate can be reduced. Also, the yield was improved.
In this embodiment, the source / drain diffusion layer 113 of the memory cell was formed and then the silicon oxide film sidewall 111a was formed in the same manner as in the second embodiment. However, as in the first embodiment, the source / drain diffusion layer 113 was formed. The same effect can be obtained even if the silicon oxide film side wall 111a is formed before.

  In the above-described embodiments, the floating gate is formed in a fin shape and rides on the third gate to increase the coupling ratio and improve the write / erase characteristics. Even with such a structure that is buried between the third gates, by forming a silicon oxide film sidewall on the third gate side wall, bird's beak extension at the lower end of the third gate is suppressed, It is possible to reduce the variation in writing between the memory cells and improve the writing throughput of the chip. Further, cut-off characteristics of the split gate MOS transistor formed by the third gate are improved, and the gate length of the third gate can be reduced. In addition, as a result of forming the third gate, which is a base of the word line, in a flat pattern except for the memory cell region, the step is reduced, and the lithography focus margin is improved. As a result, the disconnection and short-circuit of the word line, which have occurred at the end of the mat, are greatly reduced, and the yield is possible.

  In the above embodiment, the erasing operation was performed by applying a negative bias to the word line and setting the other terminals to 0 V to discharge the electrons accumulated in the floating gate to the well. The same effect can be obtained by emitting electrons from the floating gate to the third gate by setting the positive bias to the third gate and setting the other terminals to 0V.

  Also, in any of the embodiments, at least two states of electrons stored in the floating gate are required at the time of writing, but four or more states are formed, and one memory cell has two or more bits of data. May be applied to a so-called multi-valued storage for storing. In conventional multi-value storage, even if the amount of electrons stored in the floating gate is controlled with high precision to compress the threshold distribution at each level, the threshold state is the lowest as compared with binary storage. There is a problem that the difference between the high threshold states becomes large. For this reason, in the Fowler-Nordheim type rewriting, there has been a problem that the rewriting speed becomes slow or the writing voltage becomes high. According to the present invention, both writing and erasing can be performed at a low voltage of about 13 V, in other words, rewriting can be performed at a high speed, which is very effective for multi-value storage.

  As described above, the invention made by the inventor has been specifically described based on the second embodiment. However, the present invention is not limited to the above-described embodiment, and can be changed without departing from the gist of the invention. Of course. For example, the present invention may be applied to a one-chip microcomputer (semiconductor device) including a memory cell array unit having a nonvolatile semiconductor memory element.

FIG. 1 is a circuit diagram showing an array configuration of a flash memory cell according to a first embodiment of the present invention. FIG. 2 is a plan view of a main part of the flash memory. FIG. 2 is a sectional view of a main part of the flash memory. Sectional drawing for explaining the manufacturing method of the flash memory. Sectional drawing for explaining the manufacturing method of the flash memory. Sectional drawing for explaining the manufacturing method of the flash memory. FIG. 2 is a circuit diagram for explaining a write operation of the flash memory. FIG. 3 is a circuit diagram for explaining an erasing operation of the flash memory. FIG. 3 is a circuit diagram for explaining a read operation of the flash memory. FIG. 4 is a diagram showing a change in threshold value at the time of writing / erasing of the flash memory cell. FIG. 3 is a diagram showing a finished cross-sectional shape of the flash memory cell. Sectional drawing for demonstrating the manufacturing method of the flash memory which is Example 2 of this invention. Sectional drawing for explaining the manufacturing method of the flash memory which is Embodiment 3 of the present invention. FIG. 2 is a diagram showing a cross-sectional shape of a flash memory cell of the present invention. FIG. 9 is a cross-sectional view of a main part of a conventional flash memory. FIG. 4 is a cross-sectional view for explaining a method for manufacturing a memory cell to a select transistor (a cross section taken along the line E′-E in FIG. 2) in the flash memory of the present invention. FIG. 4 is a cross-sectional view for explaining a method for manufacturing a memory cell to a select transistor (a cross section taken along the line E′-E in FIG. 2) in the flash memory of the present invention. FIG. 4 is a cross-sectional view for explaining a method for manufacturing a memory cell to a select transistor (a cross section taken along the line E′-E in FIG. 2) in the flash memory of the present invention.

Explanation of reference numerals

101 silicon substrate, 102 element isolation region, 103, 104a, 104b, 105a, 105b well, 106, 106a, 106b gate insulating film, 107 photoresist, 108 gate insulating film, 109, 109a third A polysilicon film serving as a gate, 109b a polysilicon film, 109c a polysilicon film serving as a peripheral MOS gate, 110, 110a, 110b, 110c a silicon oxide film, 111, 111a a silicon oxide film, 112 a channel implantation region, Reference numeral 113 denotes a source / drain diffusion layer, 114 denotes a gate insulating film, 114a denotes an insulating film for separating a floating gate from a third gate, 115, 115a, 115b: a polysilicon film serving as a floating gate, 116, 116a ... Film (ONO film), 117, 117a: Polycide film to be word line , 118, 118a: silicon oxide film, 119a, 119b, 120a, 120b: source / drain diffusion layer, 121: silicon oxide film sidewall, 122a, 122b, 123a, 123b: source / drain diffusion layer, 124: memory cell Selection transistor connection diffusion layer region, 125: third gate binding portion, 126: polysilicon film, 127: selection transistor gate wiring, 128: contact hole, 129: word line extraction metal wiring, 130: through hole, 201: silicon Substrate, 202 ... well, 203, 203 '... source / drain diffusion layer, 204 floating gate polysilicon film, 205 ... word line polycide film, 206 ... third gate polysilicon film, 207 ... separate floating gate and word line Insulating film 208, the floating gate and the third gate Insulating film for separating, 209: insulating film for separating the third gate and the word line, 210: insulating film for separating the floating gate and the well, 211: insulating film for separating the third gate and the well, WL: word line, GDL ... global data line, LDL ... local data line, AG ... third gate, ST ... select transistor gate wiring, PSC1, PSC2 ... write select cell, ESC ... erase select cell, RSC1, RSC2 ... write select cell.

Claims (18)

Source and drain regions formed at predetermined intervals on one main surface side of the semiconductor substrate;
A channel region formed between the source region and the drain region;
A first gate provided on the drain-side channel region via a first gate insulating film;
A second gate provided on the source-side channel region with a side surface covered with a first insulating film via a second gate insulating film, and a second insulating film provided on an upper surface thereof;
The first gate is formed so as to cover the first gate insulating film, a side surface of the first insulating film, and a side surface of the second insulating film, and one end thereof is provided on a side surface of the second insulating film. A nonvolatile semiconductor memory device characterized by being used. Source and drain regions formed at predetermined intervals on one main surface side of the semiconductor substrate;
A channel region formed between the source region and the drain region;
A first gate provided on the drain-side channel region via a first gate insulating film;
A second gate provided on the source-side channel region with a side surface covered with a first insulating film via a second gate insulating film, and a second insulating film provided on an upper surface thereof;
The first gate is formed so as to cover the first gate insulating film, a side surface of the first insulating film, and a side surface of the second insulating film, and one end thereof is formed on an upper end surface of the second insulating film. A non-volatile semiconductor storage device, wherein   3. The nonvolatile memory according to claim 1, wherein the first gate is disposed in a gap region between both ends of the first gate, and is filled so as to form a recess. 4. Semiconductor memory device. The surface area of the first gate is A, the area of the side wall portion in the gap region of the second gate is B, the area of the bottom portion in the second gate gap region is B, and the area of the flat portion above the second gate is Is C, and D is the area of the side wall portion above the second gate.
A> B + C + D
3. The nonvolatile semiconductor memory device according to claim 1, wherein:   3. The non-volatile semiconductor memory device according to claim 1, wherein the second gate is a gate that controls a split channel formed in the semiconductor substrate via the second gate insulating film. .   3. The non-volatile semiconductor memory device according to claim 1, wherein the second gate has a gate function of controlling both an erase gate and a split channel. 3. The nonvolatile memory according to claim 1, wherein the second gate insulating film is the same as a gate insulating film of a MOS transistor forming a low voltage portion of a peripheral circuit formed on the semiconductor substrate. 4. Semiconductor storage device.   7. The material according to claim 1, wherein a constituent material and a film thickness of the second gate are the same as those of a gate of a MOS transistor forming a peripheral circuit formed on the semiconductor substrate. Nonvolatile semiconductor memory device. Source and drain regions formed at predetermined intervals on one main surface side of the semiconductor substrate;
A channel region formed between the source region and the drain region;
A first gate provided on the drain-side channel region via a first gate insulating film;
A second gate having a side surface covered with a first insulating film on a channel region on the source side via a second gate insulating film, and a second insulating film provided on an upper surface thereof;
A third gate provided via a third insulating film formed on the first gate;
A word line electrically connected to the third gate;
A contact hole provided through a third insulating film formed on the third gate;
A metal wiring connected via the word line and the contact hole,
The non-volatile semiconductor memory device according to claim 1, wherein the contact hole is placed on a member having the same material and thickness as a film forming the second gate.   10. The non-volatile semiconductor storage device according to claim 9, wherein said member is a polysilicon film. A first conductivity type well formed on one main surface side of the semiconductor substrate;
A second conductivity type source region and a drain region formed at predetermined intervals in the first conductivity type well;
A channel region formed between the source region and the drain region;
A first gate provided on the drain-side channel region via a first gate insulating film;
A second gate having a side surface covered with a first insulating film on a channel region on the source side via a second gate insulating film, and a second insulating film provided on an upper surface thereof;
A third gate provided via a third insulating film formed on the first gate,
A non-volatile semiconductor memory, wherein a binding region for binding a plurality of the second gates is provided on a region of the semiconductor substrate where an impurity diffusion layer having a second conductivity type is selectively formed. apparatus.   The impurity diffusion layer region having the second conductivity type is connected to a source region and a drain region of the second conductivity type and a diffusion layer region of a selection transistor that selects the source region and the drain region. The nonvolatile semiconductor memory device according to claim 11, wherein: In a method of manufacturing a nonvolatile semiconductor memory device having a memory cell array region and a peripheral circuit region,
Forming a well region on one main surface side of the semiconductor substrate;
Forming a first gate insulating film on the well region;
Forming a first silicon film on the first gate insulating film;
A line and space forming step of selectively patterning a film including the first silicon film and the first gate insulating film in the memory cell array region to form a line region and a space region in a first direction;
Forming a second gate insulating film in the space region, and forming a second silicon film on a region including the second gate insulating film;
Patterning the second silicon film so as to extend in a first direction;
Forming an interlayer insulating film on a region including the second silicon film, and forming a third silicon film on the interlayer insulating film;
Patterning the third silicon film and the second silicon film in a direction orthogonal to the first direction, and patterning the first silicon film again;
Nonvolatile semiconductor memory, wherein the second silicon film is patterned in a first direction, and the patterning is performed such that an end of the formed second silicon film pattern is arranged in the space region. Device manufacturing method. In a method of manufacturing a nonvolatile semiconductor memory device having a memory cell array region and a peripheral circuit region,
Forming a well region on one main surface side of the semiconductor substrate;
Forming a first gate insulating film on the well region;
Forming a first silicon film on the first gate insulating film;
A line and space forming step of selectively patterning a film including the first silicon film and the first gate insulating film in the memory cell array region to form a line region and a space region in a first direction;
Forming a second gate insulating film in the space region, and forming a second silicon film on a region including the second gate insulating film;
Patterning the second silicon film so as to extend in a first direction;
Forming an interlayer insulating film on a region including the second silicon film, and forming a third silicon film on the interlayer insulating film;
Patterning the third silicon film and the second silicon film in a direction orthogonal to the first direction, and patterning the first silicon film again;
Nonvolatile semiconductor memory, wherein the second silicon film is patterned in a first direction, and the patterning is performed such that an end of the formed second silicon film pattern is arranged on the line region. Device manufacturing method.   15. The method according to claim 13, wherein a thickness of the first gate insulating film is smaller than a thickness of the second gate insulating film.   The formation of the second gate insulating film is performed after forming the line and space and forming a sidewall made of an insulating film on a side wall of the first silicon film patterned in the memory cell array region. 15. The method for manufacturing a nonvolatile semiconductor memory device according to claim 13, wherein: 15. The non-volatile semiconductor memory device according to claim 13, wherein the first silicon film is patterned so that ends of the lines formed in the first direction are bound to form a bound portion. Production method. 15. The non-volatile memory according to claim 13, wherein an impurity of a conductivity type opposite to a conductivity type of the semiconductor substrate is introduced into the semiconductor region corresponding to a portion under the binding portion before forming the binding portion. A method for manufacturing a semiconductor memory device.

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