JP2989205B2 - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a memory cell having a floating gate and a control gate.

(Prior Art) In the field of EEPROM, an ultraviolet erasing type nonvolatile semiconductor memory device using a memory cell having a MOSFET structure having a floating gate is known.

EPROMs that can be electrically rewritten are EEP
Also known as ROM.

EEPROM memory cells that use a tunnel current to transfer charges between the floating gate and the substrate have two types: an FETMOS type in which a thin gate insulating film that allows a tunnel current to flow over the entire channel region and a floating gate is provided, There is a FLOTOX type in which a thin gate insulating film in which a tunnel current can flow only in a specific rewrite region is formed.

3 (a) and 3 (b) are a top view and a cross-sectional view, respectively, of a cell portion of a conventional ETMOSX type memory cell. An element isolation insulating film 2 is formed on a Si substrate 1, and a first gate insulating film 3 is provided in a region surrounded by the element isolation insulating film 2 via a first gate insulating film 3.
A floating gate 4 made of a layer polycrystalline silicon film is formed. The floating gate 4 is patterned so as to partially extend on the element isolation insulating film 2. A control gate 6 made of a second-layer polycrystalline silicon film is further formed on the floating gate 4 with a second gate insulating film 5 interposed therebetween. The selection gate 7 for connecting the memory cell to the bit line is formed simultaneously, for example, in the process of forming the floating gate 4 and the control gate 6. Impurities are ion-implanted using the control gate 6 and the selection gate 7 as a mask to become a source and a drain.
An n ⁺ type layer 8 is formed.

This memory cell stores information in a nonvolatile manner by associating different threshold values with “0” and “1” in accordance with the charged state of electrons in the floating gate. To inject electrons into the floating gate 4, apply a high voltage of about 20 V to the control gate 6,
FN tunneling from the substrate is used with the drain set to 0V. As a result, the threshold value of the memory cell moves in the positive direction. In order to emit electrons from the floating gate to the substrate, the control gate is set to 0 V, and a high voltage of about 20 V is applied to the drain, again causing FN tunneling. One of these operations is used for writing data, and the other is used for erasing data.

In the above operation, when a high voltage is applied to the control gate to inject electrons into the floating gate, it is necessary that the potential of the floating gate determined by the capacitance partial voltage is higher than a certain level in order to perform electron injection efficiently. is there. Therefore, it is desirable that the capacitance between the floating gate and the control gate is large, and a part of the floating gate is extended on the element isolation region so as to satisfy such a condition.

On the other hand, it is preferable that the high voltage applied to the control gate be as small as possible because the withstand voltage of the element is small and miniaturization can be achieved. However, in practice, the coupling capacitance between the floating gate and the control gate cannot be so large,
There is a problem that a high voltage as high as about 20 V is required, so that the withstand voltage of the element is sufficient, and the memory cell array cannot be sufficiently reduced in size.

(Problems to be Solved by the Invention) As described above, in the conventional nonvolatile semiconductor memory device having the floating gate and the control gate, it is possible to reduce the control voltage used for rewriting and also reduce the memory cell occupation area. There was a problem that it was difficult.

An object of the present invention is to provide a nonvolatile semiconductor memory device which solves such a problem and a method of manufacturing the same.

[Configuration of the invention]

(Means for Solving the Problems) According to the present invention, in order to achieve the above object, a floating gate and a control gate are stacked on a semiconductor substrate via a gate insulating film, and a part of the floating gate is formed on an element isolation region. MO to extend
A nonvolatile semiconductor memory device having an SFET structure, wherein a control gate has a portion opposed to a side surface of a floating gate via a gate insulating film, and a method for manufacturing the same.

(Function) According to the present invention, since the second control gate is formed on the side wall of the floating gate, the capacitance between the floating gate and the control gate can be increased without extending the floating gate to the element isolation region. It can be. Therefore, the voltage applied to the control gate at the time of rewriting can be made lower than before, and the element can be miniaturized. Further, the voltage at the time of rewriting can be reduced. Therefore, the design of the peripheral circuit is facilitated, and the withstand voltage and the area of the peripheral circuit can be reduced.

Embodiment 1 Hereinafter, a first embodiment of a nonvolatile memory device according to the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views of a cell showing an example of a manufacturing method according to the present invention for forming the EEPROM of the above embodiment.

First, an element isolation region is formed in a P-Si (100) substrate (11), and a first gate insulating film (12) is selectively formed in the element region, for example, at about 50 to 150 °, and then becomes a floating gate material. After the polycrystalline silicon film (13) is formed on the entire surface of about 3000 °, the polycrystalline silicon film is selectively etched on the element isolation region to perform one-way isolation of the floating gate.

Next, at least a second gate insulating film (1
3) After forming about 100 to 300 mm, a polycrystalline silicon film (15) serving as a control gate is formed about 4000 mm, and a SiN film (16) is formed thereon for about 1000 mm, for example. Thereafter, a resist pattern is selectively formed so as to selectively serve as a control gate. Using this resist pattern as a mask, the SiN film (1
6), polycrystalline silicon film (15), second gate insulating film (1
4), the polycrystalline silicon film (13) is sequentially etched.
After that, the resist pattern is removed by an O ₂ asher. Thereafter, a diffusion layer (21) is formed by ion implantation. Next, a third gate insulating film (17) of about 150 to 450 ° is formed at least on the side walls of the polycrystalline silicon films (13) and (15) by, for example, a thermal oxidation method. After that, the SiN film (18) is
A thickness of about 00 ° is formed (FIG. 1A).

Next, the SiN film (18) is etched by the RIE method to leave the SiN film (18) only on the side walls, and thereafter, the SiN films (16) and (18)
Using a mask as a mask, for example, thermal oxidation is performed to form a SiO ₂ film (1
9) is formed (FIG. 1 (b)).

Next, after forming a 2000mm SiO ₂ film on the entire surface by CVD method, RIE
The SiO ₂ film (20) is left at least on the side wall of the floating gate (13) by etching. At this time, SiO ₂
The film (17) and the SiN film (18) are also etched from the surface of the control gate (15), and a part of the side wall of the control gate (15) is also exposed (FIG. 1C).

Next, the SiO ₂ film (20) is removed with, for example, an NH ₄ F solution, and the SiN film (18) is further removed with, for example, a solution of phosphoric acid at about 180 ° C. Next, a polycrystalline silicon film (22) doped with, for example, phosphorus is formed on the entire surface to a thickness of about 2000 mm, and then an SiO ₂ film (17) is formed on at least the side wall of the floating gate (13) by RIE.
Is formed so as to be left behind. At this time, the control gate (1
5) is electrically connected to the polycrystalline silicon film (22) (FIG. 1 (d)).

Thereafter, a metal wiring process is performed by a normal process.

According to the nonvolatile memory device of this embodiment, since the control gate also faces the side surface of the floating gate, the coupling capacitance between the control gate and the floating gate can be made sufficiently large. For example, the increasing length of the periphery of the first layer of polycrystalline silicon is 6 μm (for an area of 1 μ × 3 μ).
If the thickness of the floating gate is 0.4 μm, the area of about 2.4 μm ² is increased by about 2.4 μm ² with respect to the plane area of about 4 μm ² (conventional example), which is about 1.6 times larger.

As a result, the high voltage applied to the control gate at the time of rewriting can be reduced from 17 V to 20 V in the above example. This requires a small area (for example, an LDDn ⁻ element isolation width) for the peripheral circuit or the like to have a high withstand voltage, and the whole can be miniaturized.

 Also, miniaturization of the cell becomes easy.

Next, a second embodiment of the nonvolatile memory device according to the present invention will be described with reference to FIGS. 2 (a) to 2 (d).

As described with reference to FIG. 1, after the floating gate (13), the second gate insulating film (14), and the control gate (15) are selectively formed, the SiO 2 having a thickness of about 100 to 250 ° is formed by, for example, a thermal oxidation method. _Two films (17) are formed. Thereafter, a molten film, for example, a photoresist film (30) is formed on the entire surface by spin coating, and heat treatment is performed so that the surface becomes flat (FIG. 2A).

Next, the photoresist film (30) is etched on the entire surface by RIE using O ₂ gas, and at least the control gate (15) is etched.
The surface of the upper SiO ₂ film (17) is exposed (FIG. 2 (b)).

Next, using a photoresist film (30) as a mask, for example, the SiO ₂ film (17) on the surface is removed by etching using an NH ₄ F solution to expose the surface of the control gate (15). Thereafter, the photoresist (30) is removed with an O ₂ asher.

Next, a polycrystalline silicon film (31) doped with, for example, phosphorus is formed on the entire surface at about 2000.degree. (FIG. 2 (c)).

Next, the entire surface is etched by RIE so that the polycrystalline silicon film (31) is left at least on the side wall of the floating gate (13) and is electrically connected to the control gate (15).

In this way, the polycrystalline silicon film (31) as the second control gate is formed more easily than in FIG.

 The present invention is not limited to the above embodiment.

For example, in the first embodiment, the diffusion layer (21) is formed after forming the cell, but may be formed by ion implantation after forming the polycrystalline silicon film (22). In the second embodiment, a film serving as a stopper during Poly-RIE may be formed on the control gate (15). For example, an SiO ₂ film, a silicide film, or the like is used. Alternatively, a p-Well or n-Well substrate may be used.

In place of the polycrystalline silicon film, metal, metal silicide, silicide, a combination thereof, or the like may be used. As a result, the resistance of the control gate can be reduced, the circuit speed can be increased, and the variation in access of cells far from the decoder in the memory cell array when the capacity is increased can be suppressed, and the speed can be increased.

It is also important because it leads to advantages such as a reduction in voltage drop in a long control gate wiring and improvement in writing and erasing characteristics.

In the embodiment, the case where one FETMOS type memory cell has one bit has been described. However, a plurality of memory cells are connected in series in a form sharing a source and a drain to form a NAND type cell, and each NAND cell unit The present invention is also effective in the case where the memory configuration is connected to the bit line. Further, the present invention is not limited to the EEPROM, and can be similarly applied to an ultraviolet-erasable EEPROM.
Further, the present invention can be similarly applied to a case where the memory cell is not a FETMOS type but a FLOTOX type.

〔The invention's effect〕

As described above, according to the present invention, the coupling capacitance between the floating gate and the control gate can be increased without increasing the occupied area, and high performance and high integration of the nonvolatile semiconductor memory can be achieved. .

[Brief description of the drawings]

1 (a) to 1 (d) are process sectional views showing a memory cell structure according to an embodiment of the present invention. FIG. 3 is a top view showing a conventional memory cell structure and its AA 'line. It is sectional drawing. 11,1 ... P-type Si substrate, 2 ... Field oxide film, 3,12 ... First gate oxide film, 4.13 ... Floating gate, 5,14 ... Second gate oxide film, 6,15 ... Control gate, 7 ... Select gate, 8,21 ... n ⁺ type layer, 16,18 ... SiN layer, 17,19,20 ... SiO ₂ layer, 22,31 ... Polycrystalline silicon film.

Claims (1)

(57) [Claims] A step of selectively forming an element isolation insulating film and an element forming region on a semiconductor substrate; and forming a first gate insulating film and a first conductive film serving as a floating gate on the element forming region. Sequentially forming a film, a second insulating film, and a second conductive film to be a first control gate; and using the mask material selectively formed on the second conductive film as a mask, A first conductive film, a second insulating film, and a second
Patterning the conductive film to form a floating gate and a first control gate; and forming a second control gate on the side wall of the floating gate via an insulating film. A method for manufacturing a nonvolatile semiconductor memory device.