JP3233998B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device using a memory cell array having a floating gate and a control gate, and more particularly to a nonvolatile semiconductor memory device having a divided floating gate.

[0002]

2. Description of the Related Art In recent years, electrically rewritable EEPROMs have attracted attention as nonvolatile semiconductor memory devices. An EEPROM memory cell that transfers a charge between a floating gate and a substrate by utilizing a tunnel current has an FETMOS type in which a thin gate insulating film through which a tunnel current can flow is formed on the entire surface of a channel region and a floating gate is provided. There is a FLOTOX type in which a thin gate insulating film through which a tunnel current can flow only in a specific rewriting region is formed.

FIGS. 11A and 11B are a top view and a sectional view, respectively, of a cell portion of a conventional FETMOS memory cell. An element isolation insulating film 2 is formed on a Si substrate 1, and a floating gate 4 made of a first-layer polycrystalline silicon is formed in a region surrounded by the element isolation insulating film 2 via a first gate insulating film 3. I have. The floating gate 4 is patterned so as to partially extend on the element isolation insulating film 2. A control gate 6 made of a second-layer polycrystalline silicon film is further formed on the floating gate 4 with a second gate insulating film 5 interposed therebetween. The selection gate 7 for connecting the memory cell to the bit line is formed simultaneously, for example, in the process of forming the floating gate 4 and the control gate 6. Impurities are ion-implanted using the control gate 6 and the select gate 7 as a mask, and n ⁺ becomes a source and a drain. A mold layer 8 is formed.

This memory cell stores information in a nonvolatile manner by associating different threshold values with "0" and "1" according to the charged state of electrons in the floating gate 4. To inject electrons into the floating gate 4, a high voltage of about 20V is applied to the control gate 6, the drain is set to 0V, and FN tunneling from the substrate is used. As a result, the threshold value of the memory cell moves in the positive direction. In order to emit electrons of the floating gate 4 to the substrate, the control gate is set to 0 V, and a high voltage of about 20 V is applied to the drain, again causing FN tunneling. One of these operations is used for writing data, and the other is used for erasing data.

On the actual pattern, in order to increase the integration density of the memory cells, the memory cell occupation area is reduced by making the drains of the two memory cells common and making the column line contact therewith. However, even in this case, a contact portion with the column line is required for every two common drains, and this contact portion occupies a large area of the cell.

On the other hand, recently, there has been proposed an EEPROM in which a plurality of memory cells are connected in series to constitute a NAND cell and the number of contacts can be greatly reduced. In this NAND cell, after the entire surface is erased (collectively erased) by injecting electrons into the floating gate all at once, writing is performed to discharge the electrons from the floating gate of the selected memory cell. When erasing the entire surface, the control gate is set to “H” level,
The drain is at "L" level. At the time of selective writing, writing is performed sequentially from the memory cell on the source side to the memory cell on the drain side. In this case, the selected memory cell and drain are set at "H" level, and the control gate is set at "L" level, whereby electrons are emitted from the floating gate to the substrate. Note that in a non-selected memory cell located on the drain side of the selected memory cell, the control gate has the same level as the drain so that the high potential for writing applied to the drain is transmitted to the selected memory cell. "H" level is applied.

In the layout of this NAND cell, the area occupied by the contact portion can be made as close as possible to zero by theoretically increasing the number of memory cells connected in series, and the control gate formed with the minimum processing size The minimum size of the memory cell is determined by the pitch and the bit line pitch. That is, assuming that the control gate pitch is L _C and the bit line pitch is L _B , the minimum occupied area per bit is L _C × L _B. However, L _C, there are naturally a limit to the miniaturization of L _B, in the conventional memory cell structure has a problem that limits the increase of the memory capacity comes while there.

[0008]

As described above, conventionally, in a nonvolatile semiconductor memory device having a floating gate and a control gate, only one bit of information can be stored in a memory cell defined by a control gate pitch and a bit line pitch. For,
There is a problem that it is difficult to further increase the memory capacity due to the limit of high integration of memory cells.

The present invention has been made in consideration of the above circumstances, and has as its object to store a plurality of bits of information in one memory cell, thereby increasing the memory capacity and increasing the degree of integration. An object of the present invention is to provide a nonvolatile semiconductor memory device that can be measured.

[0010]

The gist of the present invention is to store a plurality of bits of information in one memory cell by using a floating gate as a divided structure.

That is, the present invention relates to a nonvolatile semiconductor memory device having a memory cell in which a floating gate and a control gate are formed on a semiconductor substrate and writing / erasing is performed by transferring charges to and from the floating gate. The floating gate is divided in a channel length direction.

According to the present invention, a floating gate and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells, which are electrically rewritten by transferring charges between the floating gate and the substrate, are connected in series to form a NAND type memory cell. In a nonvolatile semiconductor memory device in which a memory cell unit is formed and the memory cell unit is arranged in a matrix, a floating gate of the memory cell is divided in a channel length direction.

Here, the number of divisions of the floating gate may be two or more. The number of information that can be stored changes depending on the number of divisions. For example, when the information is divided into two pieces, four pieces (two bits) are used.
Alternatively, three pieces of information can be stored. The length of each of the divided floating gates does not necessarily have to be the same, and the length may be appropriately changed according to a desired threshold value.

[0014]

According to the present invention, since the floating gate of a memory cell has a divided structure, independent writing can be performed on a plurality of floating gates of one memory cell. Therefore, multi-valued information can be stored and read in one memory cell defined by the minimum processing size. Therefore, the memory capacity can be doubled or more without changing the apparent memory cell occupation area,
A large increase in capacity is possible.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration and a charge storage state of a memory cell according to a first embodiment of the present invention.
The source and the source are separated from the surface layer of the p-type Si substrate 10 by a predetermined distance.
Drain region (n ⁺ Mold layers) 11 and 12 are formed. On the channel region between the source / drain regions 11 and 12, a floating gate 14 made of first-layer polycrystalline Si is formed via a first gate insulating film 13. This floating gate 14 is divided into two in the channel length direction. On the divided floating gates 14 (14a, 14b), a second layer polycrystalline Si is provided via a second gate insulating film 15.
Is formed.

In the device configured as described above, to erase data, electrons in the floating gate 14 are extracted or electrons are injected into the floating gate 14 at a time. Further, ultraviolet irradiation may be performed.

To perform data writing, electrons are selectively injected into the floating gates 14a and 14b on the source and drain sides by FN tunneling or hot electrons. After electrons are injected into all the floating gates 14, electrons may be selectively extracted from the source side and the drain side. By this writing, the accumulation state of the floating gate 14 can take four states as shown in FIGS.

Here, (a) shows floating gates 14a, 14
b shows a state in which no electrons are stored, (b) shows a state in which only the floating gate 14a stores electrons, (c) shows a state in which only the floating gate 14b stores electrons,
(D) shows a state where both the floating gates 14a and 14b are accumulating electrons.

In order to perform data reading, FIG.
Since the threshold voltage of the memory cell transistor shifts according to the four states shown in FIG. 2D as shown in FIG. 2A, quaternary reading can be performed by sensing the threshold voltage. Here, the lengths of the floating gates 14a and 14b do not necessarily need to be equal, and can be adjusted so that the current sensing margin is maximized. Further, as shown in FIG. 2B, the modes shown in FIGS. 1B and 1C may be treated as one mode and may be operated as a ternary mode.

As described above, according to the present embodiment, the floating gate 14 can be divided into two parts, and charges can be injected or discharged independently of each other. Shifts to four states. Therefore, quaternary data can be stored. That is, 1
Two bits of information can be stored in one memory cell. Therefore, the memory capacity can be increased without increasing the area occupied by the memory cells.

FIG. 3 shows a NAND type EEPROM according to the present invention.
This is a second embodiment applied to the present invention, and shows a layout of one NAND cell section of an EEPROM. FIG.
Shows a section taken along the line AA 'in FIG. 3, and FIG. 5 shows an equivalent circuit of the NAND cell.

As shown in FIG. 3, in this embodiment, four memory cells M1 to M4 and two selection transistors S1 and S4 are used.
2 and their sources and drains connected in series to form one N
This constitutes an AND cell. A memory array is formed by arranging a plurality of such NAND cells in a matrix. The drain of the NAND cell is connected to the bit line via the selection transistor S1. The source of the NAND cell is connected to the ground line via the selection transistor S2. In this embodiment, it constitutes one NAND cell of four memory cells, in general 2 ⁿ One NAND cell can be constituted by the memory cells.

The memory cell structure of this embodiment is basically the same as that of the first embodiment, as shown in the sectional view of FIG.
The memory cell M is formed by forming the floating gate 34, the control gate 36, and the source / drain region 32 on the Si substrate 30. Specifically, the floating gates 34 _1a , 34 _1b ,
~, 34 _4a, 34 _4b and the control gate 36 _{1-36 4} and to form a source and drain regions 32 of four memory cells M
1 to M4. Then, the memory cells M1 to M4
The four memory cells M1 to M4 are connected in series in such a manner that adjacent ones of the n-type diffusion layers 32, which are the source / drain, are shared with each other.

The drain side of the NAND cell, each of the source side selection gate 36 ₅ control gate 36 simultaneously with the formation of the memory cell, 36 ₆ are provided selection transistors S1, S2 are formed. The substrate on which the elements are formed is covered with a CVD oxide film 37, on which the bit lines 3 are formed.
8 are provided. The bit line 38 is in contact with the drain diffusion layer 32 at one end of the NAND cell. The control gates 36 of the NAND cells arranged in the row direction are commonly arranged as a control gate line. These control gate lines become word lines. The selection gates 36 ₅ and 36 ₆ are also respectively arranged as selection gate lines continuously in the row direction.

If one memory cell, for example, M1 is taken as an example, four states can be stored by independently writing to the floating gates 34 _1a and 34 _1b , and this can be stored in a current sense amplifier or A / A. By connecting to a D converter, 2-bit reading becomes possible.

The operation of the memory cell will be described in detail with reference to FIG. FIG. 6A shows one memory cell in a cross-sectional view perpendicular to the control gate 36. Floating gates 34a and 3
4b need not be the same size as shown in FIG. 6 (a). First, after the entire surface is erased by injecting electrons into the floating gates 34a and 34b at once,
When writing to 4a, by setting the source to "H" level and the control gate to "L" level, the electrons of the floating gate 34a are emitted to the substrate 30. When writing data on the floating gate 34b side, the drain may be set to "H" level and the source side may be set to "L" level. With this operation, four states can be stored in one memory cell.

FIG. 6B is an equivalent circuit diagram showing the memory cell of FIG. 6A. FIG. 6C shows the I _d -V _d characteristics of this memory cell. In such a read operation, the four states are determined by the O
The data can be read out in the form of an N resistor, and can be converted into 2-bit information by inputting it to a current sense amplifier and an A / D converter. At this time, it is necessary to control the initial value of Vth so that the MOS transistor becomes a normally-on type.

The above-mentioned writing and reading of the memory cells can be performed for each memory cell by controlling the floating gate 34, the control gate 36, the n-type diffusion layer 32 and the substrate potential. Therefore, one NAND cell unit can store 8-bit data.

As described above, according to the present embodiment, not only the high integration which is a feature of the NAND cell type can be realized, but also the floating gate has a divided structure. Data can be stored, and twice the memory capacity can be realized with the same occupied area as compared with the conventional NAND cell.

Next, the manufacturing process of the memory cell of the present invention will be described.
This will be described with reference to FIGS. In FIG. 7, first, as shown in FIG. 7A, a first gate oxide film 53 of 5 to 20 nm is formed on a p-type silicon substrate (or a p-type well formed on an n-type silicon substrate) 50 by thermal oxidation. .
Subsequently, for example, a silicon nitride film of 50 to 400 n is formed on the entire surface.
m, and is patterned by RIE or the like, and has a width of 0.1 mm.
A fence 61 of about 1 μm is formed. Thereafter, a first-layer polycrystalline silicon film 5 for forming a floating gate on the entire surface is formed.
4 is deposited 50 to 400 nm

Next, as shown in FIG. 7B, after the silicon film 54 is flattened by a polishing step using a silicon oxide fine particle suspension or the like, the polycrystalline silicon is selectively formed on the element isolation region. By etching the silicon film 54, the floating gate is separated in one direction. As a result, the polycrystalline silicon film 54 is separated into 54a and 54b by the fence 61.

Next, as shown in FIG. 7C, a second gate insulating film 55 is
After the formation of 0 nm, a second-layer polycrystalline silicon film 56 serving as a control gate is formed with a thickness of about 400 nm, and a SiN film 62 is formed thereon with a thickness of about 100 nm, for example. Thereafter, a resist pattern (not shown) is formed so as to selectively serve as a control gate, and the resist pattern is used as a mask to form SiN.
Film 62, polycrystalline silicon film 56, second gate insulating film 5
5. The polycrystalline silicon films 54a and 54b are sequentially etched. After that, the resist pattern is removed by an O ₂ asher.

Next, as shown in FIG.
A diffusion layer 51 serving as a source / drain is formed on the surface of the substrate 0 by ion implantation. Then, for example, by a thermal oxidation method,
An insulating film 63 of about 15 to 45 nm is formed on the side walls of the floating gate and the control gate. After that, the bit line and metal wiring steps are performed by the usual steps.

In the method of dividing and forming the floating gate, a process shown in FIG. 8 may be used without providing a fence. That is, as shown in FIG. 8A, after depositing a first gate oxide film 53 and a polycrystalline silicon film 54 serving as a floating gate, the resist 64 is patterned so that a space of about 0.1 μm is formed. I do. In this case, an edge-based phase shift mask and a negative resist may be used.

Next, as shown in FIG. 8B, first etching is performed using the resist pattern 64 as a mask. Next, as shown in FIG.
Is oxidized to fill the trench, a polycrystalline silicon film 56 serving as a control gate is deposited. Subsequently, the control gate and the floating gate are processed in the same steps as those in FIG.

The number of divisions of the floating gate is not limited to two and may be more. 3 floating gates
FIG. 9 shows an example in which the floating gate is divided, and FIG. 1 shows an example in which the floating gate is divided into four parts.
0 is shown.

In the case of three divisions, first, as shown in FIG. 9A, after forming a first gate oxide film 53 and a polycrystalline silicon film 54 on a Si substrate 50, a resist pattern 65 is formed. Next, as shown in FIG. 9B, the polycrystalline silicon film 54 is processed by the resist pattern 65,
After forming the insulating film 66 by oxidation or the like, a polycrystalline silicon film 54 'is further deposited by the same thickness as the polycrystalline silicon film 54.

Next, as shown in FIG. 9C, polishing is performed to flatten the surface. Next, as shown in FIG. 9D, a second gate oxide film 55 is formed, and thereafter, a control gate and a floating gate are formed as in the example of FIG.

In the case of four divisions, first, as shown in FIG.
0 nm is deposited, and a concave portion is formed by etching.
Here, after exposing the exposed substrate 50 to form a first gate oxide film 53, a polycrystalline silicon film 54 is deposited.
Next, as shown in FIG. 10B, after the entire surface of the polycrystalline silicon film 54 is etched to perform a step of leaving a side wall, the surface is oxidized to form an oxide film 72. Further, a polycrystalline silicon film 54 'is deposited thereon.

Next, as shown in FIG. 10C, after the entire surface of the polycrystalline silicon film 54 'is left by etching, the surface is oxidized to form an oxide film 73. As a result, four insulated floating gates were formed. Next, after the surface is flattened by polishing or the like, FIG.
As shown in FIG. 1D, a second gate oxide film 55 and a polycrystalline silicon film 56 serving as a control gate are deposited, and a control gate is formed in the same manner as in the example of FIG.

An important point in the above manufacturing process is that the minimum design rule is the control gate width, and the floating gate is divided and formed to a smaller size. This makes it possible to increase the memory capacity apparently without increasing the area occupied by the memory cells.

The present invention is not limited to the embodiments described above. The size ratio and the number of divisions of the floating gate are not limited to those shown in the embodiment, but can be changed as appropriate according to the specifications. Also, not limited to EEPROM,
The same can be applied to an EPROM of an ultraviolet erasing type. Furthermore, if the memory cell is not of the FETMOS type, FLOTO
The present invention can be similarly applied to the case of the X type. In addition, various modifications can be made without departing from the scope of the present invention.

[0044]

As described above, according to the present invention, by storing a plurality of bits of information in one memory cell by using a floating gate as a divided structure, the minimum defined by the control gate pitch and the bit line pitch is obtained. The memory capacity can be doubled or more without increasing the area occupied by the unit memory cell, and the performance and integration of the nonvolatile semiconductor memory device can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration and operation of an EEPROM according to a first embodiment;

FIG. 2 is a characteristic diagram for explaining the operation of the first embodiment;

FIG. 3 is a NAND cell type EEPROM according to a second embodiment;
The figure which shows the array structure of OM,

FIG. 4 is a sectional view taken along the line AA ′ of FIG. 3;

FIG. 5 is an equivalent circuit diagram of the NAND cell in FIG. 3;

FIG. 6 is a diagram for explaining the operation of the memory cell in FIG. 3;

FIG. 7 is a sectional view showing a memory cell manufacturing process.

FIG. 8 is a sectional view showing a memory cell manufacturing process.

FIG. 9 is a sectional view showing a manufacturing process of the memory cell;

FIG. 10 is a sectional view showing a memory cell manufacturing process.

11A and 11B are a plan view and a cross-sectional view illustrating a configuration of a conventional EEPROM.

[Explanation of symbols]

10, 30 ... p-type Si substrate, 11, 12, 32 ... source / drain regions (n ⁺ -Type layer), 13 ... first gate insulating _{film, 14,14a, 14b, 34,34 1a ~34} 4b ... floating gate, 15 ... second gate insulating film, 16,36,36 _{1-36 4} ... control gate, 36 _5, 36 ₆ ... selection gate.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takashi Yamada 1 Toshiba Research Institute, Komukai, Kawasaki-shi, Kanagawa Prefecture (56) References JP-A-3-141676 (JP, A) JP-A-3-141676 JP-A-63-274180 (JP, A) JP-A-62-94987 (JP, A) JP-A-61-50369 (JP, A) JP-A-56-126974 (JP, A) JP-A-3-290960 (JP) JP-A-4-14255 (JP, A) JP-A-4-336469 (JP, A) JP-A-5-82793 (JP, A) JP-A-4-76955 (JP, A) JP-A-3-283662 (JP, A) JP-A-3-1575 (JP, A) JP-A-2-3986 (JP, A) JP-A-1-262669 (JP, A) JP-A-1-212472 (JP, A A) JP-A-60-65576 (JP, A) JP-A-51-77184 (JP, A) JP-A-2-58349 (JP, A) U) JitsuHiraku Akira 56-32464 (JP, U) (58 ) investigated the field (Int.Cl. ^7, DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] A step of forming a first gate insulating film on a semiconductor substrate; a step of selectively forming a first insulating film on the first gate insulating film; Forming a first conductive film on the film; selectively removing the first conductive film to form a floating gate separated by the first insulating film; A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a second gate insulating film on a first insulating film; and forming a control gate on the second gate insulating film. Method. A step of forming a first gate insulating film on the semiconductor substrate; and a step of forming a floating gate over the entire surface of the first gate insulating film.
Forming a conductive film of the first conductive film, selectively forming a groove for separating the first conductive film, forming a second gate insulating film on the first conductive film, Forming a second conductive film to be a control gate on the second gate insulating film, and leaving the first conductive film with the groove interposed therebetween.
Selectively removing the first conductive film, the second gate insulating film, and the second conductive film. 3. A first gate insulating film is formed on a semiconductor substrate.
And forming a first conductive film on the first gate insulating film.
And selectively removing the first conductive film to form a first floating gate.
Forming an insulating film on side and top surfaces of the first floating gate.
And filling at least the space between the first floating gates.
Forming a second conductive film so as to cover the first conductive film, and forming the second conductive film formed on the first floating gate.
Removing the electrical film and the insulating film on the upper surface of the first floating gate;
Flattening, and forming a second gate on the first floating gate and the second conductive film.
Forming a gate insulating film and a third gate to be a control gate on the second gate insulating film.
Forming a conductive film; forming a conductive film on the side surface of the first floating gate via the insulating film;
At least a portion of the formed second conductive film remains
The third conductive film, the second gate insulating film,
Further comprising the step of selectively removing the second conductive film
A method for manufacturing a nonvolatile semiconductor memory device, characterized by: