JPH0677498A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide an EEPROM wherein it can store information of a plurality of bits in one memory cell, it can increase a memory capacity and its high integration can be achieved. CONSTITUTION:In an EEPROM, floating gates 34a, 34b and a control gate 36 are laminated and formed on a silicon substrate 30, four memory cells M which are electrically rewritten by transferring an electric charge between the floating gates 34a, 34b and the substrate 30 are connected in series, NAND- type memory cell units are formed and the memory cell units are arranged in a matrix manner. In the EEPROM, the floating gates 34a, 34b for memory cells M are divided into two in the direction of a channel length, and information of two bits is stored in one memory cell M.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device using a memory cell array having a floating gate and a control gate, and more particularly to a nonvolatile semiconductor memory device having a floating gate in a divided structure.

[0002]

2. Description of the Related Art In recent years, an electrically rewritable EEPROM has attracted attention as a nonvolatile semiconductor memory device. In an EEPROM memory cell that uses a tunnel current to transfer charges between a floating gate and a substrate, a FETMOS type in which a thin gate insulating film through which a tunnel current can flow is formed on the entire surface of a channel region to provide a floating gate, There is a FLOTOX type in which a thin gate insulating film in which a tunnel current can flow only in a specific rewriting region is formed.

11 (a) and 11 (b) are a top view and a sectional view of a cell portion of a conventional FETMOS memory cell, respectively. An element isolation insulating film 2 is formed on a Si substrate 1, and a floating gate 4 made of first-layer polycrystalline silicon is formed in a region surrounded by the element isolation insulating film 2 with a first gate insulating film 3 interposed therebetween. There is. The floating gate 4 is patterned so as to partially extend on the element isolation insulating film 2. A control gate 6 made of a second-layer polycrystalline silicon film is further stacked on the floating gate 4 with a second gate insulating film 5 interposed therebetween. The select gate 7 for connecting the memory cell to the bit line is formed at the same time in the process of forming the floating gate 4 and the control gate 6, for example. The control gate 6 and the impurity is ion-implanted source select gates 7 as a mask, a drain n ⁺ The mold layer 8 is formed.

This memory cell stores information in a nonvolatile manner by associating different thresholds with "0" and "1" depending on the charged state of electrons in the floating gate 4. In order to inject electrons into the floating gate 4, a high voltage of about 20V is applied to the control gate 6, the drain is set to 0V, and FN tunneling from the substrate is used. As a result, the threshold value of the memory cell moves in the positive direction. In order to discharge the electrons of the floating gate 4 to the substrate, the control gate is set to 0V and a high voltage of about 20V is applied to the drain, and F-N tunneling is also generated. One of these operations is used for writing data and the other is used for erasing data.

In the actual pattern, in order to increase the integration density of the memory cells, the drains of the two memory cells are made common so that the column line is in contact with the drains to reduce the occupied area of the memory cells. However, even in this case, a contact portion with the column line is required for each of the two common drains, and this contact portion occupies a large cell occupying area.

On the other hand, recently, an EEPROM has been proposed in which a plurality of memory cells are connected in series to form a NAND cell and a contact portion can be significantly reduced. In this NAND cell, the entire surface is erased (collectively erased) by injecting electrons into the floating gate at once, and then the writing is performed to release the electrons from the floating gate of the selected memory cell. When erasing the entire surface, set the control gate to "H" level,
The drain is at "L" level. At the time of selective writing, the memory cells on the source side are sequentially written to the memory cells on the drain side. In this case, the selected memory cell and drain are set to "H" level and the control gate is set to "L" level, whereby electrons are emitted from the floating gate to the substrate. In a non-selected memory cell located on the drain side of the selected memory cell, the control gate has the same level as the drain so that the high potential for writing applied to the drain is transmitted to the selected memory cell. "H" level is applied.

In the layout of this NAND cell, theoretically, by increasing the number of memory cells connected in series, it becomes possible to make the occupied area of the contact portion as close to zero as possible, and the control gate formed with the minimum processing size. The minimum size of the memory cell is determined by the pitch and the bit line pitch. That is, if the control gate pitch is L _C and the bit line pitch is L _B , the minimum value of the occupied area per bit is L _C × L _B. However, there is a limit to the miniaturization of L _C and L _B , and there is a problem that the conventional memory cell structure is reaching the limit of increasing the memory capacity.

[0008]

As described above, in a conventional nonvolatile semiconductor memory device having a floating gate and a control gate, only 1 bit of information can be stored in a memory cell defined by a control gate pitch and a bit line pitch. For,
There is a problem that it is difficult to further increase the memory capacity due to the limit of high integration of memory cells.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to store a plurality of bits of information in one memory cell, thereby increasing the memory capacity and increasing the degree of integration. A non-volatile semiconductor memory device that can be scaled is provided.

[0010]

The essence of the present invention is to store a plurality of bits of information in one memory cell with a floating gate as a divided structure.

That is, according to the present invention, in a nonvolatile semiconductor memory device having a memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate and writing / erasing is performed by transfer of electric charge to / from the floating gate. The floating gate is divided in the channel length direction.

Further, according to the present invention, a floating gate and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells electrically rewritten by exchanging charges between the floating gate and the substrate are connected in series to form a NAND type memory cell. In a nonvolatile semiconductor memory device in which a memory cell unit is formed and the memory cell unit is arranged in a matrix, the floating gate of the memory cell is divided in the channel length direction.

Here, the number of divisions of the floating gate may be two or more. The number of pieces of information that can be stored changes depending on the number of divisions, but if it is divided into two, for example, four (2 bits)
Or three pieces of information can be stored. The lengths of the divided floating gates do not necessarily have to be the same, and the lengths may be appropriately changed according to a desired threshold value.

[0014]

According to the present invention, since the floating gate of the memory cell has a divided structure, independent writing can be performed on a plurality of floating gates of one memory cell. Therefore, multivalued information can be stored and read in one memory cell defined by the minimum processing size. Therefore, the memory capacity can be doubled or more without changing the apparent memory cell occupation area.
A large capacity can be achieved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a schematic structure of a memory cell and a charge storage state according to a first embodiment of the present invention.
The p-type Si substrate 10 is provided on the surface layer with a predetermined distance from the source.
Drain region (n ⁺ Mold layers) 11 and 12 are formed. A floating gate 14 made of first-layer polycrystalline Si is formed on the channel region between the source / drain regions 11 and 12 with a first gate insulating film 13 interposed therebetween. The floating gate 14 is divided into two in the channel length direction. On the divided floating gates 14 (14a, 14b), the second-layer polycrystalline Si is interposed via the second gate insulating film 15.
A control gate 16 is formed.

In the device thus constructed, in order to erase data, the electrons in the floating gate 14 are extracted or the electrons are collectively injected into the floating gate 14. Further, ultraviolet rays may be irradiated.

In order to write data, electrons are selectively injected into the floating gates 14a and 14b on the source side and the drain side by FN tunneling or hot electrons. Further, after injecting electrons into all the floating gates 14, electrons may be selectively extracted from the source side and the drain side. By this writing, as shown in FIGS. 1A to 1D, the floating gate 14 can have four storage states.

Here, (a) is the floating gates 14a, 14
In a state in which none of b stores electrons, (b) shows a state in which only the floating gate 14a stores electrons, and (c) shows a state in which only the floating gate 14b stores electrons.
(D) shows a state in which the floating gates 14a and 14b both store electrons.

In order to read data, the data shown in FIG.
Since the threshold voltage of the memory cell transistor shifts as shown in FIG. 2A in accordance with the four states shown in FIG. 2D, four values can be read by current sensing. Here, the lengths of the floating gates 14a and 14b do not necessarily have to be equal and can be adjusted so that the current sensing margin is maximized. Further, as shown in FIG. 2 (b), FIGS. 1 (b) and 1 (c) may be treated as one mode and operated in three values.

As described above, according to the present embodiment, since the floating gate 14 can be divided into two and the charges can be independently injected or discharged into each of them, the threshold value can be changed depending on the storage state of the floating gate 14. Shift to four states. Therefore, four-valued data can be stored. That is, 1
Two memory cells can store 2-bit information. Therefore, the memory capacity can be increased without increasing the occupied area of the memory cell.

FIG. 3 shows a NAND type EEPROM according to the present invention.
It is a second embodiment applied to, and shows a layout of one NAND cell portion of the EEPROM. Also, FIG.
Shows a cross section taken along the line AA 'in FIG. 3, and FIG. 5 shows an equivalent circuit of a NAND cell.

As shown in FIG. 3, in this embodiment, four memory cells M1 to M4 and two select transistors S1 and S are provided.
2 are connected in series with their source and drain to form a single N
It constitutes an AND cell. A plurality of such NAND cells are arranged in a matrix to form a memory array. The drain of the NAND cell is connected to the bit line via the selection transistor S1. The source of the NAND cell is connected to the ground line via the selection transistor S2. In this embodiment, four memory cells form one NAND cell, but generally 2 ⁿ One NAND cell can be composed of the individual memory cells.

The memory cell structure of this embodiment is basically the same as that of the first embodiment as shown in the sectional view of FIG.
A memory cell M is formed by forming a floating gate 34, a control gate 36, and a source / drain region 32 on a Si substrate 30. Specifically, the floating gates 34 _1a , 34 _1b ,
~, 34 _4a, 34 _4b and the control gate 36 _{1-36 4} and to form a source and drain regions 32 of four memory cells M
1 to M4 are configured. Then, the memory cells M1 to M4
The four memory cells M1 to M4 are connected in series in such a manner that adjacent n-type diffusion layers 32, which are the source and drain, are shared with each other.

Select gates 36 ₅ and 36 ₆ formed at the same time as the control gate 36 of the memory cell are provided on the drain side and the source side of the NAND cell to form select transistors S1 and S2. The substrate on which the elements are formed is covered with the CVD oxide film 37, and the bit line 3 is formed on the substrate.
8 are provided. The bit line 38 is in contact with the drain side diffusion layer 32 at one end of the NAND cell. The control gates 36 of the NAND cells arranged in the row direction are commonly arranged as a control gate line. These control gate lines become word lines. The select gates 36 ₅ and 36 ₆ are also arranged continuously in the row direction as select gate lines.

Taking one memory cell, for example M1, as an example, four states can be stored by independently writing to the floating gates 34 _1a and 34 _1b , which can be stored in a current sense amplifier or A / By connecting to the D converter, 2-bit reading becomes possible.

The operation of this memory cell will be described in detail with reference to FIG. FIG. 6A shows one memory cell in a sectional view perpendicular to the control gate 36. Floating gates 34a and 3
4b need not be the same size as shown in FIG. 6 (a). First, after erasing the entire surface by collectively injecting electrons into the floating gates 34a and 34b, for example, the floating gate 3
When writing to 4a, the source is set to "H" level and the control gate is set to "L" level, so that the electrons in the floating gate 34a are emitted to the substrate 30. When writing to the floating gate 34b side, the drain may be set to "H" level and the source side may be set to "L" level. By this operation, four states can be stored in one memory cell.

FIG. 6B is an equivalent circuit diagram showing the memory cell of FIG. 6A. FIG. 6C shows the I _d -V _d characteristic of this memory cell. Thus, in reading, the four states are O of the MOS transistor.
It is possible to read in the form of N resistance, and by inputting this to a current sense type amplifier and A / D converter, it can be converted into 2-bit information. At this time, it is necessary to control the initial value of Vth so that the MOS transistor is of a normally-on type.

Writing and reading of the above memory cell can be performed for each memory cell by controlling the floating gate 34, the control gate 36, the n-type diffusion layer 32 and the substrate potential. Therefore, one NAND cell unit can store 8-bit data.

As described above, according to the present embodiment, not only the high integration, which is a characteristic of the NAND cell type, can be realized, but the floating gate has a divided structure. It is possible to store data, and it is possible to realize twice the memory capacity in the same occupying area as the conventional NAND cell.

Next, the manufacturing process of the memory cell of the present invention will be described.
This will be described with reference to FIGS. In FIG. 7, first, as shown in (a), a first gate oxide film 53 of 5 to 20 nm is formed on a p-type silicon substrate (or a p-type well formed on an n-type silicon substrate) 50 by thermal oxidation. .
Then, for example, a silicon nitride film having a thickness of 50 to 400 n is formed on the entire surface.
m, is deposited and patterned by RIE or the like, and has a width of 0.
A fence 61 of about 1 μm is formed. Then, the first-layer polycrystalline silicon film 5 for forming a floating gate on the entire surface
4 is deposited to 50 to 400 nm

Next, as shown in FIG. 7B, the silicon film 54 is flattened by using a polishing process using a silicon oxide fine particle suspension, and then, a polycrystalline film is selectively formed on the element isolation region. The floating gate is isolated in one direction by etching the silicon film 54. As a result, the polycrystalline silicon film 54 is separated by the fence 61 into 54a and 54b.

Next, as shown in FIG. 7C, a second gate insulating film 55 is formed on the polycrystalline silicon film 54 by about 10 to 3.
After the thickness of 0 nm is formed, the second-layer polycrystalline silicon film 56 to be the control gate is formed to have a thickness of approximately 400 nm, and the SiN film 62 is formed to have a thickness of approximately 100 nm, for example. Then, a resist pattern (not shown) is formed so as to selectively serve as a control gate, and the resist pattern is used as a mask for SiN.
Film 62, polycrystalline silicon film 56, second gate insulating film 5
5. The polycrystalline silicon films 54a and 54b are sequentially etched. After that, the resist pattern is removed by an O ₂ asher.

Then, as shown in FIG. 7D, the substrate 5
A diffusion layer 51 serving as a source / drain is formed on the surface of 0 by ion implantation. Then, for example, by the thermal oxidation method,
An insulating film 63 of about 15 to 45 nm is formed on the side walls of the floating gate and control gate. After that, the steps of bit line and metal wiring are performed by the usual steps.

In the method of separately forming the floating gate, the steps shown in FIG. 8 may be used without providing a fence. That is, as shown in FIG. 8A, after the first gate oxide film 53 and the polycrystalline silicon film 54 to be the floating gate are deposited, patterning of the resist 64 is performed so that a space of about 0.1 μm is formed. I do. At this time, an edge-using phase shift mask and a negative resist may be used.

Next, as shown in FIG. 8B, first etching is performed using the resist pattern 64 as a mask. Next, as shown in FIG. 8C, the polycrystalline silicon film 54
Is oxidized to fill the groove, a polycrystalline silicon film 56 to be a control gate is deposited. Subsequently, the control gate and the floating gate are processed in the same step as FIG. 7.

The number of divisions of the floating gate is not limited to two, but may be more. 3 floating gates
FIG. 9 shows an example in which the floating gate is divided, and FIG. 1 shows an example in which the floating gate is divided into four.
It shows in 0.

In the case of three divisions, first, as shown in FIG. 9A, a first gate oxide film 53 and a polycrystalline silicon film 54 are formed on a Si substrate 50, and then a resist pattern 65 is formed. Next, as shown in FIG. 9B, the polycrystalline silicon film 54 is processed by the resist pattern 65,
After forming the insulating film 66 by oxidation or the like, a polycrystalline silicon film 54 ′ is further deposited by the same thickness as the polycrystalline silicon film 54.

Then, as shown in FIG. 9C, polishing is performed to planarize the surface. Next, as shown in FIG. 9D, a second gate oxide film 55 is formed, and thereafter, the control gate and the floating gate are formed as in the example of FIG.

In the case of four divisions, first, as shown in FIG. 10A, the CVD oxide film 71 is formed on the substrate 50 by 500 to 100.
0 nm is deposited and a recess is formed by etching.
Here, the exposed substrate 50 is oxidized to form a first gate oxide film 53, and then a polycrystalline silicon film 54 is deposited.
Next, as shown in FIG. 10B, the polycrystalline silicon film 54 is entirely etched to leave sidewalls, and then the surface is oxidized to form an oxide film 72. Further, a polycrystalline silicon film 54 'is deposited on this.

Next, as shown in FIG. 10C, after the sidewall of the polycrystalline silicon film 54 'is left by etching, the surface is oxidized to form an oxide film 73. This formed four insulated floating gates. Then, after the surface is flattened by polishing or the like, as shown in FIG.
As shown in FIG. 0 (d), the second gate oxide film 55 and the polycrystalline silicon film 56 to be the control gate are deposited, and the control gate is formed in the same manner as in the example of FIG.

An important point in the above manufacturing process is that the minimum design rule is the control gate width, and the floating gate is divided into smaller sizes. As a result, the memory capacity can be increased without apparently increasing the occupied area of the memory cell.

The present invention is not limited to the above embodiments. The ratio of the size of the floating gate and the number of divisions are not limited to those shown in the embodiment, and can be appropriately changed according to the specifications. Also, not limited to the EEPROM,
It is similarly applicable to an ultraviolet erasing type EPROM. Furthermore, the memory cell is not a FETMOS type,
The present invention can be similarly applied to the case of the X type. In addition, various modifications can be made without departing from the scope of the present invention.

[0044]

As described above, according to the present invention, by storing a plurality of bits of information in one memory cell with a floating gate as a divided structure, the minimum defined by the control gate pitch and the bit line pitch is obtained. The memory capacity can be doubled or more without increasing the occupied area of the unit memory cell, and high performance and high integration of the nonvolatile semiconductor memory device can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration and an operation of an EEPROM according to a first embodiment,

FIG. 2 is a characteristic diagram for explaining the operation of the first embodiment,

FIG. 3 is a NAND cell type EEPR according to a second embodiment.
The figure which shows the array structure of OM,

FIG. 4 is a sectional view taken along the line AA ′ of FIG.

5 is an equivalent circuit diagram of the NAND cell of FIG.

FIG. 6 is a diagram for explaining the operation of the memory cell of FIG. 3;

FIG. 7 is a cross-sectional view showing the manufacturing process of the memory cell,

FIG. 8 is a sectional view showing a manufacturing process of the memory cell,

FIG. 9 is a cross-sectional view showing the manufacturing process of the memory cell,

FIG. 10 is a cross-sectional view showing a manufacturing process of the memory cell,

FIG. 11 is a plan view and a cross-sectional view showing the configuration of a conventional EEPROM.

[Explanation of symbols]

10, 30 ... P-type Si substrate, 11, 12, 32 ... Source / drain regions (n ⁺ -Type layer), 13 ... first gate insulating _{film, 14,14a, 14b, 34,34 1a ~34} 4b ... floating gate, 15 ... second gate insulating film, 16,36,36 _{1-36 4} ... control gate, 36 ₅ , 36 ₆ ... Select gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Yamada 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research Laboratories

Claims (3)

[Claims] 1. A non-volatile semiconductor memory device comprising a memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate, and writing / erasing is performed by transfer of electric charge to / from the floating gate. Is divided in the channel length direction, a nonvolatile semiconductor memory device. 2. A NAND type memory cell unit in which a floating gate and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells are electrically connected to each other to electrically rewrite the floating gate and the substrate. In the nonvolatile semiconductor memory device in which the memory cell units are arranged in a matrix, the floating gates of the memory cells are divided in the channel length direction. 3. The floating gate of the memory cell is divided into two having different lengths, and the memory cell stores 2-bit information depending on the charge accumulation state of the floating gate. Item 3. The nonvolatile semiconductor memory device according to item 1 or 2.