JPH10125812A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax the field concn. on the edge of a floating gate and increase the coupling ratio of memory cells to improve the reliability by forming the floating gate like a trapezoidal sectional shape in the control gate direction. SOLUTION: On a surface layer of a semiconductor substrate 11 element isolation regions 12 are selectively formed with source/drain regions 19 and channel regions formed on the substrate surface layer between the element isolation regions 12. On the channel regions floating gates 14i are formed through a first insulation film 131 so that a plane extending from a pair of side walls makes an acute angle to a plane extending from the top face ends and control gates 16i are formed on the tops and side wall of the floating gates 14i through a second insulation film 15. At regions surrounded with the insulation film 12 on p-wells formed on the n-type Si substrate 11, NAND cells composed of four memory cell transistors and two selective transistors sandwiching them are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a floating gate of a memory cell transistor and a method of forming the same in a semiconductor device having a memory cell transistor having a floating gate and a control gate. For use in, for example, nonvolatile semiconductor memory devices.

[0002]

2. Description of the Related Art In recent years, a nonvolatile semiconductor memory device (EEPRO) having an array of electrically rewritable memory cells has been developed.
M), in order to improve the degree of integration, a NAND cell type EEPROM in which a plurality of memory cell transistors are connected in series to form a NAND cell has been developed (Japanese Patent Laid-Open No. 1-173654).

FIG. 6 shows a NAND of this type of EEPROM.
FIG. 8 is a plan view showing the basic configuration of the cell, and FIG.
(B) is a sectional view taken along line AA 'and BB' of FIG. 8, and FIG. 8 is an equivalent circuit of the NAND cell of FIG.

In this example, four memory cells M1 to M4
And two select MOS transistors S1 and S2 are connected in series in such a manner that their source and drain diffusion layers 9 are shared.
This constitutes an AND cell. Such NAND cells are arranged in a matrix to form a memory array.

The drain 9 of the NAND cell is connected to a bit line BL via a select transistor S1. Also,
The source 9 of the NAND cell is connected to the ground line 10 via the selection transistor S2. The control gates CG1 to CG4 of each memory cell are connected to a word line WL crossing the bit line BL. In this embodiment, one memory cell has four memory cells.
Although one NAND cell is configured, one NAND cell can be generally configured by 2 n (n = 1, 2,...) Memory cells.

Next, a specific cell structure is shown in FIG.
This will be described with reference to FIG. p on n-type silicon substrate 1
A well 1 'is provided. A memory cell is formed on this p-well 1 ', and peripheral circuits are provided on a different p-well from the memory cell. In the NAND cell, in one example, four memory cells and two select transistors sandwiching the memory cell are formed in one region surrounded by the element isolation insulating film 2 on the p well 1 '.

Each memory cell has 5 to 2 on p well 1 '.
Via a first gate insulating film 3 ₁ made of a thermal oxide film of 0 nm, the floating gate 4 _i by the first-layer polycrystalline silicon film of 50~400nm (i = 1, 2, 3, 4) are formed, the A control gate 6 _i (i = 1, 2, 3, 4) is formed by a second-layer polycrystalline silicon film of 100 to 400 nm via a second gate insulating film 5 of a 15 to 40 nm thermal oxide film.
Are formed. The control gates 6 _i are arranged continuously in one direction to form word lines WL.

The source / drain diffusion layer 9 of each memory cell
Four memory cells are arranged and connected in such a manner that adjacent n-type layers are shared by adjacent ones. The drain 9 of the one end of the memory cell is connected to a bit line 8 via the configured selection MOS transistors S1 by the gate electrode 4 _5, the source 9 of the memory cell at the other end another composed of the gate electrode 4 ₆ It is connected to the ground line 10 via two select transistors S2.

The two selection transistors S 1 and S 2 are connected to p
A third layer composed of a 25 to 40 nm thermal oxide film on the well 1 ';
The gate insulating film 3 ₂ selected by the first-layer polycrystalline silicon film via a gate 4 _5, 4 ₆ are formed. Then, the select gates 4 _5, 4 ₆ through the second gate insulating film 5 on the made of the second layer polycrystalline silicon wiring 6 _5, 6 ₆ is formed. Here, the select gates 4 ₅ and the wiring 6 ₅ are connected by a conductor in the through holes (not shown), are low resistance. Similarly, select gate ₄₆ and wiring ₆₆
Are connected by a conductor (not shown) in the through hole, and the resistance is reduced.

Here, the floating gates 4 ₁ to 4 ₁ of each memory cell are used.
4 ₄ and the control gate ₆₁ through _4, for the pair of side wall surfaces of the respective channel length direction is simultaneously patterned using the same etching mask, edges are aligned. Similarly, the select gates 4 ₅ and 4 ₆ and the low-resistance wirings 6 ₅ and 6 ₆ are simultaneously patterned on the pair of side walls in the channel length direction using the same etching mask, and the edges are aligned. Have been.

Further, the source, drain diffusion layer 9 to become n-type layer, the control gate ₆₁ through ₄ and the wiring 6
_5, 6 ₆ as a mask, is formed by ion implantation of arsenic As or phosphorus P.

[0012] In this arrangement, the floating gate 4 _i and coupling capacitance C1 between the substrate 1 in each memory cell is set smaller than the coupling capacitance C2 between the floating gate 4 _i and the control gate 6 _i .

This will be described with reference to a specific example of a cell parameter.
Each of the floating gate 4 _i and the control gate 6 _i has a width of 1 μm, and the floating gate 4 _i extends by 1 μm on both sides on the element isolation insulating film 2 serving as a field region.

Further, the first gate insulating film 3 ₁ example 20
The second gate insulating film 5 is a 35 nm thermal oxide film. Assuming that the dielectric constant of the thermal oxide film is ε, C1 = ε / 0.02 and C2 = 3ε / 0.035. That is, C1 <C2. FIG. 9 is a circuit diagram for explaining write, erase, and read operations in the NAND cell. Table 1 below shows a potential relationship of each gate.

[0015]

[Table 1]

First, memory cells constituting a NAND cell are erased collectively. Therefore, in this example, NAN
Control gates CG1 to CG of all memory cells in the D cell
4 is set to 0 V, and the gates SG1 and SG2 of the selection MOS transistors S1 and S2 and the p-well 1 'surrounding the n-type substrate 1 and the memory cell are set to "H" level (for example, the boosted potential Vp
p '= 18V), and the bit lines BL1 and BL2
Let it be p 'potential.

Thus, the control gates C of all the memory cells
G1 ～CG4 a p-well 1 'while the electric field is applied, the p-well 1 from the floating gate 4 _i' electrons are emitted by the tunnel effect. As a result, all the memory cells M1 to M8 move in the direction in which the threshold value is negative (-1 to 5 V), and become "0". Thus, batch erasing of the NAND cells is performed.

Next, data is written to the NAND cell. Data writing is performed sequentially from the memory cell M4 on the source side. First, when selectively writing only the memory cell M4 (cell A in FIG. 8) on the bit line BL1 side, as shown in Table 1, the gate SG1 of the selection transistor S1 on the bit line BL1 side is set to Vpp / 2 (10 V). ), The gate SG2 of the selection transistor S2 on the source line side is set to 0 V, and the control gate CG4 is set to the "H" level (for example, the boosted potential Vpp =
12 to 20 V), and the other control gates CG1 to CG3 are set to an intermediate potential between 0 V and the "H" level (for example, Vpp / 2).

At this time, the bit line BL1 is set at 0 V, and the bit line BL2 is set at an intermediate potential (for example, Vpp / 2). Thus, the control gate CG4 of the memory cell A and the n-type diffusion layer 9
And a high electric field is applied between the p well 1 '. As a result, p
Electrons are injected from the well 1 'and the n-type diffusion layer 9 into the floating gate by the tunnel effect, the threshold moves in the positive direction, and the state becomes "1" where the threshold is 0 V or more. At this time, the threshold value of the unselected memory cell does not change.

The memory cells M1 to M1 on the bit line BL1 side
In M3, since the control gates CG1 to CG3 are at Vpp / 2 and the n-type diffusion layer 9 and the channel portion are at 0 V, a write mode is set. However, the electric field is weak, electrons are not injected into the floating gate, and the threshold value of the memory cell does not change. "Continue to be in a state.

On the bit line BL2 side where "0" is written or not selected, the memory cells M5 to M7 have the control gates CG1 to CG3 at the intermediate potential Vpp / 2, and the source / drain and channel portions of each memory cell. Is also Vpp / 2, there is almost no electric field between the floating gate and the diffusion layer 9 and the channel portion, and injection and emission of electrons do not occur at the floating gate. Therefore, the threshold value of the memory cell does not change and remains in the “0” state.

In the memory cell M8 on the bit line BL2 side, the control gate CG4 is at the "H" level (Vpp), but the potentials at the source, drain and channel are Vpp.
/ 2 and the mode becomes the writing mode, but the electric field is weak,
No electrons are injected into the floating gate, and the threshold value of the memory cell does not change and remains in the “0” state.

As described above, writing is selectively performed only on the cell A. Next, the operation shifts to the writing of the memory cell M3 one stage higher than the NAND cell. At this time, the memory cell M
3 control gate CG3 is raised to "H" level (Vpp),
Control gates CG1, CG of memory cells M1, M2, M4
2, CG4 is set to the intermediate potential Vpp / 2, the bit line BL1 on the selected memory cell side is set to 0 V, and the other bit lines BL2 are set to the intermediate potential Vpp / 2. Two select gates S1, S2
Is not different from that at the time of selective writing of the memory cell M4. Then, similarly to the writing of the memory cell M4, the writing of the memory cell M3 in the next upper stage can be selectively performed. Similarly, writing is sequentially performed on the memory cells M2 and M1.

At the time of the above writing, the "H" level (V
pp) and the intermediate potential (Vpp / 2) are applied to the control gate and the bit line. The current flowing from the "H" level and the intermediate potential is only the tunnel current and the junction leak between the diffusion layer 9 and the p well 1 '. 10 μA or less.

At the time of batch erasing, the n-type substrate 1 and the p well 1 'surrounding the memory cell are raised to the "H" level (Vpp'), but the current flowing from the "H" level is the tunnel current and 0V. Since it is only the junction leak between the p-well surrounding the circuit and the n-type substrate 1, it is 10 μA or less.

Therefore, the high voltage at the time of writing and erasing can be
Can be produced by a booster circuit from a low voltage of about 5 V externally applied to the circuit. Further, since the current flowing from the high voltage at the time of selective writing is very small, all the memory cells connected to one control gate can be written at once. That is, writing can be performed in the page mode, and high-speed writing can be performed accordingly.

Further, in the above-described writing and erasing methods, surface tunneling between the drain portion of the memory cell and the p-well does not occur when a tunnel current flows, and the number of times of data rewriting and the reliability of data retention are improved. .

Further, since only about 10 V is applied to the gate electrode of the selection gate SG1 at the time of writing, element isolation is easy and the element isolation width can be reduced to the same extent as a conventional hot electron injection type EEPROM.

In the read operation, for example, the case of reading data from the memory cell A will be described. The select gates SG1 and SG2 of two select transistors are set to Vcc (5V).
The transistor is turned on, and an "H" level (for example, 5 V) potential is applied to the control gates CG1, CG2 and CG3 of the non-selected memory cells to turn on the memory cell in the written state, thereby controlling the selected memory cell A. Gate C
G4 is set to "L" level (for example, 0V).

Then, the bit line BL1 connected to the selected memory cell A is set to "H" level (about 1 to 5V), the other bit lines are set to 0V, and the source line is set to 0V. As a result, "0" or "1" of the memory cell A can be determined depending on whether or not a current flows through the bit line BL1.

In the above, N which constitutes the EEPROM
The basic configuration and operation of the AND cell have been described. However, In such a configuration, the electric field between the edge portion F of the floating gate 4 _i shown in FIG. 7 (a) and the floating gate 4 _i and the control gate 6 _i is concentrated as shown in FIG. 10. Therefore, there is a possibility that the second gate insulating film 5 may be broken at the edge F of the floating gate 4 _i . To prevent this, usually, as shown in FIG. 11, the corner portion 4a of the floating gate 4 _i is thermally oxidized after the etching of the edge portion F of the floating gate 4 _i.

[0032] However, rounding the result to the corner portion 4a by such thermal oxidation, as shown in FIG. 12, the edge portion G of the first gate insulating film 3 ₁ side of the floating gate 4 _i also oxidized, the gate bird's beak is it can. As a result, the coupling ratio γ {= C2 / (C1 + C2)} of the memory cell varies, and the reliability decreases. Here, C1 is the coupling capacitance between the floating gate 4 _i and the substrate 1, and C2 is the floating gate 4 _i
The coupling capacitance between the control gates _6i .

In an EEPROM, the larger the value of the coupling ratio γ, the lower the voltage for writing and erasing can be. However, since the value of the coupling ratio γ is usually about 0.6, at present, At the time of writing, a high voltage of about 20 V is applied to the control gate 6 _i , the floating gate 4 _{i is set} to 12 V (= 20 V × 0.6), and electrons are injected from the substrate 1 into the floating gate 4 _i . .

However, when the writing and erasing voltages are high, it is necessary to increase the breakdown voltage of the transistor, which complicates the device design. Further, in designing a row decoder circuit for driving the control gate 6 _i , it is necessary to increase a design rule, so that the pattern area of the row decoder circuit becomes large or the row decoder circuit is arranged in accordance with the arrangement pitch of the control gate 6 _i. It becomes difficult to arrange a word line driving circuit of the circuit.

In view of the above, in order to increase the coupling ratio γ, it is necessary to increase the length of the floating gate 4 _{i in} the direction of the control gate 6 _i to increase C 2. There is a problem that the size of the memory cell also increases.

[0036]

As described above, in the conventional NAND type EEPROM, electric field concentration occurs at the edge of the floating gate, and rounding oxidation is performed to avoid the electric field concentration at the edge of the first gate insulating film. Bird's beak occurs, and as a result, there is a problem that the coupling ratio of the memory cell varies.

Further, the coupling ratio of the memory cell is set to 0.
Since it was about 6, the voltage for writing and erasing was 20
V, which makes the device design and row decoder circuit design complicated and difficult.

The present invention has been made in order to solve the above-mentioned problems, and alleviates the electric field concentration at the edge of the floating gate and increases the coupling ratio of the memory cell.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can lower the voltage for writing and erasing and improve reliability.

[0039]

According to the present invention, there is provided a semiconductor device comprising:
An element isolation region selectively formed in a surface layer portion of a semiconductor substrate, a drain region, a channel region, and a source region formed in a substrate layer portion between the element isolation regions; and a first insulating film on the channel region A floating gate having a forward tapered side wall such that the extended surfaces of the pair of side walls form an obtuse angle with respect to the extended surface of the upper surface end; And a control gate formed with an insulating film interposed therebetween.

In the semiconductor device of the present invention, when the element isolation region is a field oxide film, the height of the lowest portion of the upper surface of the floating gate is higher than the height of the highest portion of the upper surface of the field oxide film. It is desirable that the thickness be set to be higher.

According to the method of manufacturing a semiconductor device of the present invention, a step of selectively forming an element isolation region in a surface layer portion of a semiconductor substrate and a step of forming a first insulating film on a substrate surface between the element isolation regions Forming a conductive film for forming a floating gate to a predetermined thickness on the first insulating film;
Patterning the conductive film by a tapered RIE method so that a side wall surface becomes a forward tapered shape; forming a second insulating film so as to cover at least an upper surface and a side wall surface of the floating gate; Forming a conductive film for a control gate so as to face the upper surface and the side wall surface of the conductive film via the second insulating film.

In the method of manufacturing a semiconductor device according to the present invention,
When the element isolation region is a field oxide film,
When the conductive film for forming the floating gate is formed to have a predetermined thickness, the height of the lowest portion of the upper surface of the floating gate is higher than the height of the highest portion of the upper surface of the field oxide film. It is desirable to form it.

[0043]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a NAND cell type EEPROM according to a first embodiment of the semiconductor device of the present invention.
It is a block diagram which shows M. A bit line control circuit 32 is provided for performing data write, read, rewrite, and verify read on the memory cell array 31. The bit line control circuit 32 is connected to a data input buffer 36. The address signal from the address buffer 34 is applied to a bit line control circuit 32 via a column decoder 33 as a column selecting means for selecting a bit line.

On the other hand, a row decoder 35 is provided as row selection means for selectively controlling a control gate and a selection gate in the memory cell array 31. Further, a substrate potential control circuit 37 is provided to control the potential of a P-type region (P substrate or P-type well) in which the memory cell array 31 is formed.

The program end detection circuit 38 detects the data latched in the bit line control circuit 32 and outputs a write end signal. The write end signal is output from the data input / output buffer 36 to the outside. The bit line control circuit 32 mainly includes a CMOS flip-flop (FF)
Having. These FFs perform latching of data for writing, a sensing operation for detecting a potential of a bit line, a sensing operation for verify reading after writing, and a latch of reread data.

FIG. 2 shows the NAND cell type EE shown in FIG.
FIG. 3 is a plan view showing an example of a pattern of a PROM.
(A), (b) is sectional drawing which shows an example of the structure along arrow AA 'and BB' direction in FIG.

The EE shown in FIGS. 2 and 3 (a) and (b)
In the PROM, a p-well 11 'is provided on an n-type silicon substrate 11, and a NAND cell, 4 in this example, is formed in a region surrounded by an element isolation insulating film (field oxide film) 12 on the p-well 11'. Consisting of two memory cell transistors and two select transistors sandwiching the memory cell transistors
A cell is formed.

The peripheral circuit is provided on a different p-well from the NAND cell. In this case, using a p-type silicon substrate, an n-well may be provided in the p-type silicon substrate, a p-well may be provided in the n-well, and a NAND cell may be formed on the p-well.

Each memory cell transistor of the NAND cell has a thickness of 5 to 20 formed on p-well 11 '.
nm between the first gate insulating film 13 ₁ of a thermally oxidized film, the first layer portion on the thickness, which is formed of the first gate insulating film 13 ₁ and on the field oxide film 12 is not less than 1000nm polycrystalline The floating gate 14 _i (i
= 1, 2, 3, 4), a second gate insulating film 15 formed on the floating gate 14 _i and made of a thermal oxide film having a thickness of 15 to 40 nm, and a second gate insulating film 15 on the second gate insulating film 15. A control gate 16 _i (i = 1, 2, 3, 4) formed of a second-layer polycrystalline silicon film having a thickness of 100 to 400 nm or a laminated film of a silicide film and a polycrystalline silicon film;
The floating gate 14 _i below the p-well 11 'surface portion source channel region made of n-type diffusion layers formed to sandwich the direction of arrangement of the four memory cell transistor of the NAND cell of, and a drain region 19 Have.

In this case, the source / drain regions 19 of each memory cell transistor are shared by adjacent ones in the arrangement direction of the memory cell transistors of the NAND cell. In addition, the control gates 16 _i are arranged continuously in a direction orthogonal to the arrangement direction of the memory cell transistors to form a word line.

[0051] Further, the drain 19 of one end side of the memory cell transistor of the NAND cell, a first selection transistor having a gate electrode 14 ₅ (MOS transistor)
It is connected to the bit line 18 through the source 19 on the other end side of the memory cell transistor of the NAND cell is connected to a second selection transistor (MOS transistor) via a ground line 20 having a gate electrode 14 ₆ .

Each of the selection transistors has a p-well 1
1 'and the third gate insulating film 13 ₂ having a thickness that is formed is made of a thermal oxide film 25~40nm on, the third gate insulating film 13 thickness formed on the _two of more than 1000 nm 1
Select gates 14 ₅ and 14 _{6 made of} polycrystalline silicon film
When, and wirings 16 _5, 16 ₆ The selection gate 14 _5, 14 thick formed on the ₆ consists of a second layer polycrystalline silicon film of 100 to 400 nm. Here, the selection gate 14 ₅ and the wiring 16 ₅ are connected via the conductor in the via hole (not shown), are low resistance. Similarly,
The select gates 14 ₆ and the wiring 16 ₆ are connected via conductor in the via hole (not shown), are low resistance.

Then, the floating gate 14 _{1 of} each memory cell
-14 ₄ and the control gate _161-164, the pair of side wall surfaces of the channel length direction, respectively, are simultaneously patterned using the same etching mask, edges are aligned. Similarly, the selection gate 14 _5, 14 ₆ and the wiring 16 _5, 16 _6, the pair of side wall surfaces of the channel length direction, respectively, are simultaneously patterned using the same etching mask, edges are aligned.

[0054] Further, as the source, n-type layer to be a drain region 19, the control gate _161-164 and the wiring 16 _5, 16 ₆ a mask, arsenic As or phosphorus P
Formed by ion implantation.

Next, an example of a method of manufacturing an EEPROM having the above-described structure shown in FIGS. 3A and 3B will be described. In this manufacturing method, first, an element isolation region is selectively formed in a surface layer portion of a semiconductor substrate. Next, a first insulating film is formed on the substrate surface between adjacent element isolation regions. next,
A conductive film for forming a floating gate is formed on the first insulating film to have a predetermined thickness. Next, the conductive film is patterned by a tapered RIE (reactive ion etching) method so that a sidewall surface of the conductive film has a forward tapered shape, and a slit corresponding to the element isolation region is provided. Next, a second insulating film is formed so as to cover at least an upper surface and a side wall surface of the patterned conductive film.
Next, a conductive film for forming a control gate is formed so as to face the upper surface and the side wall surface of the conductive film for forming a floating gate with the second insulating film interposed therebetween. The conductive film, the second insulating film, and the conductive film for forming the floating gate are sequentially patterned so that the edges are aligned in the channel length direction to form a floating gate and a control gate for the memory cell transistor.

That is, in the EEPROM having the structure shown in FIGS. 3A and 3B, taper RIE is performed at the time of patterning for aligning the edges of the conductive film for forming the floating gate in the word line direction. As shown in FIG.
The floating gate 14 _{i of the} cell has a trapezoidal cross section along the length direction of the control gate 16 _i .

In other words, in the cross section shown in FIG. 3, the floating gate 14 _i has a forward tapered shape in which the extended surfaces of the pair of side walls form an obtuse angle (for example, 100 to 95 °) with the extended surface of the upper end. Is formed. Thus, during a write operation and erase operation of the memory cell transistor, the electric field concentration between the floating gate 14 _i · control gate 16 _i at the edge portion E of the floating gate 14 _i is relaxed, the second gate between the gates The destruction of the insulating film 15 is prevented.

Such an effect can be obtained even when a trench (groove) structure is adopted as the element isolation region. Here, a corner portion where the side wall surface of the floating gate 14 _i is continuous with the upper end may be rounded by thermal oxidation or the like. That is, since the cross-sectional shape of the floating gate 14 _i shown in FIG. 3 is a trapezoidal shape, can be provided with a rounded corner portion at mild thermal oxidation conditions, while suppressing the variation in the turn coupling ratio of memory cell γ , Floating gate 14 _i
Can be further alleviated at the edge portion E.

An E having the structure shown in FIGS.
In EPROM, as shown in FIG. 4, so that the upper surface height D of the lowest portion of the floating gate 14 _i than the upper surface height of the C of the highest portion of the field oxide film 12 is high, the floating gate 14 _i Of the field oxide film 12 (for example, 600 nm) or more (300 nm or more).
nm or more).

[0060] Thus, it is possible to take from the top surface C of the field oxide film 12 to the top surface D of the floating gate 14 _i the height H increases, the same height by the side wall surface of the floating gate 14 _i was tapered However, in combination with the increase in the area of the side wall surface, the contact length 1 between the floating gate 14 _i and the control gate 16 _i via the second gate insulating film 15 can be increased.

As a result, the coupling capacitance between the floating gate 14 _i and the control gate 16 _i can be increased, the coupling ratio of the memory cell can be made close to 1, and the write and erase voltages can be significantly reduced.

For example, the coupling ratio γ of the memory cell increases from about 0.6 to about 0.8, and the voltage Vpp for writing and erasing can be reduced from about 20 V to about 15 V. The reason for this is that the voltage of the floating gate is determined substantially by γ × Vpp, and a desired voltage of the floating gate is assumed to be about 12V.

As a result, it becomes easy to design a transistor device and a circuit for driving a control gate such as a row decoder circuit, thereby improving reliability.

After the floating gate material is deposited and before the tapered RIE, for example, a CMP (Chemical Mechanical Po
By introducing an etch-back process by the lishing method and performing a flattening process on the surface of the floating gate material, the floating gate 14 _i and the control gate 16 _i are opposed to each other in a plate shape via the gate oxide film 15. , Device (EEPRO)
M) can be reduced in thickness.

[0065] Hereinafter, the field oxide film 12, an example of the floating gate 14 _i of the formation process will be described with reference to FIGS. 5 (a) to (c). First, as shown in FIG. 5A, a field oxide film 12 is formed by masking an element region of a memory cell portion on a p-well 11 'with, for example, an SiN film 21.

Thereafter, as shown in FIG.
The film 21 is removed, a first gate insulating film 11 is formed, and a first gate insulating film 11 is formed.
After depositing the layer polycrystalline silicon film 14, FIG.
As shown in (1), the first-layer polycrystalline silicon film 14 is flattened by an etch-back process.

[0067] Thereafter, as shown in FIG. 5 (d), by etching the first layer polycrystalline silicon film 14 by using the tapered RIE, floating of the cross-section along the length of the control gate 16 _i trapezoidal Gate _14i is obtained.

[0068] Incidentally, in the case of not performing planarization treatment of the floating gate material surface, the upper surface of the floating gate 14 _i the center portion becomes lower concave than the end according to the level shape of the underlying surface, the floating gate opposing area between 14 _i and the control gate 16 _i are both wider than the facing area of the case opposed to the flat, the coupling capacitance between the floating gate 14 _i · control gate 16 _i increases.

It should be noted that the present invention relates to the NAN of the above-described embodiment.
A plurality of memory cell transistors M1, M2 each having a two-layer gate structure as shown in FIG.
,..., Mn are connected in parallel and select transistors S1, S2 are connected in series at both ends thereof, or a plurality of memory cell transistors M1, M2,. Connected in parallel,
A DI having a selection transistor connected in series at one end
The present invention is also applicable to an EEPROM having an array of NOR cells. Further, the present invention is not limited to the above-described examples, and can be variously modified and implemented without departing from the gist thereof.

[0070]

As described above in detail, according to the present invention, the electric field concentration between the floating gate and the control gate at the edge of the floating gate can be reduced by making the cross-sectional shape of the floating gate in the control gate direction trapezoidal. As a result, the insulation film between the floating gate and the control gate can be prevented from being broken, so that the reliability of the memory cell can be improved.

Further, by increasing the coupling capacitance between the floating gate and the control gate, it is possible to reduce the voltage for writing and erasing the memory cell, and to control the device design of the transistor and the control of the row decoder circuit and the like. A circuit for driving the gate can be easily designed, and a highly reliable EEPROM can be realized.

[Brief description of the drawings]

FIG. 1 shows an EEPROM according to a first embodiment of the present invention.
1 is a block diagram showing an example of a NAND cell of FIG.

FIG. 2 is an EEPROM according to the first embodiment of the present invention;
1 is a plan view showing an example of a NAND cell of FIG.

FIG. 3 is a sectional view taken along lines AA ′ and BB ′ in FIG. 2;

FIG. 4 is a sectional view taken along the line AA ′ in FIG. 2;

FIG. 5 is a sectional view for explaining an etch-back step at the time of forming a floating gate in FIG. 2;

FIG. 6 is a plan view showing an example of a NAND cell of a conventional EEPROM.

FIG. 7 is a sectional view taken along arrows AA ′ and BB ′ in FIG. 6;

FIG. 8 is an equivalent circuit diagram of the NAND cell in FIG. 6;

FIG. 9 is a circuit diagram for explaining the operation of the NAND cell of FIG. 6;

FIG. 10 is a cross-sectional view for explaining that an electric field between a floating gate and a control gate is concentrated at an edge of the floating gate.

FIG. 11 is a cross-sectional view for explaining round oxidation of an edge portion of a floating gate.

FIG. 12 is a cross-sectional view for explaining a gate bird's beak generated in an insulating film between a floating gate and a substrate.

FIG. 13 is an equivalent circuit diagram showing an example of an AND cell of the EEPROM.

[Explanation of symbols]

11 ... n-type silicon substrate, 11 '... p-well, 12 ... the element isolation insulating film, 13 ₁ ... first gate insulating film, 13 ₂ ... second gate insulating _{film, 14i (14 1 ~14 4)} ... a floating gate, 14 _5, 14 ₆ ... selection gate, 15 ... third gate insulating _{film, 16i (16 1 ~16 4)} ... control gate, 16 _5, 16 ₆ ... selection gate wiring, BL1 ~BL3, 8 ... bit line, 19 ... Source and drain diffusion layers, M (M1 to M8) ... memory cell transistors, S (S1, S2) ... selection transistors.

Claims (11)

[Claims] An element isolation region selectively formed in a surface layer of a semiconductor substrate; a drain region, a channel region, and a source region formed in a surface layer of the substrate between the element isolation regions; A floating gate formed via the first insulating film, the floating gate having a forward tapered sidewall surface such that the extended surfaces of the pair of sidewall surfaces form an obtuse angle with the extended surface of the upper surface end; And a control gate formed on a side wall surface with a second insulating film interposed therebetween. 2. The element isolation region is a field oxide film, and the floating gate has a thickness such that the height of the lowest portion of the upper surface is higher than the height of the highest portion of the upper surface of the field oxide film. The semiconductor device according to claim 1, wherein is set. 3. The semiconductor device according to claim 1, wherein a corner portion where a side wall surface of the floating gate is continuous with an upper end portion is rounded. 4. The semiconductor device according to claim 1, wherein an upper surface of the floating gate is lower at a center portion than at an end portion. 5. The semiconductor device according to claim 1, wherein an upper surface of the floating gate is flattened. 6. The semiconductor device according to claim 1, wherein the memory cell array includes memory cell transistors arranged in a matrix, a row selection unit that selects a control gate of the memory cell array, and the memory. A semiconductor device, comprising: a non-volatile semiconductor storage device including: a column selection unit that selects a bit line of a cell array. 7. The semiconductor device according to claim 1, wherein the memory cell unit includes a plurality of memory cell transistors connected to each other, and a memory cell unit is arranged in a matrix. A semiconductor device comprising: a non-volatile semiconductor memory device including a row selection unit for selecting a control gate and a column selection unit for selecting a bit line of the memory cell array. 8. The memory cell unit according to claim 1, wherein said plurality of memory cell transistors are connected in series.
8. The semiconductor device according to claim 7, wherein the semiconductor device is a D cell or an AND cell or a DINOR cell in which a plurality of the memory cell transistors are connected in parallel. 9. A step of selectively forming an element isolation region in a surface portion of a semiconductor substrate, a step of forming a first insulating film on a substrate surface between the element isolation regions, and a step of forming the first insulating film. A step of forming a conductive film for forming a floating gate thereon to have a predetermined thickness, a step of patterning the conductive film by a tapered RIE method so that a side wall surface becomes a forward tapered shape, and a step of forming at least the floating gate Forming a second insulating film so as to cover an upper surface and a side wall surface of the semiconductor device;
Forming a conductive film for a control gate so as to face the upper surface and the side wall surface of the conductive film with the insulating film interposed therebetween. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the element isolation region is a field oxide film, and when the conductive film for forming the floating gate is formed to have a predetermined thickness, A method of manufacturing a semiconductor device, wherein the height of the lowest part of the upper surface of the conductive film is higher than the height of the highest part of the upper surface of the field oxide film. 11. The method according to claim 9, further comprising an etch-back step of flattening an upper surface of the conductive film after forming the conductive film for forming the floating gate and before patterning. The manufacturing method of the semiconductor device described in the above.