JP3226589B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory (EEPROM) using electrically rewritable memory cells having a structure in which a floating gate and a control gate are stacked.
And a method for producing the same.

[0002]

2. Description of the Related Art Conventionally, as an EEPROM having a high integration density, an N-series memory cell having a plurality of memory cells connected in series has been proposed.
An AND cell type EEPROM is known. One memory cell has a FETMOS structure in which a floating gate and a control gate are stacked on a semiconductor substrate with an insulating film interposed therebetween, and a plurality of memory cells are connected in series so that adjacent ones share a source and a drain. Connected to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array. The drains on one end of the NAND cells arranged in the column direction of the cell array are commonly connected to a bit line via a selection gate, and the source on the other end is connected to a common source diffusion layer also serving as a source line via the selection gate. ing. The gate electrodes of the control gate and the select gate of the memory cell are commonly connected as a control gate line (word line) and a select gate line in the row direction of the memory cell array, respectively. The operation of this NAND cell type EEPROM is as follows.

[0003] Data writing is performed sequentially from the memory cell farthest from the bit line. Explaining the case of n-channel, a high potential Vpp (for example, 20 V) is applied to the control gate of the selected memory cell, and the control gate and the selection gate of the non-selected memory cell on the bit line side are applied thereto. An intermediate potential VM (for example, 10 V) is applied. 0 V (for example, “1”) or an intermediate potential VM (for example, “0”) is applied to the bit line according to data. At this time, the potential of the bit line is transmitted to the drain of the selected memory cell through the selected gate and unselected memory cells.

When there is data to be written (when data is "1"), a high electric field is applied between the gate and drain of the selected memory cell, and electrons are tunnel-injected from the substrate to the floating gate. As a result, the threshold value of the selected memory cell moves in the positive direction. When there is no data to be written (when data is "0"), there is no change in the threshold value.

In data erasing, a high potential is applied to a p-type substrate (n-type substrate and p-type well formed in the case of a well structure), and the control gate and select gate of the selected memory cell are set to 0V. Then, a high potential is applied to the control gate of the unselected memory cell. Thereby, in the selected memory cell, electrons of the floating gate are emitted to the substrate, and the threshold value moves in the negative direction.

In data reading, a non-selected memory cell on the bit line side from the selected gate and the selected memory cell is turned on, and 0 V is applied to the gate of the selected memory cell. At this time, by reading the current flowing through the bit line, “0”,
A determination of "1" is made.

Such a conventional NAND cell type EEPRO
In M, in the data write mode, the intermediate potential VM is applied to the bit line on which no write is performed. Therefore, to prevent data destruction in unselected NAND cells,
It is essential to provide a selection gate between each NAND cell and a bit line. In the peripheral circuit, an intermediate potential VM and a high potential Vpp are used in addition to the power supply potential Vcc. For this reason, this type of EEPROM requires several types of gate insulating films having different thicknesses in each part.

For example, the gate insulating film of the select gate portion is 3
A silicon oxide film of 0 nm is required, while the gate insulating film under the floating gate of the memory cell is a silicon oxide film of about 10 nm. Conventionally, in order to obtain such two types of gate insulating films, for example, after forming a silicon oxide film of, for example, 30 nm, this is partially etched and removed with an NH ₄ F solution by a photoresist process, and the photoresist is peeled off. 10 again
A process of forming a silicon oxide film having a thickness of nm is adopted.

[0009] However, this photoresist process has a 30 nm
There is a problem that the silicon oxide film and the substrate surface of the 10 nm silicon oxide film forming portion are contaminated, and the gate dielectric strength voltage is deteriorated. This is the same when forming gate insulating films having different thicknesses in the peripheral circuit portion.

[0010]

As described above, the conventional E
In EPROM, in order to obtain a different gate insulating film in each part, oxidation → etching using a photoresist → oxidation,
This causes a problem that gate breakdown voltage is deteriorated, which lowers the reliability of the EEPROM. The present invention has been made in view of such circumstances,
EEPR with improved reliability by preventing gate breakdown voltage deterioration
And to provide a OM manufacturing method.

[0011]

SUMMARY OF THE INVENTION The EEPRO according to the present invention
The method of manufacturing M is a method of manufacturing a semiconductor substrate having element isolation regions formed thereon.
A first layer conductor film is deposited thereon via a first gate insulating film
Then, this is selectively etched to form the selective gate electrode and the selective gate electrode.
And the gate electrode of the first MOS transistor of the peripheral circuit.
After the formation, the second gate insulating film is formed on the substrate through the second gate insulating film.
A layer conductor film is deposited, and at least the cell array area is
Selective etching, leaving over, then the second
A third gate isolation is provided on the substrate surface of the MOS transistor formation region.
After forming the edge film, a third layer conductor film is deposited and selected.
Etching the control gate of the memory cell and the
Forming a gate electrode of the second MOS transistor;
Then, the second layer conductor film under the control gate is etched and floated.
A play gate is formed .

[0012]

[0013]

The gate insulating film contamination in the conventional method has occurred because two gate insulating films are simultaneously formed with a common conductor layer to form a gate electrode. According to the present invention, by applying different conductor layers to the floating gate of the memory cell and the gate electrodes of the two types of MOS transistors in the peripheral circuit, the thickness of the underlying gate insulating film is different. Eliminating the step of forming a photoresist and performing NH ₄ F etching before forming the gate electrode,
A gate electrode can be formed. Thereby, the gate withstand voltage is improved, and a highly reliable EEPROM can be obtained.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an EEPRO according to an embodiment of the present invention.
FIG. 2A is a plan view showing an M NAND cell, and FIGS. 2A and 2B are sectional views taken along lines AA ′ and BB ′. FIG. 3 (a)
(b) shows a first MOS transistor section (intermediate potential VM system) and a second MOS transistor section (high potential V
FIG. 4 is a sectional view of a NAND cell (pp system), and FIG. 4 is an equivalent circuit of a NAND cell.

In this embodiment, four memory cells M ₁ -M ₁
M ₄ is their source and drain diffusion layers are connected in series in a form shared by adjacent ones by constituting the NAND cell. Such NAND cells are arranged in a matrix to form a cell array. One end of the drain of the NAND cell is connected via a selection gate S ₁ to the bit line BL, and also the other end source through the select gate S ₂ are connected to a common source line (common source diffusion layer). The control gates CG _{1 to} CG ₄ of each memory cell are arranged in a direction intersecting the bit line BL and become a word line WL.

In this embodiment, one NAND cell is constituted by four memory cells. In general, one NAND cell is constituted by 2 n (n = 1, 2,...) Memory cells. can do.

The specific memory cell structure and the MOS transistor structure of the peripheral circuit are as shown in FIGS. In this embodiment, different p-type wells 2 and 21 are formed in an n-type silicon substrate 1 in a cell array region and a peripheral circuit region, and a cell array and a peripheral circuit are formed in these p-type wells 2 and 21. In this embodiment, four memory cells and two select gates are formed in a region of the p-type well 2 surrounded by the element isolation insulating film 10.

Select gate section of cell array and first MOS
In the transistor section, 10
A thermal oxide film having a thickness of about 40 nm is formed, on which a select gate electrode 12 and a first MOS are formed by a first polycrystalline silicon film.
A gate electrode 12a of the transistor is formed.

Each memory cell is placed on the p-type well 2 by 5 to 2
The floating gate 4 is formed of a 50-400 nm second-layer polycrystalline silicon film formed via a second gate insulating film 3 made of a 0 nm thermal oxide film. This floating gate 4
A control gate 6 is formed of a third layer polycrystalline silicon of 100 to 400 nm formed thereon with an interlayer insulating film 5 of a 15 to 40 nm thermal oxide film interposed therebetween. The gate insulating film 13 of the second MOS transistor of the peripheral circuit is a third gate insulating film, and its gate electrode 6a is formed of the same third-layer polycrystalline silicon film as the control gate 6 of the memory cell. is there.

The n-type diffusion layers 9 serving as the source and drain of each memory cell and MOS transistor are formed by ion implantation of arsenic or phosphorus after each gate electrode is formed. Four memory cells are connected in series so that adjacent n-type layers 9 serving as source / drain diffusion layers of the memory cells are shared by adjacent ones. On the element-formed substrate,
The bit line 8 and the respective electrode wirings 23 of the peripheral circuit portion are formed by an Al film thereon, which is covered with the CVD insulating film 7.

In such a configuration, the coupling capacitance C ₁ between the floating gate 4 and the substrate of each memory cell is set smaller than the coupling capacitance C ₂ between the floating gate 4 and the control gate 6. This relationship is obtained by extending the floating gate 4 from the element region to the element isolation region, as shown in FIG.

To explain by giving specific parameters,
According to the 1 μm rule, the floating gate 4 and the control gate 6 have a width of 1 μm and a channel width of 1 μm.
And the floating gate 4 is 1 μm on both sides on the element isolation insulating film.
Are extended. The second gate insulating film 3 is, for example, a thermal oxide film of 10 nm, and the interlayer insulating film 5 is a thermal oxide film of 35 nm. If the dielectric constant of the thermal oxide film is ε, then C ₁ = ε / 0.02 and C ₂ = 3ε / 0.035. Therefore, C ₁ <C ₂ .

Next, a specific manufacturing process of the EEPROM of this embodiment will be described with reference to FIGS. These figures show process cross sections of one memory transistor and select gate of the cell array, and first and second MOS transistors of the peripheral circuit.

First, p-type wells 2 and 21 are formed in the cell array region and the peripheral circuit region of the n-type silicon substrate 1 in separate steps with an optimum concentration for obtaining a necessary threshold voltage, according to a normal process. Then LOCOS
In the step, an element isolation oxide film 10 is formed. Subsequently, for example, a 30 nm thermal oxide film is formed as the first gate insulating film 11, and then a 250 nm first polycrystalline silicon film ₁₂₀ is deposited, and necessary impurity doping is performed. Subsequently, for example, a CVD silicon nitride film 31 of 100 nm is deposited (FIG. 5).

[0026] Then, the first-layer polycrystalline silicon film 12 ₀ of the underlying silicon nitride film 31 a photoresist process
Is patterned to select gate electrode 1 in the cell array section.
2 and the gate electrode 12a of the first MOS transistor in the peripheral circuit section are patterned. Thereafter, thermal oxidation is performed to form an oxide film 32 on the side wall of the gate electrode (FIG. 6). As described above, the first gate insulating film 11 under the select gate electrode 12 and the gate electrode 12a is not subjected to the photoresist processing before the gate electrode is formed.

Thereafter, the entire surface is subjected to NH ₄ F treatment to remove the first gate insulating film 11 in a region not covered with the gate electrode. An oxide film is formed. Followed by depositing a second layer polycrystalline silicon film 4 ₀ used as a floating gate of a memory cell, an impurity doping required. On the second layer polycrystalline silicon film 4 ₀ to form a thermal oxide film of 30nm for example, an interlayer insulating film 5. Then the second layer polycrystalline silicon film 4 _0, after processing to separate the parts to be separated before the control gate thereon is formed, the photo cell array region and a first MOS transistor region Cover with a resist 33 (FIG. 7). No photoresist processing is performed on the second gate insulating film 3.

[0028] Then using the photoresist 33 as a mask, the second-layer polycrystalline silicon film by CDE 4 ₀
Is etched to remove the gate insulating film 3 in the second MOS transistor region by NH ₄ F treatment. Then, a third gate insulating film 13 having a thickness of 50 nm is formed thereon by thermal oxidation. depositing a crystalline silicon film _{6 0.} The third layer polycrystalline silicon film 6 ₀ performs the desired impurity doping. Next, a photoresist 34 that covers the control gate region and the second MOS transistor region of the memory cell is patterned (FIG. 8). No photoresist processing is performed on the third gate insulating film 13.

[0029] Then using the photoresist 34 as a mask, the third layer polycrystalline silicon film 6 ₀ and the second layer polycrystalline silicon film 4 ₀ thereunder by selective etching,
The control gate electrode 6 and the floating gate 4 in the cell array region are simultaneously patterned. The third layer polycrystalline silicon film 6 ₀ At the same time the first MOS transistor region, a second layer polycrystalline silicon film 4 ₀ is also removed. Then, the second M
A photoresist 35 for patterning the gate electrode of the OS transistor is simultaneously formed in the cell array region and the second MOS.
A pattern is formed so as to cover the transistor region (FIG. 9).

[0030] Then using the photoresist 35 as a mask, the third layer polycrystalline silicon film 6 ₀ of the second MOS transistor region is selectively etched, the gate electrode 6a patterning. Thereafter, an n-type layer 9 serving as a source / drain diffusion layer is formed by ion implantation of impurities (FIG. 10). Next, an ordinary interlayer insulating film is formed and a metal wiring is formed, thereby completing the EEPROM.

In this embodiment, the removal of the second and third layers of polycrystalline silicon in the first MOS transistor region is performed at the time of forming the control gate and the floating gate pattern. This can be performed at the time of forming the gate electrode pattern of the transistor.
Further, the step of removing an unnecessary gate electrode from each transistor can be performed by another method.

Next, the NAND cell type EEPROM of this embodiment will be described.
The operation of the OM will be described. First, in data erasing, batch erasing is performed on memory cells constituting a NAND cell.
Therefore, in this embodiment, first, second select gate S _1, the gate electrode SG ₁ of S _2, SG ₂ and NAND
Control gates CG _{1 to} CG of all memory cells in the cell
₄ is set to 0 V, and a high potential Vpp (for example, 18 V) is applied to the n-type substrate 1 and the p-type well 2. High potential Vpp is also applied to bit lines BL ₁ and BL ₂ . As a result, an electric field is applied between the control gates of all the memory cells and the p-type well 2, and electrons are emitted from the floating gate 4 to the p-type well 2 by a tunnel current. All memory cells M
₁ ~M ₄ is thereby in threshold is moved in the negative direction,
The state becomes “0”.

[0033] Next, data writing is performed from the memory cell M ₄ remote from the memory cell or bit line on the source line side in the NAND cell sequentially. Now, the memory cell M ₄
In the case where data “1” is selectively written into the gate electrode SG of the second selection gate S ₂ on the source side,
₂ is a 0V, control a high potential Vpp is applied to the gate CG _4, the remaining control gate CG ₁ ~CG ₃ and the gate electrode SG ₁ of the first selection gate S ₁ of the drain-side power supply potential Vcc and the high An intermediate potential VM between the potentials Vpp (for example, (1 /
2) Vpp) is applied. Further, 0 V is applied to the selected bit line BL ₁ as the “L” level potential, and the intermediate potential VM is applied to the non-selected bit line BL ₂ . The p-type well is set to 0 V, and the n-type substrate is set to Vcc.

Thus, in the selected cell,
0V bit line BL ₁ is a high electric field is applied between the control gate are transferred to the drain, electrons are injected into the floating gate. As a result, the threshold value of the selected cell moves in the positive direction, and "1" is written.

Another memory cell M connected to the bit line BL ₁
Becomes the ₁ ~M ₃ in the writing mode, the electric field is small, no threshold changing. In the non-selected (or "0" is written) memory cells along bit line BL ₂ side of the CG ₁ ~CG ₃ of the control gate intermediate potential VM, the channel potential is Vcc, the potential difference is a 3~4V Again, there is no threshold change. Memory cells along CG ₄ bit lines BL ₂ side are likewise write mode, but also the electric field is small, no threshold changing.

When writing to the selected memory cell is completed in this way, next, writing is similarly performed to the memory cell M ₃ immediately above in the NAND cell, and writing is sequentially performed with the memory cells M ₂ and M _1. Is made.

The data read operation, will describe the memory cell M _4, the gate electrode SG ₁ of the select gate, SG
₂ Vcc is applied to the still Vcc is given, the control of the selected cell as the degree of potential non-selected control gate CG ₁ ~CG ₃ of the memory cell M ₁ ~M _{3 "1"} state of the memory cell is turned on gate CG ₄ is a 0V. Then, a read potential of ₁ to 5 V is applied to the bit line BL ₁ connected to the selected cell, and the other unselected bit lines BL ₂ are set to 0 V. Thus, depending on whether or not current flows in the bit line BL _1, the data "0", the determination of "1" is made.

According to this embodiment, the photoresist does not directly contact the gate insulating film under the gate electrode of the cell array and the peripheral circuit. Therefore, the contamination of the gate insulating film due to the resist processing is eliminated, and the gate insulation withstand voltage is reduced. A highly reliable EEPROM can be obtained.

In the embodiment, a NAND cell type EEPROM is used.
However, the present invention is not limited to this,
NO using memory cell with floating gate and control gate
The same can be applied to an R-type EEPROM.
A similar technique is applied to a flash EEPROM of an EPROM type memory cell without a control gate, a DRAM, an SRA
It is also possible to apply to M and the like.

[0040]

As described above, according to the present invention, it is possible to provide an EEPROM in which the contamination of the gate insulating film by the photoresist is prevented and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is an NAN of an EEPROM according to an embodiment of the present invention.
The top view of a D cell.

FIG. 2 shows AA 'and BB' of the NAND cell of FIG.
Sectional view.

FIG. 3 is a sectional view of the peripheral circuit transistor of the embodiment.

FIG. 4 is an equivalent circuit diagram of the NAND cell according to the embodiment.

FIG. 5 is a sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing step of the embodiment.

FIG. 7 is a sectional view of the manufacturing process of the embodiment.

FIG. 8 is a sectional view of the manufacturing process of the embodiment.

FIG. 9 is a sectional view of the manufacturing process of the embodiment.

FIG. 10 is a sectional view of the manufacturing process of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type silicon substrate, 2, 21 ... p-type well, 10 ... element isolation insulating film, 11 ... 1st gate insulating film, 3 ... 2nd gate insulating film, 13 ... 3rd gate insulating film, 4 ₍₄₁ to ₄₎ ... floating gate (second layer polycrystalline silicon film), 5 ... interlayer insulating film, 6 ₍₆₁ through ₄₎ ... control gate (third layer polycrystalline silicon film), 6a ... gate Electrode (third layer polycrystalline silicon film), 12 (12 ₁ 12 ₂ ) ... select gate electrode (first layer polycrystalline silicon film), 12a ... Gate electrode (first layer polycrystalline silicon film), 7 ... CVD insulation Film 8 bit line 9 n-type diffusion layer (source, drain, common source) 23 electrode wiring M ₁ ~M ₄ ... memory cell, S _1, S ₂ ... selection gate.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-12572 (JP, A) JP-A-62-76668 (JP, A) JP-A-3-126265 (JP, A) JP-A 62-76265 150781 (JP, A) JP-A-2-96378 (JP, A) JP-A-4-348072 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27 / 115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] An electrically rewritable nonvolatile semiconductor memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate via a gate insulating film, and a cell array in which select gates having select gate electrodes are arranged. And first and second at least two types of MOs having gate insulating films of different thicknesses.
A method of manufacturing a nonvolatile semiconductor memory device having a peripheral circuit including an S transistor, comprising: depositing a first layer conductor film via a first gate insulating film on a semiconductor substrate on which an element isolation region is formed. Selectively etching this to form the select gate electrode and the gate electrode of the first MOS transistor of the peripheral circuit; and depositing a second conductive film on the substrate via a second gate insulating film. Selectively etching while leaving it so as to cover at least the cell array region; and forming a third etching on the substrate surface of the second MOS transistor formation region.
After forming the gate insulating film, a third layer conductive film is deposited and selectively etched to form a control gate of the memory cell and a gate electrode of the second MOS transistor. Forming a floating gate by etching the two-layer conductor film; sources of the memory cell and each MOS transistor;
Forming a drain diffusion layer. A method for manufacturing a nonvolatile semiconductor memory device, comprising: