KR100745030B1 - Flash memory device, method for manufacturing the same and driving method for the same - Google Patents

Abstract

A flash memory device, its fabricating method and a driving method are provided to improve CHE(Channel Hot Electron) programming efficiency by dividing a floating gate into two regions and forming the parts in material of different work functions. A first gate electrode(102) is formed in a predetermined portion of an active region on a semiconductor substrate(100), and is divided into a first region(102a) and a second region(102b) which are made of material having different work function. Source/drain regions(103,104) are formed on the substrate corresponding to both sides of the first gate electrode. The first gate electrode is made of polycrystal silicon doped with first and second conductive-type high-concentration impurities corresponding to the first and second regions.

Description

Flash memory device, method for manufacturing same and driving method thereof {Flash Memory Device, Method for Manufacturing the Same and Driving Method for the Same}

1A and 1B are a cross-sectional view and a plan view of a conventional flash memory device

2 is a cross-sectional view showing a conventional single poly flash EEPROM.

3A and 3B show a work function of a conventional single polysilicon flash EEPROM.

4 is a cross-sectional view showing a single polysilicon flash memory device of the present invention.

5 is a graph showing the electric field effect of the channel of the conventional single polysilicon flash memory device of the present invention

6 illustrates a work function for each region of a single polysilicon flash memory device of the present invention.

7 is a circuit diagram showing a single polysilicon flash memory device of the present invention.

8 is a plan view showing a single polysilicon flash memory device of the present invention.

9 is a cross-sectional view taken along line II ′ of FIG. 8.

10A and 10B are cross-sectional views illustrating different embodiments of the stacked flash memory device of the present invention.

11A is a graph showing the characteristics of the drain current (Vgs-Id) versus the voltage applied to the floating gate in a single polysilicon flash memory device of the prior art and the present invention.

FIG. 11B is a graph showing the transconductance (Vgs-Gm) characteristics of a voltage applied to a floating gate in a single polysilicon flash memory device of the related art and the present invention.

12 is a graph illustrating electron injection efficiency into a floating gate according to a voltage Vgs applied to a floating gate in a single polysilicon flash memory device of the related art and the present invention.

FIG. 13 is a graph showing threshold voltage shift characteristics of a voltage Vg applied to a floating gate in a single polysilicon flash memory device of the related art and the present invention.

* Description of the Signs of the Major Parts of the Drawings *

100 semiconductor substrate 101 gate insulating film

102: gate electrode 102a: first region

102b: second region 103: source region

104: drain region 200: semiconductor substrate

201: gate insulating film 202: gate electrode

202a: first region 202b: second region

203: source region 204: drain region

300: semiconductor substrate 301: first active region

302: second active region 305: first gate electrode

305a: first region 305b: second region

305c: second gate electrode 310: polysilicon layer

316a: source region

316b: drain region 316c: first high concentration impurity region

316d: second high concentration impurity region 308a to 308d: sidewall insulating film

317: source terminal 318: drain terminal

319 and 320: control gate terminal 400: semiconductor substrate

401: gate insulating film 402, 412: first region

403 and 413: second region 404: interlayer insulating film

405 control gate 406 source region

407: drain region 408: sidewall insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, and more particularly, to a flash memory device (EPEPROM) having improved program speed, a manufacturing method thereof, and a driving method thereof.

Recently emerging digital media devices are changing into a living environment that can easily access the information you want when and where. As digital devices are rapidly spreading from analog to digital, various types of digital devices need storage media that can easily store recorded images, recorded music, and various data. Optical, high-density magnetic and flash memories are rapidly developing as media.

In line with this trend, non-memory semiconductors are becoming more highly integrated and are focusing on System on Chip (hereinafter referred to as "SoC") fields, and the global semiconductor industry is competing for investment in strengthening SoC-based technologies. The SoC integrates all system technologies in one semiconductor. If the system design technology is not secured, the development of non-memory semiconductors will be difficult.

One of the indispensable parts of SoC, where this complex technology is concentrated, is embedded memory, and the most popular of these is the flash EEPROM (Electrically Erasable Programmable Read-Only Memory). This is because it is a highly integrated non-volatile memory device that can store data even when there is no power supply, such as ROM, read-only memory, and can erase and program data electrically. This device is mainly used in products with low power consumption and high-speed programming that require frequent memory changes.

The flash memory is largely divided into a NAND type and a NOR type. The difference is the difference between the read operation speed and the density. The NOR type has a faster read speed than the NAND type. It is mainly used in devices such as mobile phones, set-top boxes, and PDAs, also called code flash.

NAND type is slower than NOR type, but its density is very high, so it is used in devices requiring large memory such as digital cameras and MP3 players.

Hereinafter, a general flash memory will be described with reference to the accompanying drawings.

1A is a cross-sectional view illustrating a general flash memory cell structure, and FIG. 1B is a layout view of a general flash memory cell.

As shown in FIG. 1A, a unit cell of a general flash memory device includes a gate oxide film 4, a floating gate 5, and a control gate on a P-type semiconductor substrate 1. (7) are sequentially stacked, and a source region 2 and a drain region 3 are formed in the semiconductor substrate 1 on both sides of the floating gate 5 by high concentration of N-type impurity ion implantation.

A channel region is defined in the semiconductor substrate 1 below the floating gate 5 between the source region 2 and the drain region 3.

Here, an inter-poly oxide (IPO) 6 is further formed between the floating gate 5 and the control gate 7.

The floating gate 5 is a means for storing charge, and the control gate 7 on the floating gate 5 is for inducing a voltage to the floating gate 5.

As shown in FIG. 1A, the floating gate 5 and the control gate 7 are formed in a stacked structure, and the source region 2 and the drain region 2 are arranged side by side on both sides of the gate having the stacked structure. 3) is formed in the semiconductor substrate 1 to form a single transistor unit block.

The layout structure of a typical flash memory device is as shown in FIG. 1B, where each unit cell 11 is separated by a field isolation region 10 and the control gate 15 of each cell corresponds to one word. Connected to line 12, each word line 12 is isolated from each other. A bit line 13 is formed in a direction perpendicular to the word line 12, and the drain region 17 of each cell is connected to the bit line 13 through a bit line contact 14.

The operation (read, write and erase) of a general flash memory device configured as described above will be described below.

The operation of a general flash memory device mainly writes a cell by injecting high-energy electrons into the floating gate 5, and conversely, by using Fowler-Nordheim tunneling, electrons in the floating gate 5 are transferred to the substrate 1. ) Or the cell is erased by pulling it out into the source / drain regions 2 and 3.

That is, during writing (programming), a voltage of about 5V is applied to the drain region 3, the source region 2 is grounded (0V), and about 8V is applied to the control gate 7, so that channel hot electrons are generated. It is injected into the floating gate.

When the unit block is erased, 0 V or a negative high voltage is applied to the control gate 7 so that tunneling of charge occurs toward the source region 2 or the semiconductor substrate 1, and the source region 2 or A positive high voltage is applied to the semiconductor substrate 1.

Such a general stacked flash memory device (EEPROM) has the following problems.

First, since a typical stacked flash memory device (EEPROM) is formed of a structure in which a floating gate and a control gate are stacked, a polysilicon deposition process and an etching process must be performed to form a floating gate and a control gate, respectively. Longevity increases

Second, since the flash memory device and the logic circuit driving the memory device must be implemented at the same time, a large number of masks is required.

Accordingly, in order to overcome the problems of the general stacked flash memory device (EEPROM) as described above, a single-poly pure CMOS EEPROM (Single Poly Silicon EEPROM) memory device has recently been studied.

The conventional single polysilicon EEPROM memory device will be described as follows.

2 is a cross-sectional view of a conventional single polysilicon flash EEPROM.

As shown in FIG. 2, a transistor formed in a unit cell of a conventional single polysilicon flash EEPROM includes a substrate 40, a gate insulating layer 41, and a gate electrode 42 formed corresponding to a predetermined portion on the substrate 40. And source / drain regions 43a and 43b formed at a predetermined depth in the substrate 40 corresponding to both sides of the gate electrode 42.

Here, the gate electrode 42 functions as a floating gate, and a high concentration of impurities are doped together with the source / drain regions 43a and 43b. Depending on the type of the transistor, the n + or p + type impurity ions are doped. For example, when n + type impurities are doped into the gate electrode 42 and the source / drain regions 43a and 43b, the substrate 40 is defined as a p-type semiconductor substrate.

The gate electrode 42 is connected to the control gate Cg formed to be spaced apart from each other.

Therefore, the conventional single polysilicon EEPROM memory device having the above structure has an advantage that it can be implemented in a relatively simple process compared to the general stacked flash memory device. Meanwhile, the conventional single polysilicon EEPROM memory device having the above structure has almost the same program and erase operations as the general stacked flash EEPROM memory device described with reference to FIGS. 1A and 1B. Accordingly, the conventional single polysilicon EEPROM memory device requires various levels of high voltage and many high voltage switching circuits to perform program and erase operations.

In the following, a single polysilicon flash EEPROM will be described by comparing the work function when implementing an nMOS transistor and a pMOS transistor.

3A and 3B show a work function of a conventional single polysilicon flash EEPROM.

3A and 3B, in the conventional single poly flash EEPROM formed of a complementary metal-oxide semiconductor (CMOS) type, the nMOS transistor 25 and the pMOS transistor 35 are respectively a substrate 20 or a well region ( 30, the gate insulating layers 21 and 31, the gate electrodes 23 and 33 formed corresponding to predetermined portions on the substrate or the well regions 20 and 30, and both sides of the gate electrodes 23 and 33. Source / drain regions 22a and 22b and 32a and 32b are formed in the substrate or well regions 20 and 30 to a predetermined depth. Here, the gate electrode 23 and the source / drain regions 22a and 22b of the nMOS transistor 25 are doped with n + type, the substrate 20 is doped with p type, and of the pMOS transistor 35 The gate electrode 33 and the source / drain regions 32a and 32b are doped with p + type, and the well region 30 is doped with n type. In this case, the well region 30 is defined at a predetermined depth in the substrate 20 at a predetermined depth.

The work functions of the gate electrodes 23 and 33 of the nMOS transistor 25 and the pMOS transistor 35 are Φ 2 and Φ 1, and one of the gate electrodes 33 of the pMOS transistor 35 is represented. The function? 1 is relatively large compared to the work function? 2 of the gate electrode 23 of the nMOS transistor 25.

In embedded non-volatile memory devices, single polysilicon flash EEPROMs are known to be easy to embed in logic processes.

In general, a single poly EEPROM device uses a lightly doped drain (LDD) type junction at both boundaries of a gate electrode and a source / drain region used in a logic device as a source / drain junction. However, a single poly EEPROM device is typically programmed using channel hot carrier injection (CHE). Since the junction between the source / drain region and the channel is an LDD region, hot carrier generation efficiency is good. This slows down the program much.

On the other hand, in order to improve the program speed of a nonvolatile memory device, a method commonly used includes adjusting the doping of a channel region and a drain / source region of the device, and attempting to apply a substrate voltage during programming.

For example, when programming using a MCI (Mid-Channel Injection) cell structure, a structure that extends the drain region toward the channel center direction is used. In this case, a separate mask for redefining the extended drain region is required. Process additions occur and process costs increase.

Alternatively, when using a channel initiated secondary electron injection (CHISEL) method, since a negative voltage is applied to the substrate, a deep N-well forming process is required, thereby increasing the process cost.

As a simple solution, the source / drain junction of the embedded single polysilicon flash EEPROM device can be applied with a separate junction structure that is distinct from the source / drain of the logic device, which requires additional masking and cost. An increase is essential.

Conventional single polysilicon EEPROM devices use a junction structure of a logic device, for example, a lightly doped drain (LDD) structure, etc., for embedding in a standard CMOS logic process. If a single-drain structure is formed without applying the LDD structure used in the logic device, additional process costs are incurred.

Also, in flash memory devices such as EEPROM, channel hot electron (CHE) method is more preferred to FN (Fowler-Nordheim) method in order to reduce operating voltage and time during programming.

In summary, the generation efficiency of hot carriers (for example, hot electrons) during the program operation of the device having the LDD junction structure by the CHE method decreases, and the voltage must be increased for the program. In addition, the use of LDD junction structures results in an increase in cell program time.

The present invention has been made to solve the above problems, and relates to a non-volatile memory device (Non-volatile Memory devcie), in particular a flash memory device (EEPROM) with improved program speed, a manufacturing method and It is an object of the present invention to provide a driving method thereof.

The flash memory device of the present invention for achieving the above object is formed on a semiconductor substrate defined by being divided into an active region and a device isolation region, and formed on a semiconductor substrate of a predetermined portion of the active region, the region is first, It comprises a first gate electrode made of a material divided into two regions and having a different work function corresponding to each region, and a source / drain region formed on the semiconductor substrate corresponding to both sides of the first gate electrode. have.

Here, the first gate electrode corresponds to the first region and the second region, and is made of polysilicon doped with high concentration impurities of first and second conductivity types, respectively.

Alternatively, the first gate electrode may correspond to the first region and the second region, and may be formed of metal having different work functions.

The source / drain regions are doped with a high concentration of impurities of a first conductivity type, and the semiconductor substrate is defined as a second conductivity type.

In this case, when the first conductivity type is n-type and the second conductivity type is p-type, the first region adjacent to the source region is doped with a high concentration of impurity of p-type and is adjacent to the drain region. The second region is formed by doping with an n-type high concentration impurity.

Alternatively, when the first conductivity type is p-type and the second conductivity type is n-type, the first region adjacent to the source region is doped with n-type high concentration impurities and the second region adjacent to the drain region. The region is doped with a high concentration of p-type impurities.

In addition, a second gate electrode is further formed on the semiconductor substrate in a first direction from the first gate electrode, and the semiconductor substrate corresponds to both sides of the second gate electrode in a direction crossing the first direction. High concentration impurity regions may be further formed in the.

The drain region is connected to the bit line, and the high concentration impurity regions on both sides of the second gate electrode are connected to the word line.

Here, the first gate electrode functions as a floating gate, and the high concentration impurity region functions as a control gate.

In addition, the flash memory device of the present invention for achieving the same object is a semiconductor substrate divided into a first region and a second region, and a polysilicon layer formed in a first direction across the first region and the second region And first and second high concentration impurity regions formed on the semiconductor substrate so as to correspond to both sides of the polysilicon layer in a second direction crossing the first direction of the first region, and the first direction of the second region. The third and fourth high concentration impurity regions formed on the semiconductor substrate in correspondence to both sides of the polysilicon layer in a second direction crossing the second direction, and the polysilicon layer between the first high concentration impurity region and the second high concentration impurity region A floating gate defined by dividing to have different work functions, and the third high concentration impurity region and the fourth high concentration impurity region In the yirueojim including a control terminal coupled to the gate, there is another characteristic.

Here, a second conductivity type well is formed in the first region, and a first conductivity type well is formed in the second region.

In the floating gate, a second conductivity type high concentration impurity is injected into a portion adjacent to the first high concentration impurity region and a first conductivity type high concentration impurity is injected into a portion adjacent to the second high concentration impurity region.

In addition, a first conductivity type high concentration impurity is implanted into the first to fourth high concentration impurity regions.

A gate insulating layer may be further interposed between the floating gate and the control gate and the semiconductor substrate.

Here, the first conductivity type may be n-type, the second conductivity type may be p-type or vice versa, the first conductivity type may be p-type, and the second conductivity type may be n-type.

Sidewall insulating films may be further formed on sidewalls of the polysilicon layer between the first and second high concentration impurity regions and between the third and fourth high concentration impurity regions. A low concentration impurity region may be further formed on the semiconductor substrate under the sidewall insulating layer.

The interlayer insulating layer may be further interposed on the entire surface of the substrate by including first to fourth contact holes corresponding to the first to fourth high concentration impurity regions. In this case, the first and second high concentration impurity regions are respectively connected to source and drain terminals further formed on the interlayer insulating layer through the first to fourth contact holes, and the third and fourth high concentration impurity regions are respectively formed. Is connected to the control gate terminal further formed on the interlayer insulating layer. The drain terminal is connected to a bit line, the control gate terminal is connected to a word line, and the source terminal is connected to a source line.

In addition, in the method of manufacturing the flash memory device of the present invention for achieving the same object, a first active region and a second active region are defined on a semiconductor substrate, and a device isolation film is formed in regions other than the first and second active regions. Forming a polysilicon layer in one direction crossing the first active region and the second active region; dividing the polysilicon layer in the first active region on both sides of the polysilicon; Covering a portion adjacent to any one of the drain regions, high concentration impurities of a first type are implanted into the first active region and the second active region, and both sides of the polysilicon layer regions of the first and second active regions are injected. Forming first and second high concentration impurity regions and third and fourth high concentration impurity regions, respectively, and In addition, there is another feature that is made, including the step of injecting a high concentration of the second type of impurities in a state in which the remaining part is covered.

Here, a well of a first type is formed in the second active region, and a well of a second type is formed in the first active region.

And depositing an interlayer insulating film on the entire surface of the semiconductor substrate including the polysilicon layer and selectively removing the interlayer insulating film to form first to fourth contact holes exposing predetermined portions of the first to fourth high concentration impurity regions. And filling the first to fourth contact holes, and depositing a metal layer on the interlayer insulating layer and selectively removing the first and fourth contact holes to form source / drain electrodes on the first and second contact holes. And forming a control gate electrode on the third contact hole and the fourth contact hole.

A bit line is further formed to connect to the drain electrode, and a word line is further formed to be connected to the control gate electrode.

The polysilicon doped with the first and second high concentration impurities between the source and drain regions serves as a floating gate.

In addition, the driving method of the flash memory device of the present invention configured as described above to achieve the same object is to apply a first voltage to the bit line, ground the source line, and the first voltage to the word line Programming by applying the above voltage, grounding the source line and the word line, applying a positive high voltage to the bit line to erase the electrons injected into the floating gate, grounding the source line, and A first voltage equal to or greater than a threshold voltage is applied, a positive voltage is applied to the bit line to ground the floating gate, and a high voltage is applied to the bit line to read whether data is programmed in the floating gate.

Hereinafter, a flash memory device, a manufacturing method thereof, and a driving method thereof of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view showing a flash memory device of the present invention.

As shown in FIG. 4, a flash memory device formed of a flash electrically erasable programmable read only memory (EEPROM) having a single poly floating gate structure of the present invention is deposited on a substrate 100 and a substrate 100. The gate insulating film 101 and the gate electrode 102 formed on the gate insulating film 101 corresponding to a predetermined portion on the substrate 100 and the substrate 100 corresponding to both sides of the gate electrode 102. It includes the defined source / drain regions 103 and 104. Here, the gate electrode 102 is bi-divided and made of polysilicon doped with impurities of different types, and each of the first regions 102a adjacent to the source region 103 is doped with p + impurities. The second region 102b adjacent to the drain region 104 side is doped with n + type impurities. The overlapping region between the gate electrode 102 and the source / drain regions 103/104 is defined as a lightly doped drain (LDD) doped with n-type impurities. In this case, the source / drain regions 103 and 104 are doped with n + type high concentration impurity ions.

In the above description, only the point where the gate electrode 102 is formed of polysilicon is shown, but in some cases, the gate electrode 102 has different work functions for the first and second regions 102a and 102b. It is possible to change various examples such as a conductive material such as a metal having a function).

In addition, the source / drain regions 103 and 104 may be doped with high concentration impurity ions of p + type instead of high concentration impurity ions of n + type. When n + type high concentration impurity ions are doped into the source / drain regions 103 and 104, the device including the gate electrode 102 and the source / drain regions 103 and 104 may be referred to as an nMOS transistor. When the source / drain regions 103 and 104 are doped with high concentration impurity ions of p + type, the device including the gate electrode 102 and the source / drain regions 103 and 104 may be referred to as a pMOS transistor. In the former case, p + type impurity ions are implanted into the first region 102a adjacent to the source region 103, and n + impurity ions are implanted into the second region 102b adjacent to the drain region 104. In the latter case, on the contrary, n + type impurity ions are implanted into the first region 102a adjacent to the source region 103 and p + type impurity ions are implanted into the second region 102b adjacent to the drain region 104. do.

In the example of FIG. 4, the gate electrode 102 is used as a floating electrode, and a spaced apart control gate Cg and the floating electrode are connected to each other.

In the present invention as shown in Figure 4 to improve the program speed of a single polysilicon flash EEPROM device without increasing the cost of forming a separate mask or increase the process, by devising a new structure called a dual work function gate I'm proposing.

5 is a graph showing the electric field distribution of the channels of the single polysilicon flash EEPROM of the prior art and the present invention.

Figure 5 shows the electric field change according to the distance of the channel of the single polysilicon flash EEPROM of the present invention and the conventional structure. First, in the present invention and the conventional single polysilicon flash EEPROM, the length of each channel is 1㎛ When the length of the source / drain regions on both sides of the channel is 1 mu m, the channel and source region boundary points are 1 mu m, and the channel and drain region boundary portions are 2 mu m. In the present invention and the prior art, the thickness of the gate insulating film Tox is 7 nm, the drain-source voltage Vds is 6.0 V, and the gate-source voltage Vgs is 2.0 V. define. In addition, it is assumed that the LDD structure is further formed at the source / drain region and the gate junction in the same manner as in the present invention and the conventional single polysilicon flash EEPROM.

According to this definition, the electric field change at each point of the channel is as follows.

In the case of the conventional single polysilicon flash EEPROM, it rapidly increases from 2.75E + 0.5 [V / cm] from the boundary between the channel and source region (distance 1.0 μm) to about 1.1 μm, and then reaches 3.5 E + 0.5 up to 1.8 μm. It gradually rises to [V / cm], and then the electric field reaches its peak near the distance of 1.8 mu m, and then falls back to the boundary of the channel and drain region to about 2.5E + 05 [V / cm].

In the case of the single polysilicon flash EEPROM of the present invention, there is a tendency similar to the conventional single polysilicon flash EEPROM described above, but since the gate electrode is doped with different heterogeneous impurities, the first region and the second region of the gate electrode At the boundary, that is, at the center of the channel, the electric field changes from about 2.5E + 05 to 4.0E + 05 [V / cm], and the boundary and the center of the channel and source region are slightly lower than those of the conventional case. The electric field rises to about 2.5E + 05 [V / cm], and the electric field value slightly lowered from the center of the channel to the boundary between the channel and the drain region is maintained at a predetermined channel length, and then the The boundary tends to fall to a similar extent as the conventional single polysilicon flash EEPROM.

In this graph, in the single polysilicon flash EEPROM of the present invention, the electric field change in the channel shows a change in electric field characteristics in which the region adjacent to the source region and the region adjacent to the drain region are distinguished from each other. Since the electric field change is large when the same bias voltage is applied, the programming time can be expected to be short. On the contrary, it can be expected that the same programming efficiency can be obtained even if a lower voltage is applied at the time of programming.

6 is a diagram illustrating work functions for respective regions of a single polysilicon flash EEPROM of the present invention.

As shown in FIG. 6, since the single polysilicon flash EEPROM of the present invention is composed of gate electrodes 202 doped with impurities of different types, the first region doped with p + type impurities having a higher work function value, respectively ( A second region 202b doped with an n + type impurity having a lower work function than 202a is defined. In this case, n + impurity ions are doped in the source / drain regions 203 and 204 formed in the semiconductor substrate 200 on both sides of the gate electrode 202.

Although not shown, in some cases, the source / drain regions 203 and 204 may be doped with p + impurity ions, and in this case, the first region 202a adjacent to the source region 203 may be formed. P + type impurity ions are doped in the second region 202b where n + type impurity ions are adjacent to the drain region 204.

In general, the work function between the gate electrode of the nMOS transistor and the gate electrode of the pMOS transistor is different, and the work function of the pMOS transistor is relatively large.

According to the present invention, the potential distribution of the channel region can be adjusted to a desired degree by dividing the gate electrodes adjacent to the source / drain regions, respectively, and inducing a difference in the work function on both sides of the divided region. You can adjust the distribution of the electric field in the channel region of. By adjusting the potential distribution in this channel region, the program efficiency is increased by inducing a reduction in program time using a Channel Hot Electron (CHE) method in a nonvolatile memory device.

Such adjustment of the work function is possible by adjusting the doping of the gate. That is, by selectively doping the gate doping using an ion implantation method or a diffusion method, it is possible to arbitrarily adjust the work function of the gate material.

Since the doping of the gate is performed in the source / drain formation process in the manufacture of the flash EEPROM of the present invention, it is possible to implement by applying an ion implantation process to the (polysilicon) gate material to form the source / drain. Alternatively, the present invention can be implemented using a separate ion implantation and a diffusion process using an additional mask.

Hereinafter, a flash memory device according to the present invention will be described in which a single polysilicon flash EEPROM is implemented by applying polygates having different work functions to both sides of the above-described bifurcation with reference to the drawings.

FIG. 7 is a circuit diagram illustrating a single polysilicon flash memory device of the present invention, FIG. 8 is a plan view illustrating the flash memory device of the present invention, and FIG. 9 is a cross-sectional view taken along line II ′ of FIG. 8.

As shown in FIGS. 7 to 9, the flash memory device of the present invention may be divided into a first active region 301 and a second active region 302, and a semiconductor substrate 300 and the first active region 301. And a polysilicon layer 310 crossing the second active region 302 in a first direction, and the polysilicon layer 310 in a second direction crossing the first direction of the first active region 301. The polysilicon layer 310 in a second direction crossing the source / drain regions 316a and 316b formed in the semiconductor substrate 300 and the first direction of the second active region 302 corresponding to both sides. The polysilicon layer 310 between the first and second high concentration impurity regions 316c and 316d formed on the semiconductor substrate 300 and the source / drain regions 316a and 316b corresponding to both sides. ) Is divided into two to have different work functions The polysilicon layer 310 has a high concentration of a first conductivity type between the first gate electrodes 305: 305a and 305b of the floating gate and the second source / second drain regions 316c and 316d. And a second gate electrode 305c of the floating gate defined by implanting impurities.

The device isolation region 303 is formed in regions except for the polysilicon layer 310, the source / drain regions 316a and 316b, and the first and second high concentration impurity regions 316c and 316d. It is responsible for separation between elements formed on the semiconductor substrate 300.

In this case, a p-type well is formed in the first active region 301, and an n-type well is formed in the second active region 302. Here, the semiconductor substrate 300 is a p-type conductive substrate.

The polysilicon layer 310 is formed to pass through the first active region 301 and the second active region 302 so that the source / drain regions 316a and 316b of the first active region 301 are formed. It serves as a first gate electrode 305 therebetween, and serves as a second gate electrode 305c between the first and second high concentration impurity regions 316c and 316d of the second active region 302. Here, the first and second gate electrodes 305 and 305c are in a floating state and are referred to as floating gates, and both are defined by injecting predetermined impurities into the polysilicon layer 310. That is, the p + type high concentration impurity is implanted into the first gate electrode 305 adjacent to the source region 316a among the divided regions, and the second region adjacent to the drain region 316b is implanted. The high concentration impurity of n + type is injected into 305b. Herein, the n + type high concentration impurity is implanted into the polysilicon layer 310 in all regions except for the portion of the first gate electrode 305a. That is, the n + type high concentration impurity is doped in the remaining portion of the polysilicon layer 310 in which the second gate electrode 305c is formed.

At this time, n + type high concentration impurities are implanted into the source / drain regions 316a and 316b and the first and second high concentration impurity regions 316c and 316d. The source / drain regions 316a and 316b are connected to the source terminal 317 and the drain terminal 318 formed thereon, respectively, and the first and second high concentration impurity regions 316c and 316d are controlled together. It is connected to the gate terminals 319 and 320.

A gate insulating film 304a is further interposed between the first gate electrode 305 and the semiconductor substrate 300, and between the first gate electrode 305 and the semiconductor substrate 300 serving as the floating gate. It functions as a tunneling oxide. Further, a gate insulating film 304b is further interposed between the second gate electrode 305c and the semiconductor substrate 300 so that the first gate electrode 305 and the control gate terminal 319 functioning as the floating gate. And an interlayer insulating film between the first and second high concentration impurity regions 316c and 316d connected to the first and second high concentration impurity regions 316c and 316d as a control gate to form a single polysilicon flash memory device (EEPROM). Can be implemented.

Further, sidewall insulating films 308a and 308b are further formed on sidewalls of the floating gate 305 and the control gate 307, and at this time, low concentration impurity regions (LDDs) are lightly doped in the semiconductor substrate under the sidewall insulating films. Drains may be further formed.

In the foregoing description, the n-type memory element is formed, but the conductive type of the source / drain region, the high concentration impurity region and the well region is reversed (p type to n type, n type to p type). To form a p-type memory device.

In addition, first to fourth contact holes 315a, 315b, 315c, and 315d respectively correspond to the source / drain regions 316a and 316b and the first and second high concentration impurity regions 316c and 316d. An interlayer insulating film (not shown) may be further interposed on the entire surface of the semiconductor substrate 300. In this case, the source / drain regions 316a and 316b may be further formed on the interlayer insulating layer through the first to fourth contact holes 315a, 315b, 315c, and 315d, respectively. The first and second high concentration impurity regions 316c and 316d are connected to the control gate terminals 319 and 320 which are further formed on the interlayer insulating layer.

In addition, the drain terminal 318 is connected to a bit line (BL) (not shown) that is formed to extend in the direction crossing the polysilicon layer 310, the control gate terminals (319, 320) are It is connected to a word line (WL) (not shown) in the polysilicon layer 310 direction, and the source terminal is connected to a source line (SL).

The method of manufacturing the flash memory device of the present invention is made as follows.

That is, the first active region 301 and the second active region 302 are defined in the semiconductor substrate 300, and the device isolation layer 303 is disposed in regions other than the first and second active regions 301 and 302. Form. In this case, a first conductivity type well may be formed in the second active region 302, and a second conductivity type well may be formed and defined in the first active region.

Next, the polysilicon layer 310 is formed in one direction crossing the first active region 301 and the second active region 302.

Subsequently, the polysilicon layer of a predetermined portion of the first active region 301 on both sides of the polysilicon 310 is divided into two parts to cover a portion of the divided portion, and thus, the first active region 301 and the first portion. High concentration impurities of a first type are injected into the active region 302 so that source / drain regions 316a and 316b are formed on both sides of the polysilicon layer 310 of the first and second active regions 301 and 302, respectively. And first and second high concentration impurity regions 316c and 316d.

Subsequently, the blind region is opened, and the second type high concentration impurity is injected while the remaining portion is blocked.

As described above, the polysilicon layer portion doped with the first and second high concentration impurities between the source region 316a and the drain region 316b by the impurity implantation of the polysilicon layer 310 is floated. Functions as a floating gate.

In addition, an interlayer insulating film (not shown) is deposited on the entire surface of the semiconductor substrate 300 including the polysilicon layer 310 and selectively removed to remove the source / drain regions 316a and 316b and the first and second layers. First to fourth contact holes 315a to 315d exposing predetermined portions of the high concentration impurity regions 316c and 316d are formed.

Subsequently, the first to fourth contact holes 315a to 315d are filled, and a metal layer (not shown) is deposited on the interlayer insulating layer and selectively removed to form the first contact hole 315a and the second contact hole. Source / drain electrodes 317 and 318 are formed on 315b, and control gate terminals 319 and 320 are formed on the third and fourth contact holes 315c and 315d. In this case, a bit line BL (not shown) connected to the drain electrode 318 is further formed, and a word line WD (not shown) connected to the control gate electrode is further formed. The bit lines and the word lines may be formed by metal interconnects having different layers by further performing a separate interlayer insulating layer and a contact hole forming process.

On the other hand, when driving the flash memory device of the present invention, programming, applying a first voltage of 5 ~ 10V to the bit line connected to the drain electrode 318, grounds the source line, and the first line to the word line Program by applying voltage above voltage.

The erase operation of the flash memory device of the present invention grounds the source line and the word line, and erases electrons injected into the floating gate by applying a positive high voltage of about 10V or more to the bit line.

In addition, when the flash memory device of the present invention is driven, a reading may be performed by grounding the source line, applying a first voltage equal to or greater than a threshold voltage to the word line, and applying a positive voltage to the bit line. Is grounded and a high voltage is applied to the bit line to read whether data is programmed in the floating gate.

As shown in FIG. 8, the width Wcg of the channel defined by the control gate Cg is wider than the channel width Wfg formed by the floating gate Fg.

In another embodiment, a stacked gate flash memory device (EEPROM) including a gate electrode having a dual work function of the present invention will be described.

10A and 10B are cross-sectional views illustrating different embodiments of a stacked flash memory device (EEPROM) of the present invention.

As shown in FIG. 10A, the stacked flash EEPROM of the present invention includes a semiconductor substrate 400, a gate structure formed by being sequentially stacked on a predetermined portion of the substrate 400, sidewall insulating films 408 formed on both sides of the gate structure, and Source / drain regions 406 and 407 defined on the substrate 400 to correspond to both sides of the gate structure. The gate structure may include a gate insulating layer 401 sequentially stacked on the substrate 400, a floating gate and an interlayer insulating layer including a first region 402 and a second region 403 doped with different impurities. 404 and control gate 405.

Here, the floating gate electrode including the first region 402 and the second region 403 is made of polysilicon, and the length corresponding to the channel is divided into two portions, so that the first region 402 adjacent to the source region 406 is formed. ) Is doped with a p + type impurity having a high work function, and an n + type impurity having a high work function is doped in the second region 403 adjacent to the drain region 407.

The control gate 405 is entirely doped with n + type impurities.

FIG. 10B illustrates another example of a stacked flash EEPROM, wherein the floating gate is formed of a material other than polysilicon doped with impurities, for example, a metal or a similar work function in each of the divided regions 412 and 413. An example made of a metal material is shown. In this case, it is assumed that both the source / drain regions 406 and 407 and the control gate 405 are doped with n + type ions.

10A and 10B, if the source / drain regions 406 and 407 and the control gate 405 are doped with p + type or polysilicon of p + type, the floating gate is the source region (as shown). The first regions 402 and 412 adjacent to 406 are formed of a material having a low work function, and the second regions 403 and 413 adjacent to the drain region 407 are formed of a material having a high work function.

The driving method of the stacked flash EEPROM shown in FIGS. 10A and 10B may be similarly applied to the driving method of the flash memory device of the present invention described with reference to FIGS. 7 to 9.

The graphs described below compare the characteristics of the flash memory device and the conventional flash memory device of the present invention.

FIG. 11A is a graph illustrating the characteristics of the drain current Vgs-Id compared to the voltage applied to the floating gate in the state in which a predetermined drain voltage is applied in the flash memory device of the prior art and the present invention.

In the flash memory device of the present invention conventionally formed as in FIG. 11A and as shown in FIG. 9A or 9B, the channel W / L = 0.6 / 1.0 and the same condition of 1.0V are applied to the drain voltage Vds. The change of the drain current Ids according to the change of the voltage Vgs applied to the floating gate will be described.

At this time, while the Vgs changes from 0 to 5V in the conventional flash memory device, the Ids increases from the initial value, whereas the Vgs value is used in the flash memory device having the double work function floating gate structure of the present invention. There is no change of Ids up to about 1.2V or more, and since then, the increase of Ids has shown, and the tendency of the threshold voltage rise of about 1.0V or more compared with the conventional is shown. This difference in threshold voltage naturally occurs from the difference in the work function of the materials constituting the floating gate.

FIG. 11B is a graph showing the characteristics of the transconductance (Vgs-Gm) versus the voltage applied to the floating gate in the flash memory device of the prior art and the present invention.

As shown in FIG. 11B, in the case of the conventional gm characteristic, the Vgs value starts to rise at about 0.5V, and gradually decreases with a peak of about 0.5E-05 [A / V]. The Vgs value starts to rise at about 1.6V and then drops after reaching a peak of about 8.0E-04 [A / V].

As described above, it can be seen that the flash memory device of the present invention also has a normal drain current (Ids) characteristic and a transconductance (gm) characteristic except for an increase in threshold voltage and transconductance.

12 is a graph showing the injection efficiency (gate current / drain current) of a hot electron to a floating gate according to a voltage Vgs applied to the floating gate in the flash memory device of the prior art and the present invention.

As shown in FIG. 12, the change in the implantation efficiency (Ig / Id) [A / A] according to the change of Vg is relatively higher than that of the conventional flash memory device, and thus the EEPROM of the present invention is more efficient and shifted upward. It can be seen that the graph of. Therefore, the value of the gate current / drain current of the EEPROM of the present invention is high, and thus it can be seen that the injection efficiency during programming is high.

13 is a graph showing threshold voltage shift characteristics with respect to program time of the EEPROM according to the related art and the present invention.

As shown in FIG. 13, the threshold voltage shift characteristic of the EEPROM of the prior art and the present invention is set to 7 V for the Vd value, and the control gate voltage value is increased by 1 V from 7 V to 10 V in the conventional and the present invention in order to Vgs value. The trend of the threshold voltage shift is explained.

In this case, in the case of the conventional EEPROM, the threshold voltage shift characteristic of about 1 V or more is different at the voltage of the same control gate, and the change of the initial 1E-06 [sec] to about 1E-04 [sec] is different. Although the characteristic of the present invention is increased almost similarly, it can be seen that the threshold voltage shift characteristic change shows a large value at about 1E-04 [sec].

Accordingly, it can be seen that the high-speed program and the low-voltage program are possible because the EEPROM of the present invention has a much higher shift of the threshold voltage under the same program condition.

In the flash memory device of the present invention, the floating gate is divided into two and formed of a material having a different work function in the divided region so that the source and drain adjacent regions have different electric field effects when voltage is applied. Accordingly, the program efficiency is increased by the channel hot carrier (CHE) injection method, which reduces the program time and enables the program operation at a lower voltage than the existing structure.

In addition, when the floating gate is formed of a material having a different work function, and the floating gate is formed of polysilicon, such as impurity implantation of source / drain regions, different impurities may be added to each divided region of the floating gate. By doping, the work function is different, and thus, a flash memory device having a higher programming efficiency can be realized without additional process.

The flash memory device of the present invention, a manufacturing method thereof, and a driving method thereof have the following effects.

The flash memory device of the present invention divides the floating gate into a side adjacent to the source region and a side adjacent to the drain region, and is formed of a material having a different work function, thereby increasing the electric field change between the channel regions between the source / drain regions. CHE programming efficiency can be improved. Since the applied voltage can be made relatively small during programming, an effect of reducing the driving voltage can be obtained, and an effect of reducing the time taken during programming can be obtained when the same driving voltage is applied.

In addition, the present invention does not require a separate process for forming a floating gate having a dual work function structure, and defines a CMOS source / drain region, that is, a p + type high concentration impurity region and an n + type high concentration impurity region. In addition, the floating gate may also be bisected and formed by injecting different impurities, thereby forming a floating gate having a double work function structure without adding a separate mask or process.

Claims (31)

A semiconductor substrate divided into an active region and a device isolation region; A first gate electrode formed on a semiconductor substrate at a predetermined portion of the active region, the region being divided into first and second regions, the first gate electrode being made of a material having a different work function corresponding to each region; And And a source / drain region corresponding to both sides of the first gate electrode and formed in the semiconductor substrate. The method of claim 1, And the first gate electrode is made of polysilicon doped with high concentration impurities of a first conductivity type and a second conductivity type, respectively corresponding to the first region and the second region. The method of claim 1, And the first gate electrode corresponds to the first region and the second region and is made of a metal having a different work function. The method of claim 1, The source / drain region is doped with a high concentration of impurities of a first conductivity type, and the semiconductor substrate is defined as a second conductivity type. The method of claim 4, wherein And the first conductivity type is n type and the second conductivity type is p type. The method of claim 5, And the p-type highly doped impurity is doped in the first region adjacent to the source region, and the n-type highly doped impurity is doped in the second region adjacent to the drain region. The method of claim 4, wherein And the first conductivity type is p-type and the second conductivity type is n-type. The method of claim 7, wherein The first region adjacent to the source region is doped with n-type high concentration impurity, and the second region adjacent to the drain region is doped with p-type high concentration impurity. The method of claim 1, A second gate electrode is further formed on the semiconductor substrate in a first direction from the first gate electrode, and a high concentration is formed on the semiconductor substrate corresponding to both sides of the second gate electrode in a direction crossing the first direction. A flash memory device, characterized in that an impurity region is further formed. The method of claim 9, And the drain region is connected to a bit line, and the high concentration impurity regions on both sides of the second gate electrode are connected to a word line. The method of claim 10, And the first gate electrode functions as a floating gate, and the high concentration impurity region functions as a control gate. A semiconductor substrate divided into a first region and a second region; A polysilicon layer formed in a first direction across the first and second regions; First and second high concentration impurity regions formed on the semiconductor substrate so as to correspond to both sides of the polysilicon layer in a second direction crossing the first direction of the first region; Third and fourth high concentration impurity regions formed on the semiconductor substrate so as to correspond to both sides of the polysilicon layer in a second direction crossing the first direction of the second region; A floating gate defined by dividing the polysilicon layer between the first high concentration impurity region and the second high concentration impurity region into two different work functions; And And a control gate terminal connected to the third high concentration impurity region and the fourth high concentration impurity region. The method of claim 12, And a second conductivity type well in the first region, and a first conductivity type well in the second region. The method of claim 12, The floating gate may be implanted with a second conductivity type high concentration impurity into a portion adjacent to the first high concentration impurity region among the divided regions, and a first conductivity type high concentration impurity is injected into a portion adjacent to the second high concentration impurity region. Flash memory device. The method of claim 12, And a first conductivity type high concentration impurity is injected into the first to fourth high concentration impurity regions. The method of claim 12, And a gate insulating film interposed between the floating gate and the control gate and the semiconductor substrate. The method of claim 14, And the first conductivity type is n-type and the second conductivity type is p-type. The method of claim 14, And the first conductivity type is p-type, and the second conductivity type is n-type. The method of claim 12, And a sidewall insulating film is further formed on sidewalls of the polysilicon layer between the first and second high concentration impurity regions and between the third and fourth high concentration impurity regions. The method of claim 19, And a low concentration impurity region is further formed in the semiconductor substrate under the sidewall insulating film. The method of claim 12, And a first to fourth contact holes respectively corresponding to the first to fourth high concentration impurity regions, and further including an interlayer insulating layer on the entire surface of the substrate. The method of claim 21, The first and second high concentration impurity regions are connected to source and drain terminals further formed on the interlayer insulating layer, respectively, through the first to fourth contact holes, and the third and fourth high concentration impurity regions are formed between the interlayers. And a control gate terminal further formed above the insulating film. The method of claim 22, And the drain terminal is connected to a bit line, the control gate terminal is connected to a word line, and the source terminal is connected to a source line. Defining a first active region and a second active region in the semiconductor substrate, and forming an isolation layer in regions other than the first and second active regions; Forming a polysilicon layer in one direction crossing the first active region and the second active region; The polysilicon layer of the first active region on both sides of the polysilicon is divided into two to cover a region adjacent to any one of a source / drain region, so that a high concentration of a first type is applied to the first active region and the second active region. Implanting impurities to form first and second high concentration impurity regions and third and fourth high concentration impurity regions on both sides of the polysilicon layer regions of the first and second active regions, respectively; And A method of manufacturing a flash memory device, the method comprising: opening the covered portion and injecting the second type high concentration impurity in a state in which the remaining portion is covered. The method of claim 24, A well of a first type is formed in the second active region, and a well of a second type is formed in the first active region. The method of claim 24, Depositing an interlayer insulating film over the semiconductor substrate including the polysilicon layer and selectively removing the interlayer insulating film to form first to fourth contact holes exposing predetermined portions of the first to fourth high concentration impurity regions; Filling the first to fourth contact holes, and depositing a metal layer on the interlayer insulating layer and selectively removing the first and fourth contact holes to form source / drain electrodes on the first and second contact holes, and forming the third contact. And forming a control gate electrode on the hole and the fourth contact hole. The method of claim 26, And forming a bit line connected to the drain electrode and a word line connected to the control gate electrode. The method of claim 24, And the polysilicon doped with the first and second high concentration impurities between the source region and the drain region serves as a floating gate. A semiconductor substrate divided into a first region and a second region, a polysilicon layer intersecting the first region and the second region in a first direction, and a cross section crossing the first direction of the first region; A source / drain region formed in the semiconductor substrate corresponding to both sides of the polysilicon layer in two directions, and corresponding to both sides of the polysilicon layer in a second direction crossing the first direction of the second region; The high concentration impurity region formed and the polysilicon layer between the source / drain regions are divided into two, and a high concentration impurity of a second conductivity type is implanted into a region adjacent to the source region, and a high concentration impurity of a first conductivity type is implanted. A defined floating gate, the drain region is connected to a bit line, and the source region is Is coupled to the scan line, and the high concentration impurity region is in a method for driving a binary flash memory device is connected to a word line, And applying a first voltage to the bit line, grounding the source line, and applying a voltage equal to or greater than the first voltage to the word line. A semiconductor substrate divided into a first region and a second region, a polysilicon layer intersecting the first region and the second region in a first direction, and a cross section crossing the first direction of the first region; A source / drain region formed in the semiconductor substrate corresponding to both sides of the polysilicon layer in two directions, and corresponding to both sides of the polysilicon layer in a second direction crossing the first direction of the second region; The high concentration impurity region formed and the polysilicon layer between the source / drain regions are divided into two, and a high concentration impurity of a second conductivity type is implanted into a region adjacent to the source region, and a high concentration impurity of a first conductivity type is implanted. A defined floating gate, the drain region is connected to a bit line, and the source region is A method of driving a flash memory device connected to an os line, and wherein the high concentration impurity region is connected to a word line, And grounding the source line and the word line, and applying a positive high voltage to the bit line to erase the electrons injected into the floating gate. A semiconductor substrate divided into a first region and a second region, a polysilicon layer intersecting the first region and the second region in a first direction, and a cross section crossing the first direction of the first region; A source / drain region formed in the semiconductor substrate corresponding to both sides of the polysilicon layer in two directions, and corresponding to both sides of the polysilicon layer in a second direction crossing the first direction of the second region; The high concentration impurity region formed and the polysilicon layer between the source / drain regions are divided into two, and a high concentration impurity of a second conductivity type is implanted into a region adjacent to the source region, and a high concentration impurity of a first conductivity type is implanted. A floating gate defined therein, the drain region is connected to a bit line, and the source region is A method of driving a flash memory device connected to an os line, and wherein the high concentration impurity region is connected to a word line, Ground the source line, apply a first voltage equal to or greater than a threshold voltage to the word line, apply a positive voltage to the bit line to ground the floating gate, and apply a high voltage to the bit line to apply the floating gate. A method of driving a flash memory device characterized by reading out whether data is programmed in the program.

Images