JPH05114739A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a drain disturbance, which is generated in a non-selection cell at the time of writing of information, by a method wherein the relation between the length and depth of a second impurity region, with which a bit line is electrically connected, is specified. CONSTITUTION:Let the length from the lower part of the side end part of a floating gate 4 along the channel length be A and the depth from the surface of a P-type silicon semiconductor substrate 1 be B. An n<+> drain region 10 is so formed as to satisfy the condition of B/A>=2. In such a way, the area of a region where the region 10 overlaps with the gate 4 is reduced, whereby the area of a region, where a drain disturbance is caused, can be also reduced. Thereby, the drain disturbance, which is generated in an unselected cell at the time of writing of information in a flash EEPROM, can be effectively reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device capable of electrically writing and erasing information and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device capable of electrically writing and erasing information,
EEPROM (Electrically Erasa)
BLEAN PROGRAMMABLE READ
Only Memory) is known. This EEP
The ROM has an advantage that both writing and erasing can be performed electrically, but there is a problem that it is difficult to achieve high integration because the memory cell requires two transistors. Therefore, conventionally, there has been proposed a flash EEPROM in which a memory cell is composed of one transistor, and written information charges can be electrically collectively erased. These are described, for example, in U.S. Pat. No. 4,868,61.
No. 9 and the like.

FIG. 19 is a block diagram showing a general structure of a flash EEPROM. Referring to FIG.
The flash EEPROM has a memory cell array 30 in which a plurality of memory cells (not shown) for storing data are arranged in a matrix and an address signal from the outside is decoded to select a row and a column of the memory cell array 30. X decoder 31 and Y decoder 32, a Y gate 33, an I / O circuit 35 for inputting / outputting data, and a Y gate 33 and an I / O circuit 35, and an external And a control circuit 34 for controlling the operation of the flash EEPROM based on the control signal from. X decoder 31, Y decoder 32, Y gate 33, control circuit 34, input / output circuit 3
5, and the memory cell array 30 includes the semiconductor chip 36.
It is formed on the same substrate above. Further, the semiconductor chip 36 is provided with a power supply input terminal Vcc 37 and a high voltage power supply input terminal V _pp 38.

FIG. 20 is an equivalent circuit diagram showing a schematic structure of the memory cell array 30 shown in FIG. Referring to FIG. 20, in memory cell array 30, a plurality of word lines WL ₁ , WL ₂ , ..., WL _i extending in the row direction,
A plurality of bit lines BL ₁ , BL ₂ , ... Which extend in the column direction
, BL _i are arranged so as to be orthogonal to each other.
Memory cell transistors Q _{1 1} , Q _{1 2} , ..., Q _ii each having a floating gate are arranged at the intersections of each word line and each bit line. The drain of each memory cell transistor is connected to each bit line. The control gate of the memory cell transistor is connected to each word line. The sources of the memory cell transistors are the source lines SL ₁ , SL ₂ ,.
··It is connected to the. Source lines SL ₁ , SL ₂ , ...
Is connected to the source lines S ₁ , S ₂ , ... Arranged on both sides.

FIG. 21 is a cross sectional structural view showing one memory cell (semiconductor memory element) portion including one memory cell transistor shown in FIG. Flash EEPROM having memory cell structure as shown in FIG.
Is called a stack gate type flash EEPROM.

Referring to FIG. 21, a memory cell of a conventional stack gate type flash EEPROM has a P-type silicon semiconductor substrate 101 and a P-type silicon semiconductor substrate 101.
And n ⁺ -type source region 108 and n ⁺ -type drain region 110 formed at predetermined intervals on the main surface of, n ⁺
An n ⁻ type source region 107 formed to cover the type source region 108 for relaxing electric field concentration, and a p ⁺ layer formed to cover the n ⁺ type drain region 110 for improving writing characteristics. 109, a channel region 117 formed between the n ⁺ type source region 108 and the n ⁺ type drain region 110, and 10 formed on the channel region 117.
A gate oxide film 103 having a thickness of 0Å, a floating gate 104 formed of a polycrystalline silicon layer formed on the gate oxide film 103, and a floating gate 10.
4 and an ONO film 105 formed on the ONO film 105 and a control gate 106 made of a polycrystalline silicon layer formed on the ONO film 105.

LDDs of peripheral circuits are provided on both side wall portions of the floating gate 104 and the control gate 106.
Sidewalls 111 for forming the structure are formed. An oxide film 112 is formed so as to cover the entire surface. A nitride film 113 is formed so as to cover the oxide film 112. An interlayer film 114 is formed so as to cover the nitride film 113. Oxide film 112, nitride film 13 and interlayer film 1
Opening portions 14 are formed in regions located on the n ⁺ type drain regions 110, respectively. N in the opening
^The interlayer film 11 is electrically connected to the ⁺ type drain region 110.
4, a titanium layer 115 is formed so as to extend upward.
An aluminum layer 116 is formed on the titanium layer 115. By the n ⁺ type source region 108, the n ⁻ type source region 107, the channel region 117, the n ⁺ type drain region 110, the gate oxide film 103, the floating gate 104, the ONO film 105, and the control gate 106. , A memory cell transistor is configured. The titanium layer 115 and the aluminum layer 116 form a bit line.

FIG. 22 shows a conventional flash EEPROM.
FIG. 7 is a cross-sectional structure diagram for explaining the data writing operation of FIG. FIG. 23 is a sectional structural view for explaining a data erasing operation of the conventional flash EEPROM. Figure 24
FIG. 6 is a sectional structural view for explaining a data read operation of a conventional flash EEPROM. 19 to 2
The operation of the conventional flash EEPROM will be described with reference to FIG.

First, referring to FIGS. 19 and 22, writing of data to a memory cell is performed by using a high voltage power supply input terminal V _pp.
12.5V is applied to 38. This high-voltage power input terminal V
12.5V is supplied from the _pp 38 to the control gate 106. At the same time, the n ⁺ type drain region 110
Is supplied with 7V via a load resistor. The n ⁺ type source region 108 is grounded and has a ground potential (GND). At this time, electrons move from the n ⁺ type source region 108 toward the n ⁺ type drain region 110, and a current of about 0.5 to 1 mA flows through the channel region 117. Then, the flowing electrons are accelerated by the high electric field in the vicinity of the n ⁺ type drain region 110. Due to this acceleration, the electrons obtain high energy exceeding the energy barrier of 3.2 eV from the surface of the P-type silicon semiconductor substrate 101 to the gate oxide film 103. The electrons that have obtained this high energy are called hot electrons.
A part of the hot electrons jumps over the barrier of the gate oxide film 103, and the high potential (1
2.5 V) and injected into floating gate 104. As a result, the floating gate 104
Becomes an electrically negative state. This state corresponds to "0" of the data.

Referring to FIGS. 19 and 23, when erasing data from a memory cell, 12.5 V is applied to high voltage power supply input terminal V _pp 38, similarly to writing. N from this high-voltage power supply input terminal V _pp 38 via a load resistor
9.0 V is supplied to the ⁺ type source region 108. The control gate 106 is grounded to the ground potential (GND).
Becomes The n ⁺ type drain region 110 is brought into a floating state. At this time, the floating gate 104
Oxide film 103 between the n ⁺ type source region 108 and
A high electric field is generated at. Due to this high electric field, a current called Fowler-Nordheim tunnel current flows between the floating gate 104 and the n ⁺ type source region 108. This current is very small because it is only due to the amount of charge accumulated in the floating gate 104.
As a result, the floating gate 104 is brought into an electrically neutral state in which there is no charge or a positive state in which excessive electrons are extracted. This state corresponds to "1" of the data.

Referring to FIGS. 19 and 24, when data is read after writing the data, V _cc (up to 5 V) is applied to control gate 106 and 1 V is applied to n ⁺ type drain region 110. 0V is applied to the ⁺ type source region 108. Then, the written data is discriminated depending on whether the threshold voltage V _th of the memory cell transistor is higher or lower than V _cc . That is, in the data write state, the threshold voltage V _th of the memory cell transistor is set to be higher than V _cc (5V). As a result, even if _Vcc (5V) is applied in the data write state, the memory cell transistor does not turn on but remains off. Then, in the data erased state, the threshold voltage V _th of the memory cell transistor is VV above OV.
Set to be smaller than _cc (5V). As a result, when _Vcc (5V) is applied in the data erased state,
The memory cell transistor is turned on. In this way
Determine the written data.

25 to 36 are sectional views for explaining the manufacturing process (first to twelfth steps) of the memory cell of the conventional stacked gate type flash EEPROM shown in FIG. The manufacturing process of the memory cell of the conventional stack gate type flash EEPROM will be described with reference to FIGS. 21 and 25 to 36.

First, as shown in FIG. 25, the specific resistance is 10
Boron (B) is ion-implanted into the P-type silicon semiconductor substrate 101 of about Ωcm under the conditions of 100 KeV and 4 × 10 ¹² / cm ² . Then, by performing heat treatment at 1150 ° C. for 6 hours, a well (not shown) is formed.

Next, as shown in FIG. 26, boron (B) is added to the region separating the active region at 80 KeV and 2.5 × 10 5.
Ion implantation is performed under the condition of ¹³ / cm ² . Then, in this region, a field oxide film 102 having a thickness of about 6000Å is formed by using a selective oxidation method. 26 is a drawing in which the cross section AA in the drawing on the right side shown in FIG. 26 is shown on the left side.

Next, as shown in FIG. 27, in order to control the threshold voltage V _th of the memory cell transistor, ion implantation (channel dope) is carried out in the active region. 1
An oxide film 103 of about 00Å is formed on the entire surface. Oxide film 1
The first polycrystalline silicon layer 104 is deposited on the surface 03 of about 1000 Å. The first polycrystalline silicon layer 104 is linearly patterned at a constant pitch in the column direction (longitudinal direction) by using photolithography and anisotropic etching. That is, by performing anisotropic etching using the resist mask 118a, patterning is performed at the pitch shown in the right portion of FIG. After that, the resist mask 118a is removed.

Next, as shown in FIG. 28, an ONO film 105 is formed on the first polycrystalline silicon layer 104. ON
The second polycrystalline silicon layer 106 is formed on the O film 105 by 250.
It is formed with a thickness of about 0Å. Second polycrystalline silicon layer 1
A resist mask 118b is formed on 06.

Next, as shown in FIG. 29, the resist mask 118b is linearly patterned at a constant pitch in the row direction (horizontal direction) by using a photolithography technique. Then, using the patterned resist mask 118b, the second polycrystalline silicon layer 106 and the ONO under the second polycrystalline silicon layer 106 are formed.
The film 105 and the first polycrystalline silicon layer 104 are anisotropically etched. Thereby, the first polycrystalline silicon layer 104 is patterned to form a floating gate, and the second polycrystalline silicon layer 106 is patterned to form a control gate.

Next, as shown in FIG. 30, a region to be the drain region of the memory cell is covered with a resist mask 118c. Using the resist mask 118c as a mask, arsenic (As) is added at 0 degree, 35 KeV, 1.
Ion implantation is performed under the condition of 0 × 10 ¹⁶ / cm ² . As a result, the n ⁺ type source region 108 is formed. Further, phosphorus (p) was added at 0 degree, 50 KeV, 5.0 × 10 ¹⁴
Ion implantation under the condition of / cm ² . This gives n ⁻
The mold source region 107 is formed.

Next, as shown in FIG. 31, after removing the resist mask 118c (see FIG. 30), the n ⁺ type source region 108 is covered with the resist mask 118d. Arsenic (As) was added to the region to be the drain region at 0 degree, 35 KeV,
Ion implantation is performed under the condition of 5.0 × 10 ¹⁴ / cm ² .
As a result, the n ⁺ type drain region 110 is formed.
Further, by injecting boron (B) by 45 degrees, 50 Ke
Ion implantation is performed under the conditions of V and 3.0 × 10 ¹³ / cm ² . As a result, the embedded p ⁺ for improving the writing characteristics
The layer 109 is formed.

Next, as shown in FIG. 32, an oxide film (not shown) is formed with a thickness of about 1500 Å. Sidewalls 1 are formed on the sidewalls of the floating gate 104 and the control gate 106 by using anisotropic etching.
11 is formed. The sidewall 111 is used to form the LDD structure of the MOS transistor in the peripheral circuit region.

Next, as shown in FIG. 33, the oxide film 112.
Is formed over the entire surface to a thickness of about 1500Å. Further, the nitride film 113 is formed with a thickness of about 500 Å.

Next, as shown in FIG. 34, boron (B)
An oxide film containing phosphorus and phosphorus (P) is formed with a thickness of about several thousand Å, and heat treatment and etching are performed to form an interlayer film 114. A resist mask 119 is formed in a predetermined region on the interlayer film 114 by using the photoengraving technique. By using the resist mask 119 to perform isotropic etching of the interlayer film 114, the tapered shape 1 is formed in the opening 120.
An interlayer film 114 having 14a is formed.

Next, as shown in FIG. 35, anisotropic etching is further performed using resist mask 119 as a mask to form an opening on n ⁺ type drain region 110.

Next, as shown in FIG. 36, after the resist mask 119 (see FIG. 35) is removed, the above-mentioned n is opened.
^The titanium layer 115 is electrically connected to the ⁺ type drain region 110, and a titanium layer 115 of 500 Å is formed so as to extend on the interlayer insulating film 114.
It is formed with a certain thickness.

Finally, as shown in FIG. 21, the titanium layer
Aluminum layer 116 on 115 with a thickness of about 5000Å
It is formed only by. Using photo engraving technology and chemical processing,
The laminated film of the aluminum layer 115 and the aluminum layer 116 is patterned.
N ⁺Type drain region 110 and
The contacting bit lines (115, 116) are formed.

[0026]

As described above, in the conventional flash EEPROM, since one memory cell is formed by one transistor, there is no selection transistor unlike the conventional EEPROM. Therefore, at the time of writing information, the write voltage 7 is applied to all the drain regions of the memory cell transistors connected to the same bit line.
V is applied. That is, in the selected cell selected for writing information, 7 V is applied to the drain region via the bit line BL ₁ and 12.5 V is applied to the control gate via the word line WL ₁ . At this time, 7V is also applied to the drain region of the non-selected non-selected cell via the bit line BL ₁ . 7V in drain area
0V is applied to the control gate of the non-selected cell to which is applied. Here, when this non-selected cell is in the written state, electrons are injected into the floating gate. That is, the potential of the floating gate is about -3V. When 7V is applied to the drain region of the non-selected cell and 0V (non-selected state) is applied to the control gate in this state, a high electric field as high as 10 MV / cm is generated between the floating gate and the drain region. This causes a drain disturb which will be described in detail below.

FIG. 38 is a sectional structural view for explaining the drain disturb by FN tunneling. FIG. 39 is a cross-sectional structure diagram for explaining the drain disturb due to the band-to-band tunnel.

First, referring to FIG. 38, 10 is provided between floating gate 104 and n ⁺ type drain region 110.
When a high electric field as high as MV / cm is generated, the electrons injected into the floating gate 104 are extracted to the n ⁺ type drain region 110 by the FN tunneling phenomenon. As a result, there is a problem that the memory cell is erased. This is so-called FN tunneling drain disturb.

Next, referring to FIG. 39, when a high electric field is generated between floating gate 104 and n ⁺ type drain region 110, band-to-band tunnel occurs and holes are generated. The generated hole is floating gate 1
By injecting into 04, the result is the same as the state in which electrons are extracted. As a result, there is a problem that the cells are erased. This is the so-called drain disturb due to the band-to-band tunnel.

Such a drain disturb phenomenon is
This is a problem peculiar to the flash EEPROM in which there is no selection transistor and only one transistor exists in one memory cell.

The present invention has been made to solve the above problems, and one object of the present invention is to occur in a non-selected cell at the time of writing information in a semiconductor memory device (flash EEPROM). It is to effectively reduce the drain disturb phenomenon.

Another object of the present invention is to alleviate a high electric field generated between a drain region and a floating gate when writing information in a flash EEPROM.

[0033]

A semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device capable of electrically writing and erasing information, comprising a first conductivity type semiconductor substrate and a semiconductor substrate on the semiconductor substrate. A second conductivity type first and second impurity regions formed at a predetermined interval so as to sandwich the channel region, and a charge storage electrode formed on the channel region via a first insulating film, A control electrode formed on the charge storage electrode via a second insulating film, a bit line is electrically connected to the second impurity region, and the second impurity region is the charge storage electrode. When the length extending from the lower side end of the substrate in the direction along the channel length is A and the depth in the direction perpendicular to the main surface of the semiconductor substrate is B, the following ranges are formed. ..

B / A ≧ 2 A method of manufacturing a semiconductor memory device according to claim 2, wherein a step of forming a charge storage electrode via a first insulating layer in a predetermined region on the main surface of the semiconductor substrate, and a charge storage electrode. A step of forming a control electrode on the second insulating layer via a second insulating layer, a step of forming a first impurity region by ion-implanting an impurity into a semiconductor substrate using the control electrode as a mask, a control electrode and a charge storage electrode A side wall insulating film is formed on the side wall portion of the substrate, and a second impurity region to be electrically connected to the bit line is formed by ion-implanting impurities into the semiconductor substrate using the control electrode and the side wall insulating film as a mask. And the process.

[0035]

In the semiconductor memory device according to the first aspect of the present invention, the second impurity region electrically connected to the bit line has a length A extending from below the side end portion of the charge storage electrode in the direction along the channel length. , B / A ≧ 2 when the depth in the direction perpendicular to the main surface of the semiconductor substrate is B, so that the charge storage electrode and the second impurity region (drain region) are formed. The area of the region where and overlap with each other is reduced as compared with the conventional case.

In the method of manufacturing a semiconductor memory device according to a second aspect, a sidewall insulating film is formed on sidewall portions of the control electrode and the charge storage electrode, and impurities are ion-implanted into the semiconductor substrate using the control electrode and the sidewall insulating film as a mask. As a result, the second impurity region to which the bit line is to be electrically connected is formed, so that the second impurity region has a shape that is laterally moved by the width of the sidewall insulating film. Thereby, the charge storage electrode and the second impurity region (drain region)
The area of the region where and overlap with each other is reduced as compared with the conventional case.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view showing a memory cell portion of a flash EEPROM according to an embodiment of the present invention.

Referring to FIG. 1, the memory cell portion of the present embodiment is a P-type silicon semiconductor substrate 1 and n ⁺ formed on the main surface of P-type silicon semiconductor substrate 1 at a predetermined distance.
Type source region 8 and n ⁺ type drain region 10, and n ⁺
N ⁻ type source region 7 formed to cover the type source region 8 for relaxing electric field concentration, and a p ⁺ layer formed to cover the n ⁺ type drain region 10 for improving writing characteristics 9, a gate oxide film 3 having a thickness of about 100 Å formed on the channel region 17 located between the n ⁺ type source region 8 and the n ⁺ type drain region 10, and formed on the gate oxide film 3. The ONO film 5 and the control gate 6 made of a polycrystalline silicon layer formed on the ONO film 5 are provided. Here, the ONO film 5 is formed by CVD-
SiO ₂ film (100 Å) and CVD formed on it
Nitride film (100Å) and CVD-S formed on it
It is composed of an iO ₂ film (100 Å).

On both sides of the control gate 6 and the floating gate 4, n ⁺ type drain regions 10 are formed.
The sidewalls 11a used for forming the are formed. The thickness of this sidewall 11a is 250 to 5
It is about 00Å. A sidewall 11b for forming the LDD structure of the transistor in the peripheral circuit region is formed so as to cover the sidewall 11a. The thickness of the sidewall 11b is about 1500 Å. An oxide film 12 is formed so as to cover the entire surface. A nitride film 13 is formed on the oxide film 12. An interlayer film 14 is formed on the nitride film 13. Oxide film 12,
Openings are formed in the nitride film 13 and the interlayer film 14 in regions located on the n ⁺ type drain region 10, respectively. In the opening, the titanium layer 15 is electrically connected to the n ⁺ type drain region 10 and extends on the interlayer film 14.
Are formed. An aluminum layer 16 is formed on the titanium layer 15.

Here, in the present embodiment, the area of the region where the n ⁺ type drain region 10 and the floating gate 4 overlap is reduced as compared with the conventional one. FIG. 2 shows an n ⁺ type drain region 1 which constitutes the memory cell transistor of this embodiment.
FIG. 6 is a cross-sectional view for explaining the degree of overlap between 0 and the floating gate 4. Referring to FIG. 2, n ⁺ type drain region 10 has a length A extending from the lower side end of floating gate 4 in the direction along the channel length and a depth from the surface of P type silicon semiconductor substrate 1. When it is set to B, it is formed to have the following range.

B / A ≧ 2 In the prior art, the length extending from below the side end of the floating gate 4 in the direction along the channel length is A ₀ , and the depth from the surface of the p-type silicon semiconductor substrate 1 is B. In this case, B / A ₀ ≈1.5.

As described above, in this embodiment, the area of the region where the drain disturb occurs can be reduced by reducing the area of the region where the n ⁺ type drain region 10 and the floating gate 4 overlap. As a result, in the flash EEPROM, it is possible to effectively reduce the drain disturb phenomenon that occurs in a non-selected cell when writing information. In addition, the n ⁺ drain region 10
Since the real electron generating region at the time of writing is located under the floating gate 4 even if the writing element is moved in parallel, the writing characteristic is not deteriorated. Further, since the FN tunneling region does not exist below the floating gate 4, the drain disturb due to FN tunneling is significantly reduced. Also, the band-to-band tunnel area
As it becomes narrower and its impurity concentration becomes lower, n
^The effect more than the effect proportional to the parallel movement amount of the ⁺ drain region 10 (the reduction amount of the overlapping portion of the floating gate 4 and the n ⁺ drain region) is obtained.

Incidentally, the n ⁺ type drain region 10 having such a structure has a sidewall 11a as described later.
It can be easily formed by using.

FIG. 3 is a characteristic diagram comparing the drain disturb characteristic of this embodiment with that of the conventional one. Referring to FIG. 3, the horizontal axis represents drain voltage Vd, and the vertical axis represents threshold voltage V _{th due} to the drain disturb phenomenon.
It takes the disturb time until it drops from V to 6.5V. As is clear from this figure, in this embodiment, the disturb time (second) is improved by about 5 digits compared to the conventional case. That is, when the drain voltage is 6.0 V, for example, the disturb time is 10 msec in the related art, whereas it is 100 se in the present embodiment.
c (10 ⁵ msec).

4 to 14 are sectional views showing an embodiment of the manufacturing process (first to eleventh steps) of the memory cell of the stack gate type flash EEPROM of the present embodiment shown in FIG. .. An embodiment of the manufacturing process of the memory cell of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 4, the specific resistance is 10Ω.
Boron (B) is added to the P-type silicon semiconductor substrate 1 of about cm.
Is ion-implanted under the conditions of 100 KeV and 4 × 10 ¹² / cm ² . Then, by performing heat treatment at 1150 ° C. for 6 hours, a well (not shown) is formed.

Next, as shown in FIG. 5, boron (B) is added to the region separating the active region at 80 KeV and 2.5 × 10 5.
Ion implantation is performed under the condition of ¹³ / cm ² . Then, in this region, a field oxide film 2 having a thickness of about 6000Å is formed by using a selective oxidation method. 5 is a drawing showing a cross section AA in the drawing on the right side shown in FIG. 5 on the left side.

Next, as shown in FIG. 6, in order to control the threshold voltage V _th of the memory cell transistor, ion implantation (channel dope) is performed in the active region. 10
An oxide film 3 having a thickness of 0Å is formed on the entire surface. A first polycrystalline silicon layer 4 is deposited on the oxide film 3 to a thickness of about 1000Å. The first polycrystalline silicon layer 4 is linearly patterned in the column direction (longitudinal direction) at a constant pitch by using photolithography and anisotropic etching. That is, anisotropic etching is performed using the resist mask 18a to perform patterning at the pitch shown in the right side portion of FIG. After that, the resist mask 18a is removed.

Next, as shown in FIG. 7, an ONO film 5 is formed on the first polycrystalline silicon layer 4. A second polycrystalline silicon layer 6 is formed on the ONO film 5 with a thickness of about 2500Å. A resist mask 18b is formed on the second polycrystalline silicon layer 6.

Next, as shown in FIG. 8, a resist mask is patterned linearly in the row direction (horizontal direction) at a constant pitch using the photolithography technique. Then, using the patterned resist mask 18b, the second polycrystalline silicon layer 6, the ONO film 5 thereunder and the first polycrystalline silicon layer 4 are anisotropically etched. In this way, the first polycrystalline silicon layer 4 forms a floating gate and the second polycrystalline silicon layer 6 is patterned to form a control gate. After that, the resist mask 18b is removed.

Next, as shown in FIG. 9, a region serving as the drain region of the memory cell is covered with a resist mask 18c.
Using the resist mask 18c as a mask, arsenic (As) is applied to the source region at 0 degrees, 35 KeV, 1.0 × 1.
Ion implantation is performed under the condition of 0 ¹⁶ / cm ² . As a result, the n ⁺ type source region 8 is formed. Further, phosphorus (P) was added at 0 degree, 50 KeV, 5.0 × 10 ¹⁴ / cm ^2.
Ion implantation is performed under the conditions of. As a result, the n ⁻ type source region 7 is formed.

Next, as shown in FIG. 10, after removing the resist mask 18c (see FIG. 9), an oxide film having a thickness of about 250 to 500 Å is formed on the entire surface by the CVD method. By performing anisotropic etchback, sidewalls 11a are formed on both side wall portions of the floating gate 4 and the control gate 6.

Next, as shown in FIG. 11, a region serving as a source region of the memory cell is covered with a resist mask 18d.
Using the resist mask 18d as a mask, arsenic (As) is added to the region to be the drain region at 0 degrees, 25 KeV, 5.0 ×.
Ion implantation is performed under the condition of 10 ¹⁴ / cm ² . As a result, the n ⁺ type drain region 10 is formed. Furthermore, boron (B) is injected at 45 degrees by rotation at 50 KeV, 3.0 ×.
Ion implantation is performed under the condition of 10 ¹³ / cm ² . As a result, a buried p ⁺ layer 9 for improving the writing characteristics is formed. Here, since the n ⁺ type drain region 10 is formed by using the sidewall 11a as a mask, the n ⁺ type drain region 10 has a shape laterally moved by the width of the sidewall 11a as compared with the conventional case. As a result, the area of the region where the floating gate 4 and the n ⁺ -type drain region 10 overlap is reduced as compared with the conventional case. As a result, the drain disturb phenomenon that occurs in the non-selected cells at the time of writing information is effectively reduced.

Next, as shown in FIG.
After removing d (see FIG. 11), an oxide film (not shown) is formed with a thickness of about 1500 Å. The sidewalls 11b are formed on the sidewalls of the floating gate 4 and the control gate 6 by using anisotropic etching.
The sidewall 11b is for forming the LDD structure of the MOS transistor in the peripheral circuit region.
An oxide film 12 is formed on the entire surface with a thickness of about 1500Å.
Further, a nitride film 13 is formed with a thickness of about 500Å.

Next, as shown in FIG. 13, boron (B)
And an oxide film containing phosphorus (B) are formed with a thickness of about several thousand Å. The interlayer film 14 is formed by performing heat treatment and etching. A resist mask 19 is formed in a predetermined region on the interlayer film 14 by using the photoengraving technique. The interlayer film 14 is isotropically etched using the resist mask 19 to form the interlayer film 14 having the tapered shape 14a in the opening 20. Then, as shown in FIG.
Anisotropic etching is further performed using resist mask 19 as a mask to form an opening on n ⁺ type drain region 10.

Finally, as shown in FIG. 1, a titanium layer 15 having a thickness of about 500 Å is formed on the opened n ⁺ type drain region 10 so as to be electrically connected and extend on the interlayer film 14. To do. Then, the aluminum layer 16 is set to 500
It is formed with a thickness of about 0Å. The laminated film of the titanium layer 105 and the aluminum layer 16 is patterned using photolithography and chemical treatment. As a result, bit lines (15, 16) contacting the n ⁺ type drain region 10 are formed.

15 to 18 are sectional structural views for explaining the second embodiment of the manufacturing process of the memory cell of this embodiment shown in FIG. Referring to FIGS. 15 to 18, in the manufacturing process of the second embodiment, first, referring to FIG.
As shown in FIG. 5, the drain region of the memory cell is covered with the resist mask 21. Arsenic (A
s) at 0 degree, 35 KeV, 1.0 × 10 ¹⁶ / cm ²
Ion implantation is performed under the conditions of. As a result, the n ⁺ type source region 8 is formed. Furthermore, phosphorus (p) is 0 degrees, 5
Ion implantation is performed under the conditions of 0 KeV and 5.0 × 10 ¹⁴ / cm ² . As a result, the n ⁻ type source region 7 is formed.

Next, as shown in FIG. 16, the n ⁺ type source region 8 is covered with a resist 22. Boron (B) is added to the region to be the drain region at 45 degrees, 50 KeV, and 3.0 × 1.
Implanted at 0 ^{1 3} / cm ² conditions. As a result, the p ⁺ layer 9 is formed.

Next, as shown in FIG. 17, after removing the resist mask 22 (see FIG. 16), 250 is formed on both side wall portions of the floating gate 4 and the control gate 6.
The sidewall 11a is formed with a thickness of about 500 Å.

Next, as shown in FIG. 18, a resist 22 is formed so as to cover the n ⁺ type source region 8. Using the resist 22 and the sidewall 11a as a mask, p ⁺
Arsenic (As) is added to the layer 9 at 0 ° C., 35 KeV, 5.0 ×.
Ion implantation is performed under the condition of 10 ¹⁴ / cm ² . As a result, the n ⁺ type drain region 10 is formed. Thus, only the n ⁺ -type drain region 10 is covered with the sidewall 11
By forming a as a mask, the same effect as that of the first embodiment of the memory cell manufacturing process shown in FIGS. 4 to 14 can be obtained. That is, the area of the region where the floating gate 4 and the n ⁺ type drain region 10 overlap can be reduced by the thickness of the sidewall 11a as compared with the conventional case.

[0062]

According to the semiconductor memory device of the first aspect,
The second impurity region electrically connected to the bit line has a length A extending from below the side end portion of the charge storage electrode in the direction along the channel length, and a depth perpendicular to the main surface of the semiconductor substrate. By forming so that B / A ≧ 2 when B is B, the area of the region where the charge storage electrode and the second impurity region (drain region) overlap can be reduced compared to the conventional case. As a result, it is possible to effectively reduce the drain disturb phenomenon that occurs in the non-selected cells when writing information in the flash EEPROM.

In the method of manufacturing a semiconductor memory device according to a second aspect, a sidewall insulating film is formed on sidewall portions of the control electrode and the charge storage electrode, and impurities are ion-implanted into the semiconductor substrate using the control electrode and the sidewall insulating film as a mask. By forming the second impurity region to which the bit line should be electrically connected, the area of the region where the charge storage electrode and the second impurity region overlap is smaller than the conventional one by the width of the sidewall insulating film. Will be reduced. As a result, when writing information, a high electric field generated between the second impurity region and the floating gate can be relaxed.

[Brief description of drawings]

FIG. 1 is a flash EEPRO according to an embodiment of the present invention.
FIG. 6 is a cross-sectional structural view showing an M memory cell.

FIG. 2 is a cross-sectional view for explaining a degree of overlap between an n ⁺ type drain region 10 and a floating gate 4 in the memory cell section shown in FIG.

FIG. 3 is a characteristic diagram comparing the drain disturb characteristics of the flash EEPROM of the present invention and a conventional flash EEPROM.

FIG. 4 is a cross-sectional view for explaining a first step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG.

FIG. 5 is a cross-sectional view for explaining a second step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG.

6 is a cross-sectional view for explaining a third step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG.

7 is a cross-sectional view for explaining a fourth step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

8 is a cross-sectional view for explaining a fifth step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG.

9 is a sectional view for explaining a sixth step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

10 is a cross-sectional view for explaining the seventh step of the embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

FIG. 11 is a cross-sectional view for explaining the eighth step of the embodiment of the manufacturing process of the flash EEPROM shown in FIG.

12 is a cross sectional view for illustrating a ninth step of the embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

13 is a sectional view for explaining a tenth step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

FIG. 14 is a cross-sectional view for explaining the eleventh step of one embodiment of the manufacturing process of the flash EEPROM shown in FIG.

15 is a cross-sectional view for explaining the eighth step of the second embodiment of the manufacturing process of the flash EEPROM shown in FIG.

16 is a sectional view for explaining a seventh step of the second embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

17 is a sectional view for illustrating a sixth step of the eighth embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

18 is a sectional view for illustrating a ninth step of the second embodiment of the manufacturing process of the flash EEPROM shown in FIG. 1. FIG.

FIG. 19 is a block diagram showing a general configuration of a conventional flash EEPROM.

20 is an equivalent circuit diagram showing a schematic configuration of the memory cell array 30 shown in FIG.

21 is a sectional structural view showing a memory cell (semiconductor memory element) including one memory cell transistor that constitutes the memory cell array shown in FIG. 20. FIG.

FIG. 22 is a cross-sectional view for explaining a data writing operation of the conventional flash EEPROM.

FIG. 23 is a cross-sectional view for explaining a data erasing operation of a conventional flash EEPROM.

FIG. 24 is a cross-sectional view for explaining a data read operation of a conventional flash EEPROM.

FIG. 25 is a cross-sectional view for explaining the first step of the manufacturing process of the conventional flash EEPROM.

FIG. 26 is a cross-sectional view for explaining the second step of the manufacturing process of the conventional flash EEPROM.

FIG. 27 is a cross-sectional view for explaining the third step of the conventional manufacturing process of the flash EEPROM.

FIG. 28 is a cross-sectional view for explaining the fourth step of the manufacturing process of the conventional flash EEPROM.

FIG. 29 is a cross-sectional view for explaining the fifth step of the conventional manufacturing process of the flash EEPROM.

FIG. 30 is a cross-sectional view for explaining the sixth step of the manufacturing process of the conventional flash EEPROM.

FIG. 31 is a cross-sectional view for explaining the seventh step of the conventional manufacturing process of the flash EEPROM.

FIG. 32 is a cross-sectional view for explaining the eighth step of the manufacturing process of the conventional flash EEPROM.

FIG. 33 is a cross-sectional view for explaining the ninth step of the conventional flash EEPROM manufacturing process.

FIG. 34 is a sectional view for explaining the tenth step of the conventional flash EEPROM manufacturing process.

FIG. 35 is a cross-sectional view for explaining the eleventh step of the manufacturing process of the conventional flash EEPROM.

FIG. 36 is a cross-sectional view for explaining a twelfth step of the conventional manufacturing process of the flash EEPROM.

FIG. 37 is an equivalent circuit diagram for explaining drain disturb in the conventional flash EEPROM.

FIG. 38 is a cross-sectional view illustrating a drain disturb caused by conventional FN tunneling.

FIG. 39 is a cross-sectional view illustrating a conventional drain disturb caused by a band-to-band tunnel.

[Explanation of symbols]

1: P-type silicon semiconductor substrate 2: field oxide film 3: gate oxide film 4: floating gate (first polycrystalline silicon layer) 5: ONO film 6: control gate (second polycrystalline silicon layer) 7: n ^- -type source region 8: n ⁺ -type source region 9: p ⁺ layer 10: n ⁺ -type drain region 11a: sidewall 11b: sidewall 13: nitride film 15: titanium layer 16: aluminum layer in the drawings, the same The reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A semiconductor memory device capable of electrically writing and erasing information, wherein a first conductive type semiconductor substrate and a channel region are sandwiched on the semiconductor substrate with a predetermined distance therebetween. Second conductivity type first and second impurity regions formed by: a charge storage electrode formed on the channel region via a first insulating film; and a second charge storage electrode formed on the charge storage electrode. A control electrode formed via an insulating film, a bit line is electrically connected to the second impurity region, and the second impurity region is below a side end portion of the charge storage electrode. From the length A extending in the direction along the channel length,
When the depth in the direction perpendicular to the main surface of the semiconductor substrate is B, it is formed in the following range:
Semiconductor memory device. B / A ≧ 2 2. A first region is provided in a predetermined region on the main surface of the semiconductor substrate.
Forming a charge storage electrode via the insulating layer of, and forming a control electrode on the charge storage electrode via a second insulating layer; ion-implanting impurities into the semiconductor substrate using the control electrode as a mask. Implanting to form a first impurity region, forming a sidewall insulating film on sidewalls of the control electrode and the charge storage electrode, and using the control electrode and the sidewall insulating film as a mask, By ion-implanting impurities into the semiconductor substrate,
And a step of forming a second impurity region to be electrically connected to the bit line.