JPH05121749A - Electrically writable and erasable semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent data stored in a non-selection memory cell from being destructed when writing is done in a selected memory cell. CONSTITUTION:First and second second conductivity type impurity regions 8a and 10a are formed in the main surface of a first conductivity type semiconductor substrate 1 and a channel region is formed between these regions 8a and 10a. A first dielectric film 3 is formed on the channel region and a charge storage electrode 4 is formed on this film 3. A control electrode 6 is formed on this electrode 4 via a second dielectric film 5. The film thicknesses of the film located directly under the end edges of the electrode 4, on the side of the region 10a, is thicker than that on the side of the region 8a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a non-volatile semiconductor memory device which can be electrically written and erased, and a method for manufacturing the same, and more particularly to electrically written information charges collectively. EEPRO that can be erased
M (Electrically Erasable and Programmable Read On
ly Memory) The present invention relates to a so-called flash EEPROM structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art An EEPROM is known as a memory device having a structure in which data can be freely programmed and which can be electrically written and erased. An EEPROM, which is composed of one transistor and is capable of electrically erasing written information charges collectively, is a so-called flash EEPROM, with reference to FIGS.
M will be described.

FIG. 18 is a block diagram showing a general structure of a flash EEPROM. As shown in FIG. 18, this flash EEPROM has a memory cell matrix 100 arranged in a matrix, an X address decoder 200, a Y gate sense amplifier 300, a Y address decoder 400, an address buffer 500, and an input / output. It includes a buffer 600 and control logic 700.

The memory cell matrix 100 has a plurality of memory transistors arranged in a matrix therein. An X address decoder 200 and a Y gate sense amplifier 300 are connected to select a row and a column of the memory cell matrix 100. The Y gate sense amplifier 300 is connected to a Y address decoder 400 which gives column selection information. An address buffer 500 for temporarily storing address information is connected to each of the X address decoder 200 and the Y address decoder 400.

An input / output buffer 600 for temporarily storing input / output data is connected to the Y gate sense amplifier 300. Address buffer 500 and input / output buffer 60
A control logic 700 for controlling the operation of the flash EEPROM is connected to 0. The control logic 700 performs control based on a chip enable signal, an output enable signal and a program signal.

FIG. 19 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG. As shown in FIG. 19, a plurality of word lines W extending in the row direction are provided.
L _1, WL _2, ... and WL _i, a plurality of bit lines BL _1, BL ₂ extending in the column direction, ... and BL _i are arranged perpendicular to each other, and thereby constitute a matrix. Memory transistors Q ₁₁ , Q ₁₂ ... Q _ii each having a floating gate electrode are arranged at the intersections of the word lines and the bit lines.

The drain diffusion region of each memory transistor is connected to each bit line, and the control gate electrode of the memory transistor is connected to each word line. The source diffusion region of the memory transistor is connected to each source line S ₁ , S ₂ , ... The source diffusion regions of the memory transistors belonging to the same row are connected to each other as shown in the figure, and the source lines S ₁ and S arranged on both sides are connected.
₂ , is connected to.

FIG. 20 is a schematic plan view showing a flash EEPROM called a conventional stack gate type flash EEPROM. 21 is a sectional view taken along the line AA of FIG. The structure of the conventional flash EEPROM will be described with reference to these drawings.

Referring to FIG. 20, control gate electrodes 37 are formed as word lines connected to each other and extending in the lateral direction (row direction). The bit line 39 is arranged orthogonal to the word line 37, and connects the drain diffusion regions 32 arranged in the vertical direction (column direction) to each other. The bit line 39 is electrically connected to each drain diffusion region 32 by a drain contact 40. Referring to FIG. 21, the bit line 39 is the smooth coat film 4
It is formed on top of 1. Referring to FIG. 20, source diffusion region 33 extends in the direction in which word line 37 extends and is formed in a region surrounded by word line 37 and element isolation oxide film 30. Each drain diffusion region 32 is formed in a region surrounded by the word line 37 and the element isolation oxide film 30.

Referring to FIG. 21, a drain diffusion region 32 and a source diffusion region 33 are formed on the main surface of p type silicon substrate 31 with a space therebetween. In the region sandwiched between the drain diffusion region 32 and the source diffusion region 33, the control gate electrode 37 and the floating gate electrode 35 are formed so that a channel region is formed.
And are formed. Floating gate electrode 35
Is formed on the p-type silicon substrate 31 via a thin oxide film 34 having a film thickness of about 100 Å. The control gate electrode 37 is connected to the floating gate electrode 3 so as to be electrically separated from the floating gate electrode 35.
5 is formed on the insulating layer 5 via the interlayer insulating layer 36. Floating gate electrode 35 and control gate electrode 37
Are formed of a polycrystalline silicon layer. The thermal oxide film 38 is formed by thermally oxidizing the surfaces of the p-type silicon substrate 31 and the polycrystalline silicon layer forming the floating gate electrode 35 and the control gate electrode 37. A smooth coat film 41 made of an oxide film or the like is formed so as to cover the floating gate electrode 35 and the control gate electrode 37.

Flash EE having the above structure
The operation of the PROM will be described below.

First, in the write operation, the drain expansion is performed.
The voltage V of about 6 to 8 V in the dispersion area 32 _D, Control
The voltage V of about 10 to 15 V is applied to the gate electrode 37._GIs applied
It This voltage V_D, V_GApplication of the
The avalanche breakdown phenomenon occurs near the region 32 and the oxide film 34.
woken up. As a result, there is high energy in this vicinity.
Generate electrons. Some of this electron is control
Voltage V applied to gate electrode 37_GDue to the electric field
Are attracted to the floating gate electrode 35. This
In this way, the floating gate electrode 35
When storage is done, the control gate transistor
Threshold voltage V_thBecomes higher. This threshold V_thWhere
A state in which a state that is higher than a fixed value is written, “0”
Called.

Next, in the erase operation, the source diffusion region
Voltage V of about 10-12V in the area 33 _SIs applied,
Troll gate electrode 37 is ground potential, drain diffusion region
33 is kept floating. Source diffusion region 3
Voltage V applied to 3_SDue to the electric field caused by
The electrons in the insulating gate electrode 35 pass through the thin oxide film 34 by F-.
Pass by N (Fowler-Nordheim) tunnel phenomenon
It In this way, in the floating gate electrode 35
Of electrons in the control gate
Transistor threshold voltage V_thWill be lower. This threshold
Value voltage V_thIs lower than the specified value, the
The state is called "1". Source of each memory transistor
Are connected to each other as shown in FIG.
This erase operation makes it possible to erase all memory cells at once.
Can be done.

Further, in the read operation, the voltage V _G ′ of about 5 V is applied to the control gate electrode 37 and the voltage V _D ′ of about 1 to 2 V is applied to the drain diffusion region 32.
At that time, the above "1" or "0" is determined depending on whether or not a current flows in the channel region of the control gate transistor, that is, whether the control gate transistor is in the ON state or the OFF state.

[0015]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the PROM, referring to FIG. 21, for example, when memory cell (1) is selected and written, 6 to 8 V is applied to drain diffusion region 32 and 10 to control gate electrode 37.
Writing to the floating gate electrode 35 of the memory cell (1) is performed by applying a voltage of about 15V. After that, also when the memory cell (2) is selected and written, the drain diffusion region 32 in the memory cell (2) is also written.
A voltage similar to the above is applied to the control gate electrode 37. At this time, the memory cell (1) and the memory cell (2) share the drain diffusion region 32,
When writing to the memory cell (2), a voltage of 6 to 8 V is applied to the drain diffusion region 32. On the other hand, since electric charges are accumulated in the floating gate electrode 35 of the memory cell (1), it is charged to about -3V, for example.

As a result, a high electric field is generated between the floating gate electrode 35 of the memory cell (1) and the drain diffusion region 32. If the charge application time for writing is, for example, about 10 μsec, a high electric field is applied to the oxide film 34 in the memory cell (1) for about 10 μsec when writing to the memory cell (2). It will be. Similarly to this, the memory cell (3),
Even when writing to the memory cell (4), a high electric field is applied to the non-selected memory cell, for example, the oxide film 34 in the memory cell (1).

On the other hand, the lower end corner portion of the floating gate electrode 35 has a sharp shape. In such a case, as shown in FIG. 21, electric field concentration is likely to occur at the lower corner portion. Therefore, as described above, the electrons stored in the non-selected floating gate electrode 35 may be extracted to the drain diffusion region 32 by FN (Fowler-Nordheim) tunneling. Further, due to the above-mentioned high electric field, the drain diffusion region 3
In the vicinity of 2, the situation in which holes generated by band-to-band tunneling are injected into the floating gate electrode 35 easily occurs. As a result, the number of electrons stored in the floating gate electrode 35 in the non-selected cell decreases, and the problem that the written data is destroyed with a certain probability occurs. This phenomenon is called "drain disturb phenomenon".

On the other hand, in Japanese Patent Laid-Open No. 2-284473, by rounding the lower corners of the floating gate electrode in the flash EEPROM, the electric field concentration is alleviated, thereby preventing variations in erase characteristics and increasing the number of times of rewriting. However, there is no description about prevention of the above-mentioned "drain disturb phenomenon". Further, in this case, as shown in FIG. 22, the lower end corner portion 57E of the floating gate electrode 57 is formed.
Are rounded symmetrically. Note that, as shown in FIG. 22, this flash EEPROM has a p-type semiconductor substrate 51, an n-type semiconductor region 52, and a p-type well region 53.
An n ⁺ type semiconductor region 54, a p type semiconductor region 55,
n ⁺ semiconductor region 56 and floating gate electrode 57
A second gate oxide film 58, a control gate electrode 59, and a sidewall 60.

The present invention has been made to solve the above problems, and is an electrically writable and erasable semiconductor memory device capable of effectively preventing the above-mentioned "drain disturb phenomenon" and the same. It is intended to provide a manufacturing method.

[0020]

A semiconductor memory device according to the present invention has a semiconductor substrate of a first conductivity type having a main surface, and a predetermined channel region is formed on the main surface of the semiconductor substrate. First and second impurity regions of the second conductivity type are formed at intervals. Then, a first dielectric film is formed on the channel region, and a charge storage electrode layer is formed on the first dielectric film. A control electrode layer is formed on the charge storage electrode layer with a second dielectric film interposed. The thickness of the first dielectric film immediately below the edge of the charge storage electrode layer is the first
Is thicker on the second impurity region side than on the impurity region side.

A method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming a first dielectric film on a main surface of a first conductivity type semiconductor substrate, and an electric charge on the first dielectric film. A step of forming a storage electrode layer, a step of forming a control electrode layer on the charge storage electrode layer with a second dielectric film interposed, and a first and second step using the control electrode layer as a mask. And forming a second conductivity type impurity region on the main surface of the semiconductor substrate with a space between the first conductivity type impurity region and the first impurity region side immediately below the edge of the charge storage electrode layer. And a step of increasing the thickness of the first dielectric film, and a second thickness that is thicker than the first thickness on the second impurity region side immediately below the edge of the charge storage electrode layer. Thus, the step of increasing the film thickness of the first dielectric film is provided.

[0022]

According to the semiconductor memory device of the present invention, the thickness of the first dielectric film formed under the charge storage electrode is different on the first and second impurity region sides. Therefore, the film thickness of the first dielectric film can be varied according to the function required for each impurity region.
As a result, a high electric field is applied to one of the impurity regions, and when writing to one of the adjacent charge storage electrodes, even if the other is in the non-selected state, the charge is stored in the non-selected charge storage electrode. The thickness of the first dielectric film can be set so as not to adversely affect the generated electrons.
Therefore, in the unselected memory cell,
The disturb phenomenon "is effectively prevented.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view of a memory cell in a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, drain diffusion region 10 and source diffusion region 8 are formed on the main surface of p-type silicon substrate 1 with a channel region interposed therebetween.
The oxide film 3 is formed on the channel region, and the floating gate electrode 4 is formed on the oxide film 3.

The thickness of the oxide film 3 depends on the source diffusion region 8
Since the drain diffusion region 10 side and the drain diffusion region 10 side are different, the shape of the bottom corner portion of the floating gate electrode 4 is
The source diffusion region 8 side and the drain diffusion region 10 side have different asymmetric shapes. A control gate electrode 6 is formed on the floating gate electrode 4 with an interlayer insulating layer 5 interposed therebetween. In addition, on the sides of the control gate electrode 6 and the floating gate electrode 4,
A sidewall oxide film 11 formed when forming the peripheral circuit is formed.

An oxide film 12 is formed on the control gate electrode 6, the side wall oxide film 11 and the source diffusion region 8 except a predetermined region on the drain diffusion region 10, and a nitride film 13 is formed thereon. Has been done. An interlayer flattening film 14 is formed on the nitride film 13. On the interlayer flattening film 14 and the drain diffusion region 10,
A titanium film 18 is formed. An aluminum wiring layer 19 is formed on the titanium film 18. The titanium film 18 and the aluminum wiring layer 19 form a bit line.

Next, referring to FIG. 2 to FIG. 15, the first to fourteenth steps of the manufacturing process of the above embodiment will be described.

First, as shown in FIG. 2, boron (B) is added to the p-type silicon substrate 1 at 100 KeV and 1.0 × 10 ^13.
/ Cm ² conditions. Then, a well (not shown) is formed by driving impurities at 1180 ° C. for 6 hours. After that, boron (B) for ensuring the isolation characteristic is applied to the area for isolating the active area at 80 KeV and 2.5.
By implanting under the condition of × 10 ¹³ / cm ² and selectively oxidizing this region, an element isolation oxide film (not shown) having a thickness of about 7500 Å is formed.

Next, as shown in FIG. 3, an oxide film 3 of about 100 Å is formed on the entire surface of the p-type silicon substrate 1, and a channel is formed in the channel region in order to control the threshold voltage V _th of the memory cell. Do the doping. Then, a first polysilicon layer 4 having a thickness of about 1000Å is formed on the oxide film 3, and a resist 7a is deposited thereon. Then, using this resist 7a, the first polysilicon layer 4 is patterned in the bit line direction at a constant pitch by photolithography and anisotropic etching. Then, the resist 7a is removed.

Next, referring to FIG. 4, an oxide film having a film thickness of about 100Å is formed on the first polysilicon layer 4 by the CVD method, and a film thickness of 100Å is formed thereon by the CVD method. A nitride film having a thickness of about 100 Å is formed on the nitride film by CVD. The interlayer insulating layer 5 is constituted by these. Then, the second polysilicon layer 6 having a thickness of about 2500 Å is formed on the interlayer insulating layer 5.
And a resist 7 is formed on the second polysilicon layer 6.
deposit b.

Then, as shown in FIG. 5, the resist 7b is linearly patterned at a constant pitch in the lateral direction by using photolithography. Using this resist 7b as a mask, the second polysilicon layer 6, the interlayer insulating layer 5 thereunder and the first polysilicon layer 4 are anisotropically etched. As a result, the first polysilicon layer 4 forms the floating gate electrode 4, and the second polysilicon layer 6 forms the control gate electrode 6.

Then, as shown in FIG. 6, the resist 7b
Then, the oxide film 20 is formed on the entire surface by the CVD method, and the nitride film 21 is formed on the oxide film 20 by the CVD method. Then, by patterning using photolithography and anisotropic etching, as shown in FIG.
Nitride film 21 on the region to be the drain diffusion region 10
To remove.

Then, a region which becomes the drain diffusion region 10.
Arsenic (As) 35 KeV, 5.0 × 10¹⁴/ Cm
²Implanted under the conditions of and then embedded to improve writing characteristics
Only P ⁺Boron (B) for forming the diffusion layer is tilted at 45 degrees.
Rotational ion implantation method is used, 50 KeV, 3.0 × 1
0¹³/ Cm²Inject under the conditions of. It drains
The diffusion region 10 is formed. Therefore, the drain diffusion region
Area 10 is n by arsenic (As) implantation.⁺Impurity diffusion region
(Not shown) and p by boron (B) implantation⁺Diffusion layer (figure
(Not shown) and.

Then, as shown in FIG. 8, thermal oxidation treatment is performed to oxidize floating gate electrode 4, control gate electrode 6, interlayer insulating layer 5 and oxide film 3 on the side of drain diffusion region 10. As a result, the interlayer insulating layer 5 and the oxide film 3 grow and their thickness increases. Then, as shown in FIG. 9, the nitride film 21 is removed.

Next, as shown in FIG. 10, a region serving as a drain diffusion region in the memory cell is covered with a resist 7c. Then, using the resist 7c as a mask, arsenic (As) is added to the region serving as the source diffusion region at 35 KeV,
Implantation is performed under the condition of 1.0 × 10 ¹⁶ / cm ² , and phosphorus (P) is further implanted under the conditions of 50 KeV and 5.0 × 10 ¹⁴ / cm ² . Thereby, the source diffusion region 8 is formed.
Therefore, the source diffusion region is composed of an n ⁺ impurity diffusion region (not shown) formed by implantation of arsenic (As) and an n ⁻ impurity diffusion region (not shown) formed by implantation of phosphorus (P). Become.

Next, as shown in FIG. 11, after the oxide film 20 and the nitride film 21 are removed, the entire surface is subjected to thermal oxidation treatment. As a result, the oxide film 3 and the interlayer insulating layer 5 on the source diffusion region 8 side also grow, and the thickness thereof increases. At this time, the method of oxidizing the oxide film 3 differs depending on the conditions of the thermal oxidation process and the concentration of the source diffusion region 8 and the drain diffusion region 10. That is, depending on the above conditions, the thickness of the oxide film 3 may be thicker on the source diffusion region 8 side, and the drain diffusion region 10 may be thickened.
It is possible that the side becomes thicker.

Here, the shape of the floating gate electrode 4 and the film thickness of the oxide film 3 after the thermal oxidation process will be described in more detail with reference to FIGS. 16 and 17. FIG.
17 and 18 are enlarged cross-sectional views schematically showing the memory cell. Note that for convenience, the oxide film 3 and the interlayer insulating layer 5 are
The boundary line in the vicinity of the floating gate electrode 4 is omitted. The drain diffusion region 10 is composed of an n ⁺ impurity diffusion region 10a and ap ⁺ diffusion region 10b, and the source diffusion region 8 is composed of an n ⁺ impurity diffusion region 8a and an n ⁻ impurity diffusion region 8b. ..

In FIG. 16, the thickness t ₁ of the oxide film 3 immediately below the edge of the floating gate electrode 4 on the drain diffusion region 10 side is smaller than the thickness t ₂ of the oxide film 3 immediately below the edge on the source diffusion region side. Is also large. In this case, as shown in FIG. 18, n on the drain diffusion region 10 side is
^At the interface between the ⁺ impurity diffusion region 10a and the p ⁺ diffusion layer 10b, the thickness t ₃ of the oxide film 3 at the portion closest to the floating gate electrode 4 is n on the source diffusion region 8 side.
^{+ The} amount of oxidation is set so that it becomes larger than the film thickness t ₄ of the oxide film 3 in the portion where the impurity diffusion region 8a and the floating gate electrode 4 are closest.

At this time, erasing is performed by FN tunneling.
Since it is done, t_FourCan't be too thick
However, since writing is performed by the avalanche breakdown phenomenon, t
₃Is t _FourIt can be thicker than. In addition, FIG.
Is the above t₂Is t₁Is assumed to be larger than
However, even in this case, the impurity diffusion region is formed.
Due to the position, t₃Is t_FourGetting bigger than
It From the above, depending on the conditions such as thermal oxidation treatment, t₁When
t₂It is not unthinkable if the magnitude relationship of
But t₁And t₂The size of is basically different. sand
That is, at the bottom corner of the floating gate electrode 4.
The shape is asymmetric.

In this case, what is important in the present invention is that
The film thickness of the oxide film 3 in the overlapping portion of the n ⁺ impurity diffusion region 10a and the floating gate electrode 4 and the shape of the lower end corner portion of the floating gate electrode 4.
The film thickness of the oxide film 3 becomes thick due to the growth of the oxide film 3 by the thermal oxidation process, and at the same time, the shape of the lower end corner portion of the floating gate electrode 4 becomes a rounded shape. As a result, electric field concentration can be prevented, and the electric field at that portion is weakened due to the increase in the film thickness of the oxide film 3. Therefore, by appropriately adjusting the amount of oxidation, it is possible to prevent the above-mentioned "drain disturb phenomenon". Is possible.

Thereafter, as shown in FIG. 12, an oxide film having a thickness of about 1500 Å is formed by the CVD method and anisotropic etching is performed to form side walls on the side surfaces of the floating gate electrode 4 and the control gate electrode 6. The oxide film 11 is formed. Thereafter, as shown in FIG. 13, an oxide film 12 having a film thickness of about 1500Å is formed on the entire surface, and a nitride film 13 having a film thickness of about 500Å is further formed.

Next, as shown in FIG. 14, an interlayer flattening film 14 is formed on the nitride film 13, and a resist 15 is deposited thereon. By patterning the resist 15, the opening 16 is formed. Then, isotropic etching is performed using the patterned resist 15 as a mask to form the interlayer flattening film 14 having the tapered recess 17. Thereafter, as shown in FIG. 15, anisotropic etching is performed using resist 15 as a mask to form an opening on drain diffusion region 10.

Next, referring to FIG. 1, a titanium film 1 having a film thickness of about 500 Å is formed on the drain diffusion region 10 having the opening.
8 is formed, and an aluminum alloy film 19 having a film thickness of about 5000Å is formed thereon by a sputtering method. Then, the titanium film 18 and the aluminum alloy film 19 are patterned by using photolithography and chemical treatment to form a bit line electrically connected to the drain diffusion region 10.

[0043]

According to the present invention, the film thickness of the first dielectric film immediately below the edge of the charge storage electrode can be varied depending on the function required for each impurity region. As a result, it is possible to prevent the phenomenon that the data stored in the non-selected cell is destroyed when the data is written in the selected memory cell, and it is possible to improve the reliability of the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a memory cell in an embodiment according to the present invention.

FIG. 2 is a cross-sectional view showing a first step of manufacturing steps of the embodiment according to the present invention.

FIG. 3 is a sectional view showing a second step of the manufacturing process of the embodiment according to the present invention.

FIG. 4 is a sectional view showing a third step of the manufacturing process of the embodiment according to the present invention.

FIG. 5 is a sectional view showing a fourth step of the manufacturing process of the embodiment according to the present invention.

FIG. 6 is a sectional view showing a fifth step of the manufacturing process of the embodiment according to the present invention.

FIG. 7 is a cross-sectional view showing a sixth step of the manufacturing steps of the embodiment according to the present invention.

FIG. 8 is a sectional view showing a seventh step of the manufacturing process of the embodiment according to the present invention.

FIG. 9 is a sectional view showing an eighth step of the manufacturing process of the embodiment according to the present invention.

FIG. 10 is a cross-sectional view showing a ninth step of the manufacturing process of the embodiment according to the present invention.

FIG. 11 is a tenth manufacturing process of an embodiment according to the present invention.
It is sectional drawing which shows a process.

FIG. 12 is an eleventh manufacturing process of an embodiment according to the present invention.
It is sectional drawing which shows a process.

FIG. 13 is a twelfth manufacturing process of the embodiment according to the present invention.
It is sectional drawing which shows a process.

FIG. 14 is a thirteenth manufacturing process of an embodiment according to the present invention.
It is sectional drawing which shows a process.

FIG. 15 is a fourteenth manufacturing process of an embodiment according to the present invention.
It is sectional drawing which shows a process.

FIG. 16 is a schematic sectional view schematically showing an embodiment according to the present invention.

FIG. 17 is a schematic sectional view schematically showing an embodiment according to the present invention.

FIG. 18 is a block diagram showing a general configuration of a conventional flash EEPROM.

FIG. 19 is a memory cell matrix 100 shown in FIG.
2 is an equivalent circuit diagram showing a schematic configuration of FIG.

FIG. 20 is a schematic plan view showing a conventional flash EEPROM.

21 is a cross-sectional view taken along the line AA in FIG.

FIG. 22 is a flash EEP given as an example of a conventional example.
It is sectional drawing which shows ROM.

[Description of Reference Signs] 1, 31, 51 p-type silicon substrate 3, 20, 34, 38 oxide film 4, 35, 57 floating gate electrode 5, 36 interlayer insulating layer 6, 37, 59 control gate electrode 8, 33 source diffusion Regions 10 and 32 Drain diffusion regions 13 and 21 Nitride film

Claims (2)

[Claims] 1. A first conductivity type semiconductor substrate having a main surface, and first and second second conductivity formed on the main surface of the semiconductor substrate so as to define a predetermined channel region with a space therebetween. -Type impurity region, a first dielectric film formed on the channel region, a charge storage electrode layer formed on the channel region with the first dielectric film interposed, A control electrode layer formed on the charge storage electrode layer with a second dielectric film interposed, and the thickness of the first dielectric film immediately below the edge of the charge storage electrode layer is The second portion is more than the first impurity region side.
Electrically writable and erasable semiconductor memory device having a thicker impurity region side. 2. A step of forming a first dielectric film on the main surface of a semiconductor substrate of the first conductivity type; a step of forming a charge storage electrode layer on the first dielectric film. Forming a control electrode layer on the charge storage electrode layer with a second dielectric film interposed, and using the control electrode layer as a mask, a first and a second
A step of forming conductive type impurity regions on the main surface of the semiconductor substrate at intervals, and a first film thickness on the first impurity region side immediately below an edge of the charge storage electrode layer. The step of increasing the film thickness of the first dielectric film, and a second film that is thicker than the first film thickness on the second impurity region side immediately below the edge of the charge storage electrode layer. And a step of increasing the thickness of the first dielectric film so as to have a thickness. A method of manufacturing an electrically writable and erasable semiconductor memory device.