JPH05136423A - Manufacture of semiconductor memory device which can be written and erased electrically - Google Patents

Abstract

PURPOSE:To reduce dispersion in threshold voltage by reducing dispersion in the channel longitudinal length of a p<+> type impurity diffusion region under a charge storage electrode of a memory cell of a flash EEPROM. CONSTITUTION:A charge storage electrode is formed on the main surface of a semiconductor substrate with a first dielectric film interposed 20. A control electrode is formed on this charge storage electrode with a second dielectric film interposed 30. BF2 is injected so as to pass through the charge storage electrode to form a p-type impurity region in the semiconductor substrate at least under the charge storage electrode 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a non-volatile semiconductor memory device capable of electrically writing and erasing, and in particular, it is possible to electrically erase written information collectively. EEPROM (Electrical
ly Erasable and Programma
ble read only memory), a so-called flash EEPROM manufacturing method.

[0002]

2. Description of the Related Art An EEPROM is known as a memory device having a structure capable of electrically writing and erasing data. An EEPROM, which is composed of one transistor and is capable of electrically erasing written information collectively, a so-called flash EEP will be described below with reference to FIGS. 19 to 36.
The ROM will be described.

FIG. 19 shows a conventional flash EEPROM.
2 is a block diagram showing a general configuration of FIG. As shown in FIG. 19, this flash EEPROM has a memory cell matrix 100 arranged in a matrix, an X address decoder 200, a sense amplifier 300, Y address data 400, an address buffer 500, and an input / output buffer 600. And control logic 700.

The memory cell matrix 100 has a plurality of memory transistors arranged in a matrix therein. X address decoder 200 and sense amplifier 300 are connected to select a row and a column of memory cell matrix 100. Sense amplifier 300
Includes a Y address decoder 400 that provides column selection information.
Are connected. An address buffer 500 for temporarily storing address information is connected to each of the X address decoder 200 and the Y address decoder 400.

An input / output buffer 600 for temporarily storing input / output data is connected to the sense amplifier 300.
In the address buffer 500 and the input / output buffer 600,
A control logic 700 for controlling the operation of the flash EEPROM is connected. The control logic 700 performs control based on a chip enable signal, an output enable signal and a program signal.

FIG. 20 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG. As shown in FIG. 20, a plurality of word lines W extending in the row direction
L _1, WL _2, ... and WL _I, a plurality of bit lines BL _1, BL ₂ extending in the column direction, ... and BL _I are orthogonal to each other, constitute a matrix. At the intersections of the word lines and the bit lines, memory transistors Q _{1 1} , Q _{1 2} , each having a floating gate electrode,
... _Qii is provided.

The drain diffusion region of each memory transistor is connected to each bit line, and the control gate electrode of the memory cell transistor is connected to each word line. The source diffusion region of the memory transistor is connected to each source line S ₁ , S ₂ , ... Source diffusion region of the memory transistor belonging to the same row are connected to each other as shown in FIG., The source lines S ₁ disposed on both sides,
It is connected to S ₂ ,.

FIG. 21 is a schematic plan view showing a flash EEPROM called a conventional stack gate type flash EEPROM. FIG. 22 is a sectional view taken along the line AA of FIG. The structure of the conventional flash EEPROM will be described with reference to these figures.

Referring to FIG. 21, control gate electrodes 56 are formed as word lines connected to each other and extending in the lateral direction (row direction). Bit line 69
Are arranged so as to be orthogonal to the word lines 56 and connect the drain diffusion regions 60 arranged in the vertical direction (column direction) to each other. The bit line 69 is electrically connected to each drain diffusion region 60 by a drain contact 70.

Referring to FIG. 22, bit line 69 is formed on interlayer flattening film 64 with titanium film 68 interposed. Referring to FIG. 21, source diffusion region 58 extends in the direction in which word line 56 extends and is formed in a region surrounded by word line 56 and element isolation oxide film 52.

Next, referring to FIG. 22, a drain diffusion region 60 and a source diffusion region 58 are formed on the main surface of p type silicon substrate 51 at a predetermined interval. The drain diffusion region 60 includes an n ⁺ type impurity diffusion region 60a and ap ⁺ type impurity diffusion region 60a.
Type impurity diffusion region 60b. In addition, the source diffusion region 58 includes n ⁺ -type impurity diffusion regions 58a and n
^- is composed of a impurity diffusion region 58b. A control gate electrode 56 and a floating gate electrode 54 are formed in a region sandwiched between the drain diffusion region 60 and the source diffusion region 58 so as to form a channel region.

The floating gate electrode 54 is formed on the p-type silicon substrate 51 by a thin oxide film 5 having a film thickness of about 100 Å.
It is formed through 3. Control gate electrode 5
6 is formed on the floating gate electrode 54 via an interlayer insulating layer 55 so as to be electrically separated from the floating gate electrode 54. The floating gate electrode 54 and the control gate electrode 56 are formed of a polycrystalline silicon layer.

Sidewall oxide films 61 are formed on the side surfaces of the floating gate electrode 54 and the control gate electrode 56. An oxide film 62 is formed on the drain diffusion region 60 except a part thereof. A nitride film 63 is formed on the oxide film 62. An interlayer flattening film 64 is formed on the nitride film 63, and an aluminum wiring layer 69a forming a bit line is formed on the interlayer flattening film 64 via a titanium film 68. ..

Flash EE having the above structure
The operation of the PROM will be described below. First, in the write operation, a voltage V _{d of} about 6 to 8 V is applied to the drain diffusion region 60, a ground potential is applied to the source diffusion region 58, and a voltage V _{G of} about 10 to 15 V is applied to the control gate electrode 56. By applying the voltages V _d and V _G , electrons having high energy are generated near the drain diffusion region 60 and the oxide film 53.

Some of the electrons are attracted to the floating gate electrode 54 by the electric field generated by the voltage V _G applied to the control gate electrode 56. When electrons are accumulated in the floating gate electrode 54 in this manner, the threshold voltage V _th of the memory cell increases. A state in which the threshold voltage V _th is higher than a predetermined value is written, which is called "0".

Next, in the erase operation, the source diffusion region
Voltage V of about 10 to 12 V in the area 58 _SIs applied,
Troll gate electrode 56 is ground potential, drain diffusion region
60 is kept floating. Source diffusion region 5
Voltage V applied to 8_SDue to the electric field caused by
The electrons in the insulating gate electrode 54 pass through the thin oxide film 53 by F-.
N (Fowler-Nordheim) tunnel phenomenon
Therefore pass.

In this way, the electrons in the floating gate electrode 54 are extracted, so that the threshold voltage V _th of the memory cell is lowered. This threshold voltage V
_A state in which _th is lower than a predetermined value is called an erased state “1”. Since the source diffusion regions 58 of the memory transistors are connected to each other as shown in FIG. 21, all the memory cells can be collectively erased by this erase operation.

Further, in the read operation, a voltage V _G ′ of about 5 V is applied to the control gate electrode 56 and a voltage V _d ′ of about 1 to 2 V is applied to the drain diffusion region 60.
At that time, whether or not a current flows in the channel region of the control gate transistor, that is, when the memory cell is O
The determination of "1" or "0" is made depending on whether the N state is the OFF state.

Next, the first to fourteenth steps in the manufacturing process of the flash EEPROM will be described below with reference to FIGS. 23 to 36.

First, referring to FIG. 23, a well (not shown) is formed by ion-implanting boron (B) into p-type silicon substrate 51 and then driving impurities. Then, as shown in FIG. 24, after boron (B) for ensuring the isolation characteristic is injected into the region for isolating the element formation region, a thermal oxidation process is applied to the element isolation oxide film 52 in the element isolation region. To form. In addition, in FIG.
21 shows a part of the sectional view taken along the line AA in FIG. 21, and FIG. 21 (II) shows the sectional view taken along the line C-C in FIG. ing. Below, FIG.
The same applies to item 5.

Next, as shown in FIG. 25, an oxide film 53 is formed on the entire surface of the p-type silicon substrate 51, and the channel region is subjected to channel doping in order to control the threshold voltage V _th of the memory cell. .. Then, a first polysilicon layer 54 is formed on the oxide film 53, and a resist 57a is deposited thereon. Then, using this resist 57a, the first polysilicon layer 54 is patterned in the vertical direction (bit line direction) at a constant pitch by photolithography and anisotropic etching. Then, the resist 57a is removed.

Next, as shown in FIG. 26, an interlayer insulating layer 55 is formed on the first polysilicon layer 54. Then, the second polysilicon layer 5 is formed on the interlayer insulating layer 55.
6 is formed, and a resist 57b is deposited on the second polysilicon layer 56. Then, as shown in FIG. 27, the resist 57b is linearly patterned at a constant pitch in the lateral direction (word line direction) by using photolithography, and then the second polysilicon layer is patterned using the resist 57b as a mask. 56, the interlayer insulating layer 55 and the first polysilicon layer 54 are anisotropically etched. As a result, the floating gate electrode 5 is formed by the first polysilicon layer 54.
4 is formed, and the control gate electrode 56 is formed by the second polysilicon layer 56.

Next, as shown in FIG. 28, a region serving as the drain diffusion region 60 in the memory cell is formed with a resist 57.
Cover with c. Then, using this resist 57c as a mask, arsenic (As) is implanted into the region to be the source diffusion region 58, and further phosphorus (P) is implanted as shown in FIG. Thereby, the source diffusion region 58 is formed.
As a result, the source diffusion region 58 is composed of an n ⁺ type impurity diffusion region 58a formed by implantation of arsenic (As) and an n ⁻ type impurity diffusion region 58b formed by implantation of phosphorus (P).

Next, as shown in FIG. 30, the source diffusion region 58 of the memory cell is covered with a resist 59. Then, arsenic (As) is implanted into the region to be the drain diffusion region 60, and further, as shown in FIG. 3, boron (B) for forming the p ⁺ -type impurity diffusion region 60b for improving the writing characteristics.
Using an oblique 45-degree rotation ion implantation method, for example, 5
The drain diffusion region 60 is formed by implanting under the conditions of 0 KeV and 3 × 10 ¹³ / cm ² . As a result, the drain diffusion region 60 is composed of the n ⁺ -type impurity diffusion region 60a by arsenic (As) implantation and the p ⁺ -type impurity diffusion region 60b by boron (B) implantation.

Then, referring to FIG. 32, a resist 59 is formed.
After removing, form an oxide film with a thickness of 1500 Å,
By performing anisotropic etching, sidewall oxide film 61 is formed on the side surfaces of floating gate electrode 56 and control gate electrode 54. Then, as shown in FIG. 33, an oxide film 62 is formed on the entire surface, and a nitride film 63 is further formed on the oxide film 62.

Then, as shown in FIG. 34, a nitride film 63 is formed.
An inter-layer flattening film 64 is formed on top of this, and a resist 6 is formed thereon.
5 is deposited. An opening 66 is formed by patterning the resist 65. Then, isotropic etching is performed using the patterned resist 65 as a mask to form the interlayer flattening film 64 having the tapered recess 67. Then, as shown in FIG. 35, an opening is formed on drain diffusion region 60 by performing anisotropic etching using resist 65 as a mask.

Next, referring to FIG. 36, a titanium film 68 is formed on the opened drain diffusion region 60, and an aluminum alloy film 69a is formed on the titanium film 68. Then, the titanium film 68 and the aluminum alloy film 69a are patterned by using photolithography and chemical treatment to form the bit line 69 electrically connected to the drain diffusion region 60.

[0028]

Although the conventional flash EEPROM is formed through the above steps, the conventional flash EEPROM has the following problems.

Conventionally, the p ⁺ -type impurity diffusion region 60b is formed by implanting boron (B) to improve the writing characteristics. However, this p ⁺ -type impurity diffusion region 60b is used.
Of the threshold voltage V _th
Can be controlled. This is because when the p-type impurity ion concentration is increased, the threshold voltage in that portion increases, and the drift velocity decreases in proportion to the carrier mobility, that is, the electric field strength, due to the impurity scattering in this portion. Therefore, the threshold voltage V _{th of the} entire memory transistor also becomes high. That is, the threshold voltage of the memory transistor can be controlled by the concentration of the p ⁺ type impurity diffusion region 60b. As a result, the channel dope region for V _th control in the above process is
It is considered that it is virtually unnecessary.

Conventionally, boron (B) is implanted by the oblique rotation ion implantation method to form the p ⁺ -type impurity diffusion region 60b. FIG. 37 is a conceptual diagram showing how boron (B) is implanted by using the oblique rotation ion implantation method. Referring to FIG. 37,
When boron (B) is implanted into the p-type silicon substrate 51 using the oblique rotation ion implantation method, some of the implanted boron (B) penetrates the floating gate electrode 54 made of polysilicon. To do.

In this case, the way in which boron (B) penetrates differs depending on the difference in the crystal orientation of polysilicon and the existence of crystal grain boundaries. That is, the crystal grains in the orientation that causes channeling are likely to penetrate, and the other portions are less likely to penetrate. Also, the crystal grain boundary portion is easily penetrated. Therefore, there may be those that are deeply implanted in the p-type silicon substrate 51 and those that are not. As a result, as shown in FIG. 37, in each memory cell, variations in the value of the length L of the p ⁺ -type impurity diffusion region 60b in the channel length direction, variations in the implantation depth, and variations in the implantation amount occur. The threshold voltage V _{th of the} cell varies. In addition,
In this case, L indicates the length of the p ⁺ -type impurity diffusion region 60b in the channel length direction when boron (B) is channeled and deeply implanted.

FIG. 38 is a diagram showing the threshold voltage distribution of each memory cell, in which the vertical axis represents the number of bits and the horizontal axis represents the threshold voltage V _th . As shown in FIG. 38, in this case, it can be seen that the threshold voltage V _th varies within the range of V ₁ = 1.5 (V). At this time, the dispersion is 0.2 (V). Thus, by the threshold voltage V _th varies, for example, after erasing, the possible presence of the memory cell threshold voltage V _th is negative (the memory cell of the over-erased state) is increased. The existence of the memory cell in the over-erased state causes a problem of causing a Y-line defect when reading data.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a flash EEPROM capable of reducing the variation in V _th between memory cells.

[0034]

The present invention is premised on a method of manufacturing a semiconductor memory device capable of being electrically written and erased. First, a charge storage electrode is formed on the main surface of a semiconductor substrate with a first dielectric film interposed, and a control electrode is formed on this charge storage electrode with a second dielectric film interposed. Then, by implanting BF ₂ so as to pass through the charge storage electrode, a p-type impurity region is formed at least in the semiconductor substrate below the charge storage electrode.

[0035]

According to the method of manufacturing the semiconductor memory device of the present invention, the p-type impurity region is formed in the semiconductor substrate by implanting BF ₂ . Since BF ₂ is less likely to cause channeling than boron (B), the difference in implantation depth between the case where the crystal grains are in the direction in which channeling occurs and the case where they do not occur becomes small. Therefore, it is possible to reduce variations in the threshold voltage V _th between the memory cells, as compared with the case where boron (B) is injected.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. 1 to 14
Is a first method of manufacturing a semiconductor memory device according to the present invention.
~ It is sectional drawing which shows 14th process. 1 to 14
FIG. 22 is a diagram mainly corresponding to a part of a cross section taken along line AA in FIG. 21.

First, referring to FIG. 1, p-type silicon substrate 1
In addition, boron (B) was added to 100 KeV, 1.0 × 10 ¹³ /
Inject under the condition of cm ² . Then, a well (not shown) is formed by driving impurities at 1180 ° C. for 6 hours. Next, as shown in FIG. 2, an element isolation region on the main surface of p-type semiconductor substrate 1 is subjected to thermal oxidation treatment to form element isolation oxide film 2 having a film thickness of about 7500Å. Note that FIG. 2 (I) is a view corresponding to a part of a cross section taken along line AA in FIG. 21, and FIG. 2 (II) is taken along line CC in FIG. It is a figure corresponding to the cross section seen.

Next, as shown in FIG. 3, an oxide film 3 having a thickness of about 100 Å is formed on the entire surface of the p-type silicon substrate 1, and a first polysilicon layer 4 having a thickness of about 1000 Å is formed thereon. .. Then, a resist 7a is deposited on the first polysilicon layer 4. Using this resist 7a, the first polysilicon layer 4 is patterned at a constant pitch in the bit line direction (vertical direction) by photolithography and anisotropic etching. Then, the resist 7a is removed.

Next, referring to FIG. 4, an oxide film having a film thickness of about 100 Å is formed on the first polysilicon layer 4 by the CVD method, and a film thickness of 100 Å is formed thereon by the CVD method. A nitride film having a thickness of about 100 Å is formed on the nitride film by CVD. Thereby, interlayer insulating layer 5 is formed on first polysilicon layer 4. Then, on the interlayer insulating layer 5, a thickness of 2500Å
A second polysilicon layer 6 is formed to a certain extent, and a resist 7b is deposited on the second polysilicon layer 6.

Then, as shown in FIG. 5, the resist 7b is linearly patterned at a constant pitch in the lateral direction (word line direction) using photolithography, and the second poly is used as a mask. The silicon layer 6, the interlayer insulating layer 5 thereunder and the first polysilicon layer 4 are anisotropically etched. As a result, the first polysilicon layer 4
Thus, the floating gate electrode 4 is formed, and the second polysilicon layer 6 forms the control gate electrode 6.

Next, as shown in FIG. 6, the region to be the drain diffusion region 10 in the memory cell is covered with a resist 7c. Then, using the resist 7c as a mask, arsenic (As) is added to the region serving as the source diffusion region 8 by 35 Ke.
V, 1.0 × 10 ¹⁶ / cm ² , and further, as shown in FIG. 7, phosphorus (P) was added at 50 KeV, 5.
The implantation is performed under the condition of 0 × 10 ¹⁴ / cm ² . Thereby,
The source diffusion region 8 is formed. Therefore, the source diffusion region 8 is composed of the n ⁺ -type impurity diffusion region 8a formed by implanting arsenic (As) and the n ⁻ -type impurity diffusion region 8b formed by implanting phosphorus (P).

Next, as shown in FIG. 8, the source diffusion region 8 of the memory cell is covered with a resist 7d. Then, 35 Ke of arsenic (As) is applied to the region to be the drain diffusion region 10.
Implant under the conditions of V, 5.0 × 10 ¹⁴ / cm ² . Further, as shown in FIG. 9, B for forming a buried p ⁺ -type impurity diffusion region 10b for controlling the threshold voltage V _th.
F ₂ was set to 250 by using the oblique 45 ° rotation ion implantation method.
Implantation is performed under the conditions of KeV and 3 × 10 ¹³ / cm ² . Thereby, the drain diffusion region 10 is formed. Therefore, the drain diffusion region 10 is composed of the n ⁺ -type impurity diffusion region 10a by arsenic (As) implantation and the p ⁺ -type impurity diffusion region 10b by BF ₂ implantation.

Here, by injecting BF ₂ ,
Regarding the case of forming the p ⁺ type impurity diffusion region 10b,
This will be described in more detail below in comparison with the case where the p ⁺ type impurity diffusion region 60b is formed by implanting boron (B). FIG. Appl. Phys. Vo
l. 54, No. 12, December 1983,
FIG. It is 1.

FIG. 15 is a diagram showing the concentration distribution in the depth direction of the substrate when the elements (B, BF, BF ₂ ) are ion-implanted into the substrate under predetermined conditions, and the concentration (cm) is plotted on the vertical axis.
^-3 ), the horizontal axis shows the driving depth (μm). Figure 15
As shown in FIG. 5, it is understood that the concentration of boron (B) (1) is larger than that of BF ₂ (2) at a deeper portion of the substrate. That is, it can be said that BF ₂ has smaller channeling than boron (B).

FIG. 16 is a conceptual diagram showing a state where the p ⁺ -type impurity diffusion region 10b is formed by implanting BF ₂ by oblique 45-degree rotational ion implantation. As described above with reference to FIG. 16, since BF ₂ has smaller channeling, it is less likely to be implanted deep into the p-type silicon substrate 1 as compared with the case where boron (B) is implanted. As a result, even when the p-type silicon substrate 1 is implanted over the floating gate electrode 4, the possibility of deep implantation in the channel length direction is similarly reduced.

As a result, the threshold voltage V between the memory cells
The variation of _th also becomes small. In addition, in FIG.
L is a floating region of the n ⁺ -type impurity diffusion region 10a and an interface between the p ⁺ -type impurity diffusion region 60b and the p-type silicon substrate 1 immediately below the floating gate electrode 4 when boron (B) is channeled and deeply implanted. The distance to the interface immediately below the gate electrode 4 is shown as L
₁ shows the above-mentioned interval when BF ₂ is injected.

FIG. 17 is a diagram showing the distribution of the threshold voltage V _th of each memory cell when the p ⁺ -type impurity diffusion region 10b is formed by implanting BF ₂ , with the vertical axis representing the number of bits, The horizontal axis represents the threshold voltage V _th .
Note that this figure corresponds to FIG. 38 used in the description of the conventional example. Referring to FIG. 17, the variation in threshold voltage V _th between memory cells is within the range of V ₂ = 0.8 (V). The dispersion in this case is 0.13
(V). Therefore, it can be seen that the variation in the threshold voltage V _th is significantly reduced as compared with the conventional case. As a result, the possibility of existence of over-erased memory cells is significantly reduced, and the possibility of Y-line defects during reading can be significantly reduced.

Next, as shown in FIG. 10, the resist 7d
Is removed, and then the film thickness is 1500Å by using the CVD method.
A side oxide film 11 is formed on the side surfaces of the floating gate electrode 4 and the control gate electrode 6 by forming an oxide film of a certain degree and performing anisotropic etching. Thereafter, as shown in FIG. 11, an oxide film 12 having a film thickness of about 1500Å is formed on the entire surface, and a nitride film 13 having a film thickness of about 500Å is further formed.

Next, as shown in FIG. 12, an interlayer flattening film 14 is formed on the nitride film 13, and a resist 15 is deposited thereon. By patterning the resist 15, the opening 16 is formed. Then, isotropic etching is performed using the patterned resist 15 as a mask to form the interlayer flattening film 14 having the tapered recess 17. Then, as shown in FIG.
Anisotropic etching is performed using the resist 15 as a mask to form an opening on the drain diffusion region 10.

Next, as shown in FIG. 14, a titanium film 18 having a film thickness of 500Å is formed on the drain diffusion region 10 having the opening, and an aluminum alloy film 19 having a film thickness of 5000Å is formed thereon by the sputtering method. Are formed by using.
Then, the titanium film 18 and the aluminum alloy film 19 are patterned by using photolithography and chemical treatment to form a bit line electrically connected to the drain diffusion region 10.

Next, with reference to FIG. 18, a method of manufacturing the semiconductor memory device according to the present invention described in the above embodiment will be summarized.

First, a charge storage electrode is formed on the main surface of a semiconductor substrate which has been subjected to a predetermined treatment, with a first dielectric film interposed (step 20). Then, a control electrode is formed on the charge storage electrode via the second dielectric film (step 30). After that, BF ₂ is implanted by using the oblique 45 ° rotational ion implantation method so as to pass through the charge storage electrode, and a p-type impurity region is formed at least in the semiconductor substrate below the charge storage electrode (step 40). Then, after performing other predetermined processing, a semiconductor memory device is manufactured.

[0053]

According to the present invention, BF ₂ is formed on the semiconductor substrate.
Since the p-type impurity region is formed by implanting, the channeling is less likely to occur as compared with the case where the p-type impurity region is formed by using boron (B). As a result, it is possible to reduce variations in the threshold voltage among the memory cells, and it is possible to significantly reduce the possibility of occurrence of over-erased memory cells. As a result, it is possible to provide a highly reliable semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step in a manufacturing process of an embodiment according to the present invention.

FIG. 2 is sectional views (I) and (II) showing a second step in the manufacturing process of the embodiment according to the present invention.

FIG. 3 is sectional views (I) and (II) showing a third step in the manufacturing process of the embodiment according to the present invention.

FIG. 4 is a sectional view showing a fourth step in the manufacturing process of the embodiment according to the present invention.

FIG. 5 is a sectional view showing a fifth step in the manufacturing process of the embodiment according to the present invention.

FIG. 6 is a sectional view showing a sixth step in the manufacturing process of the embodiment according to the present invention.

FIG. 7 is a sectional view showing a seventh step of the manufacturing process of the embodiment according to the present invention.

FIG. 8 is a sectional view showing an eighth step in the manufacturing process of the embodiment according to the present invention.

FIG. 9 is a sectional view showing a ninth step in the manufacturing process of the embodiment according to the present invention.

FIG. 10 is a sectional view showing a tenth step in the manufacturing process of the embodiment according to the present invention.

FIG. 11 is a cross-sectional view showing the eleventh step in the manufacturing process of the embodiment according to the present invention.

FIG. 12 is a sectional view showing a twelfth step in the manufacturing process of the embodiment according to the present invention.

FIG. 13 is a sectional view showing a thirteenth step in the manufacturing process of the example according to the present invention.

FIG. 14 is a sectional view showing a fourteenth step in the manufacturing process of the embodiment according to the present invention.

FIG. 15 is a diagram showing the concentration distribution in the depth direction of the substrate when the elements (B, BF, BF ₂ ) are ion-implanted under predetermined conditions.

FIG. 16 is a conceptual diagram showing a state where ap ⁺ -type impurity diffusion region 10b is formed by implanting BF ₂ by obliquely rotating ions at 45 degrees.

FIG. 17 is a diagram showing a threshold voltage distribution of each memory cell formed according to the present invention.

FIG. 18 is a process chart schematically showing a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 19 is a block diagram showing a general configuration of a conventional flash EEPROM.

FIG. 20 is a memory cell matrix 100 shown in FIG. 28.
2 is an equivalent circuit diagram showing a schematic configuration of FIG.

FIG. 21 is a schematic plan view showing a conventional flash EEPROM.

22 is a sectional view taken along the line AA in FIG.

FIG. 23 is a cross-sectional view showing a first step in the manufacturing process of the conventional flash EEPROM.

FIG. 24 is a sectional view (I), (II) showing a second step in the manufacturing process of the conventional flash EEPROM.

FIG. 25 is a sectional view (I), (II) showing a third step in the manufacturing process of the conventional flash EEPROM.

FIG. 26 is a cross-sectional view showing a fourth step in the manufacturing process of the conventional flash EEPROM.

FIG. 27 is a cross-sectional view showing a fifth step in the manufacturing process of the conventional flash EEPROM.

FIG. 28 is a cross-sectional view showing a sixth step in the manufacturing process of the conventional flash EEPROM.

FIG. 29 is a cross-sectional view showing a seventh step in the manufacturing process of the conventional flash EEPROM.

FIG. 30 is a cross-sectional view showing an eighth step in the manufacturing process of the conventional flash EEPROM.

FIG. 31 is a cross-sectional view showing a ninth step in the manufacturing process of the conventional flash EEPROM.

FIG. 32 is a sectional view showing a tenth step in the manufacturing process of the conventional flash EEPROM.

FIG. 33 is a cross-sectional view showing the eleventh step in the manufacturing process of the conventional flash EEPROM.

FIG. 34 is a sectional view showing a twelfth step in the manufacturing process of the conventional flash EEPROM.

FIG. 35 is a sectional view showing a thirteenth step in the manufacturing process of the conventional flash EEPROM.

FIG. 36 is a sectional view showing a fourteenth step in the manufacturing process of the conventional flash EEPROM.

FIG. 37 is a conceptual diagram showing a state of forming a P ⁺ -type impurity diffusion region by implanting boron (B).

FIG. 38 is a threshold voltage V of each conventional memory cell.
It is a figure which shows the distribution of _th .

[Explanation of symbols]

1,51 p-type silicon substrate 3,12,53 oxide film 4,54 floating gate electrode 5,55 interlayer insulating layer 6,56 control gate electrode 8 source diffusion region 10 drain diffusion region 8a, 10a, 58a, 60an ⁺ type Impurity diffusion region 8b, 58b n ^- type impurity diffusion region 10b, 60b p ⁺ type impurity diffusion region

Claims (1)

[Claims] 1. A method for manufacturing an electrically writable and erasable semiconductor memory device, which comprises forming a charge storage electrode on a main surface of a semiconductor substrate with a first dielectric film interposed. Forming a control electrode on the charge storage electrode with a second dielectric film interposed; and injecting BF ₂ so as to pass through the charge storage electrode, so that the control electrode is formed at least under the charge storage electrode. And a step of forming a p-type impurity region on the semiconductor substrate.