JPH06188430A - Nonvolatile storage element and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a nonvolatile storage element in which the length of the channel can be shortened while securing high-speed operation. CONSTITUTION:A p well 21 is made on the top of an n-type silicon substrate 20. A gate oxide film 25 and an address gate 26 are formed in order in the specified region of the p well 21. An ONO film 27 is formed all over the source, so as to cover the gate oxide film 25 and the address gate 26. The ONO film 27 is covered with a side wall gate 28, on one side of the address gate 26. By the ion implantation using the address gate 26 and the side wall gate 28 as masks, a source region 22 and a drain region 23 are formed in a self alignment manner. A memory gate 29 is made, to cover one part of the address region 26, on the side wall gate 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPROM (Ele
ctrically Erasable Programmable Read OnMemory)
For example, the present invention relates to a nonvolatile memory element that stores information by injecting and extracting charges and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile memory element having a memory transistor for storing information by injecting and extracting charges and an address transistor for addressing the memory transistor has been known as a single unit. There have been proposed various non-volatile memory devices arranged in a matrix on the semiconductor substrate in the row and column directions.

With the recent development of the semiconductor industry, miniaturization of elements has been demanded. However, since the above nonvolatile memory device has a 1-cell / 2-transistor structure, it cannot contribute to miniaturization. Therefore, in order to cope with miniaturization, a nonvolatile memory element including only one transistor having a memory gate and an address gate is formed in a matrix on a single semiconductor substrate in a row direction and a column direction. Sexual storage was proposed. FIG. 8 shows an example of a nonvolatile memory element according to this nonvolatile memory device. FIG. 8 is a schematic sectional view showing the structure of a conventional nonvolatile memory element.

A conventional non-volatile memory element is as shown in FIG.
On the P-type silicon substrate 1 and the surface layer surface of the P-type silicon substrate 1.
N formed at a predetermined interval⁺Mold source area 2 and
And N ⁺Type drain region 3, source region 2 and drain
The channel region 4 is formed so as to be sandwiched between the channel regions 3.
On the region except the predetermined region on the side of the drain region 3
The formed gate insulating film 5 and the gate insulating film 5 formed
A predetermined address gate 6 and channel region 4
Form a part of the address gate 6 over the area.
ONO (oxide-nitride that is formed and accumulates electrons
-oxide) film 7 and ONO film 7 on the address gate 6
A memory gate 8 formed so as to cover a partial area
I am. That is, the nonvolatile memory element shown in FIG.
There is a dielectric constant between the address gate 6 and the memory gate 8.
An ONO film 7 including a high nitride film is interposed.

The address gate 6 and the memory gate 8 are covered with an interlayer insulating film 9, and a drain wiring 11 is formed so as to come into contact with the drain region 3 through a contact hole 10 opened in the interlayer insulating film 9. There is. The entire surface of the drain wiring 11 is covered with the passivation film 12.

[0006]

In the nonvolatile memory element shown in FIG. 8, the ONO film 7 containing a nitride film having a high dielectric constant is interposed between the address gate 6 and the memory gate 8. Therefore, the channel can be made sufficiently low in resistance with the voltage of the memory gate 8 and the reading speed of information is increased.

However, the above non-volatile memory element is
There is a limit to the further miniaturization of elements. Because the address gate 6 and the memory gate 8 are used as a mask,
Since the source region 2 and the drain region 3 are formed in a self-aligned manner, the length (channel length) of the channel region 4 which is sandwiched between the source region 2 and the drain region 3 is determined by the address gate 6 and the memory gate 8. It is regulated and there is a limit to shortening the channel length.

In view of the above, it is an object of the present invention to provide a non-volatile memory element that can shorten the channel length while ensuring high-speed operation and contribute to further miniaturization of the element, and a method for manufacturing the same.

[0009]

Means and Actions for Solving the Problems A nonvolatile memory element for achieving the above-mentioned object is to inject charges,
A non-volatile memory element for storing information by taking out, a semiconductor substrate having a predetermined first conductivity type, formed on a surface layer of the semiconductor substrate at a predetermined interval,
A source region and a drain region having a second conductivity type opposite to the first conductivity type, and a channel region formed so as to be sandwiched between the source region and the drain region except a predetermined region on the drain region side. A gate insulating film formed on the gate insulating film, an address gate formed on the gate insulating film, a predetermined region of the channel region,
A charge storage film formed to cover a partial region of the address gate and storing a charge including a nitride film, and a side wall gate formed by depositing on the charge storage film corresponding to the side of the drain region of the address gate. And a memory gate formed on the sidewall gate so as to cover a partial region of the address gate.

In the above nonvolatile memory element, when reading information, the source region is set to the ground potential, a high voltage is applied to the address gate, a low voltage is applied to the drain region, and a memory gate is applied. When the sense voltage is applied, an inversion layer is formed on the surface of the semiconductor substrate just below the address gate. At this time, if the charge is accumulated in the charge storage film, the charge in the memory gate is canceled by the charge accumulated in the charge storage film, and the influence of the charge in the memory gate is influenced by the charge in the semiconductor substrate immediately below the sidewall gate. Does not reach the surface. Therefore, no channel is formed in the nonvolatile memory element, and no current flows between the drain region and the source region. On the other hand, if the charge is not stored in the charge storage film, the influence of the charge on the memory gate extends to the surface of the semiconductor substrate immediately below the sidewall gate, a channel is formed in the nonvolatile memory element, and the drain region-source region An electric current flows. If you sense this state,
The information stored in the non-volatile storage element is read.

At the time of reading this information, since the channel resistance is lowered by interposing a charge storage film containing a nitride film having a high dielectric constant between the address gate and the memory gate, the memory gate is removed from the channel region. Even if they are separated from each other, the channel can be sufficiently turned on by the memory gate voltage (sense voltage), and a high read speed can be secured as in the conventional case.

The method for manufacturing the above-mentioned nonvolatile memory device includes a step of sequentially forming a gate insulating film and an address gate on a predetermined region of a semiconductor substrate having a predetermined first conductivity type, a gate insulating film and an address. Corresponding to one side of the address gate, a step of forming a charge storage film for accumulating charges including a nitride film on the semiconductor substrate exposed on one side of the gate while covering a partial area of the address gate A step of depositing a sidewall gate on the charge storage film, using the address gate and the sidewall gate as a mask, implanting impurity ions of a second conductivity type opposite to the first conductivity type, and The process of forming the drain region in a self-aligned manner, and the memory gate on the sidewall gate while covering a partial region of the address gate. It is intended to include a step of forming a.

In the above manufacturing method, the side wall gate is formed before the memory gate is formed, ions are implanted using the side wall gate and the address gate as a mask, and the source region and the drain region are self-aligned. Since it is formed, the channel length can be shortened even if the address gate and the memory gate are provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view showing the structure of a nonvolatile memory element according to an embodiment of the present invention. The structure of the nonvolatile memory element MD according to the present embodiment will be described with reference to FIG.

The nonvolatile memory element MD of this embodiment is shown in FIG.
Like the N-type silicon substrate 20 and the N-type silicon substrate 2
0, a P well 21 formed on the upper part of 0, an N ⁺ type source region 22 and an N ⁺ type drain region 23 formed in the surface layer of the P well 21 at a predetermined interval, and a source region 2
2 and the drain region 23, a gate oxide film 25 formed on a region of the channel region 24 except the predetermined region on the drain region 23 side, and an address gate 26 formed on the gate oxide film 25. And an ONO film 27 which accumulates electrons and is formed on a predetermined region of the channel region 24 on the drain region 23 side.
And a sidewall gate 28 formed on the ONO film 27 in an insulating state with the end portion of the address gate 26 on the drain region 23 side, and on the sidewall gate 28 formed in an insulating state with the upper surface of the address gate 26. And a memory gate 29.

As the N-type silicon substrate 20, for example, one having a substrate concentration of 2 to 4 × 10 ¹⁵ cm ^-3 is used.
The diffusion depth of the P well 21 is set relatively deep. The gate oxide film 25 is made of SiO ₂ , and its film thickness is set relatively thin.

The address gate 26 contains, for example, phosphorus at high concentration.
Conductive material, such as polysilicon, that has been heavily doped to reduce resistance
It is of high quality and is covered with the ONO film 27. ONO film 2
7 is, for example, Si₃N_FourFor example, a nitride film with a high dielectric constant such as
For example SiO ₂Sandwiched from above and below with an oxide film such as
It has a structure. The thickness of the bottom oxide film is about 20Å
In addition, the thickness of the nitride film is about 50Å,
The film thickness is set to about 40Å.

Similar to the address gate 26, the sidewall gate 28 is made of a conductive material such as polysilicon, and is deposited on the ONO film 27 covering the drain region 23 side of the address gate 26. That is, the ONO film 27 is interposed between the sidewall gate 28 and the address gate 26, and the ONO film 27 is provided.
As a result, the side wall gate 28 and the address gate 2
And 6 are insulated.

The memory gate 29 is the address gate 26.
In the same manner as above, it is made of a conductive material such as polysilicon, and is connected to the sidewall gate 28 in a state of being extended to a predetermined region of the address gate 26. That is,
The ONO film 27 is interposed between the memory gate 29 and the extended portion of the address gate 26.
7, the memory gate 29 and the address gate 26 are insulated from each other.

Further, the entire surface of the silicon substrate 20 is BPSG (boron-phospho-silicate glass) obtained by mixing B in PSG (phospho-silicate glass) which is P-doped SiO _2.
It is covered with an interlayer insulating film 30 such as s). Then, in the interlayer insulating film 30 and the ONO film 27, a contact hole 31 is opened in a portion corresponding to the drain region 23, and a drain wiring 32 is formed so as to come into contact with the drain region 23 through the contact hole 31. There is. Although not shown, contact holes are also formed in portions corresponding to the source region 22, the address gate 26, and the memory gate 29, and the source wiring, the address gate wiring, and the memory gate wiring are respectively formed through the contact holes. It is formed in contact with the source region 22, the address gate 26, and the memory gate 29.

The wiring including the drain wiring 32 is made of a conductive material such as Al, and protects the surface of the non-volatile memory element MD on each wiring and prevents invasion of contaminants from the outside. For example, nitride film (Si ₃ N ₄ )
A passivation film 33 made of an insulating material such as is laminated on the entire surface. FIG. 2 is an equivalent circuit diagram of a non-volatile memory device including a non-volatile memory element. The electrical configuration of the non-volatile memory device M including the non-volatile memory element MD will be described with reference to FIG.

In the non-volatile memory device M, as shown in FIG. 2, memory cells MC1, MC2, MC3, MC4 surrounded by dotted lines are arranged in a matrix in a row direction X and a column direction Y, and each memory cell MC1, MC1. MC2, MC3, MC4 are
One nonvolatile memory element MD1, MD2, MD3, MD
It has a structure consisting of only four. In the memory gates of the non-volatile memory elements MD1 and MD2 arranged in the row direction,
The word line WL1 is connected to the address gate, and the address gate line AGL1 is connected to the address gate. Similarly, the nonvolatile memory elements MD3 and MD arranged in the row direction are arranged.
The word line WL2 is connected to the memory gate 4 and the address gate line AGL2 is connected to the address gate.

The drains of the nonvolatile memory elements MD1 and MD2 arranged in the row direction are connected in series, and the bit line BL is connected to the connection intermediate point. Similarly, the nonvolatile memory elements MD3 and MD arranged in the row direction are arranged.
The drains of 4 are connected in series, and the bit line BL is connected to the connection intermediate point. That is, the nonvolatile memory elements MD1, MD2 and MD arranged in the row direction.
3, MD4 share the bit line BL.

Then, each nonvolatile memory element MD1, MD
A source line SL is commonly connected to the sources of 2, MD3 and MD4. Here, with reference to mainly FIG. 2 and Table 1, information writing, erasing, and reading operations of information in the nonvolatile memory element MD will be described. In Table 1, it is assumed that the memory cells MC1 and MC2 are selected.

[0025]

[Table 1]

<Write (WRITE)> Information is written in the word line WL2 and the addressed gate line A.
GL2, the source line SL and the bit line BL are set to the ground potential 0V, the address gate line AGL1 is set to the ground potential 0V and the high voltage 8V is applied to the word line WL1 in order to select the memory cells MC1 and MC2 for writing information. Is applied.

Then, as shown in FIG. 3, the nonvolatile memory element MD in the selected memory cells MC1 and MC2.
1, MD2, a high voltage is applied between the memory gates 291 and 292 and the P well 21, and the FN (Fowler Nordhe
im) Tunnel current is generated. As a result, electrons are injected into the ONO films 271, 272 directly under the side wall gates 281, 282, and the state of writing information “1” is set.

On the other hand, when information is not written, the word lines WL1 and WL2, the addressed gate lines AGL1 and AGL2 and the source line SL are set to the ground potential 0V, and 5V is applied to the bit line BL. Then, in the nonvolatile memory elements MD1 and MD2 in the memory cells MC1 and MC2, the FN tunnel current is not generated, and electrons are not injected into the ONO films 271 and 272. Therefore, no information is written.

The gate voltage required to establish conduction between the source and drain of the non-volatile memory element changes depending on whether the ONO film has accumulated electons or not. That is, the threshold voltage V _TH for making the source-drain of the nonvolatile memory element conductive is O
High threshold V with electrons injected into the NO film
1 and takes a low threshold voltage V2 when electrons are not injected. Thus, the threshold voltage V _{TH is set} to 2
By setting the type, binary data of "1" or "0" can be stored in the nonvolatile storage element. <Erase> Information is erased by word line W
L2, the addressed gate line AGL2 and the source line SL are set to the ground potential 0V and the bit line BL is set to the ground potential 0V or an open state to select the memory cells MC1 and MC2 to erase information. The line AGL1 is set to the ground potential 0V, and a negative high voltage -8V is applied to the word line WL1.

Then, as shown in FIG. 4, the nonvolatile memory element MD in the selected memory cells MC1 and MC2.
1, MD2, a bias reverse to that at the time of writing is applied between the memory gates 291 and 292 and the P well 21,
An FN tunnel current is generated from the memory gates 291 and 292 toward the P well 21. As a result, the electrons accumulated in the ONO films 271, 272 flow into the P well 21, and the electrons are extracted from the ONO films 271, 272. Therefore, the information is erased, that is, the information "0" is written. <Read (READ)> Information is read from the address gate line SGL1 in order to select the memory cells MC1 and MC2 to be read by setting the word line WL2, the address gate line AGL2 and the source line SL at the ground potential 0V. 5V is applied, 1V is applied to the bit line BL, and the word line WL1
A sense voltage of 2V is applied to.

Then, as shown in FIGS. 5A and 5B, in the nonvolatile memory elements MD1 and MD2 in the selected memory cells MC1 and MC2, the address gate 261,
Since 5V is applied to 262, address gate 2
Electrons having a concentration equal to the hole concentration of the well 21 are induced on the surface of the P well 21 immediately under the layers 61 and 262, and an inversion layer IL is generated.

At this time, as shown in FIG. 5A, the ONO films 271, 272 of the nonvolatile memory elements MD1, MD2 are formed.
If electrons are stored in the memory gate 29
The positive charges of 1 and 292 are canceled by the electrons accumulated in the ONO films 271 and 272, and the influence of this positive charge does not reach the surface of the P well 21 directly below the sidewall gates 281 and 282. Therefore, no channel is formed in the nonvolatile memory elements MD1 and MD2,
From the drain regions 231 and 232 to the source regions 221 and 221
No current flows through 22. On the other hand, as shown in FIG. 5B, the ONO film 27 of the non-volatile memory elements MD1 and MD2.
If electrons are not stored in the memory cells 1 and 272, the influence of the positive charges of the memory gates 291 and 292 extends to the surface of the P well 21 immediately below the sidewall gates 281 and 283, and channels are formed in the nonvolatile memory elements MD1 and MD2. As a result, current flows from the drain regions 231 and 232 to the source regions 221 and 222. If this state is sensed by a decoder and a sense amplifier (not shown), the information stored in the nonvolatile memory elements MD1 and MD2 is read.

By the way, the sense voltage is an intermediate voltage between two kinds of V1 and V2 of the threshold voltage V _TH .
Therefore, when this sense voltage is applied, conduction / non-conduction of the nonvolatile memory element is determined by whether or not electrons are accumulated in the ONO film. At the time of reading the above information, as shown in FIG. 1, an ONO including a nitride film having a high dielectric constant is provided between the address gate 26 and the memory gate 29.
Since the channel resistance is lowered by interposing the film 27,
Even if the memory gate 29 is separated from the channel region 24, the channel can be sufficiently turned on by the memory gate voltage (sense voltage). Therefore, a high read speed can be secured as in the conventional case.

6 and 7 are schematic sectional views showing a method of manufacturing the nonvolatile memory element in the order of steps. 6 and 7
A manufacturing method of the nonvolatile memory element MD will be described with reference to FIG. First, as shown in FIG. 6A, the P well 21 is formed. That is, the N-type silicon substrate 20
After growing SiO ₂ on the entire surface by thermal oxidation, photolithography technology (photolithorraphy technolog
By y), a resist pattern is formed only in the well formation region. By using the resist as a mask, SiO ₂ in this portion is removed by etching, and further P-type impurities such as boron are ion-implanted by implantation or the like. After removing the resist, the ion-implanted boron is thermally diffused to form the P well 21 relatively deep. At this point, the resist and SiO ₂ have been used and are removed.

When the above P well forming step is completed, FIG.
As shown in (b), a gate oxide film 25 and an address gate 26 are formed. That is, a relatively thin thermal oxide film is formed on the surface of the P well 21 at a thermal oxidation temperature of 900 to 1000 ° C. And LPCVD (Low Pressure Cm
Polysilicon is deposited on the entire surface of the thermal oxide film by the emical vapor deposition method, and the polysilicon is doped with a conductive material such as phosphorus at a high concentration. Next, a resist pattern is formed on the polysilicon, and the polysilicon and the thermal oxide film are etched using the resist pattern as a mask to form a gate oxide film 25 and an address gate 26. Regarding etching, RIE (reactive io
n etching) is preferably used.

When the steps of forming the gate oxide film and the address gate are completed, as shown in FIG.
The O film 27 is formed. That is, a silicon oxide film is laminated to a thickness of about 70Å over the entire surface by the CVD method, and the upper portion of the silicon oxide film is thermally nitrided by about 50Å to form a silicon nitride film. Further, a silicon oxide film is thinly stacked on the silicon nitride film by the CVD method to have a thickness of about 40Å. As a result, the ONO film 27 in which the nitride film is sandwiched between the bottom oxide film and the block oxide film is formed.

When the ONO film forming step is completed, FIG.
As shown in (d), the sidewall gate 28 is formed. That is, polysilicon is deposited on the entire surface by the LPCVD method, and polysilicon is doped with a conductive material such as phosphorus at a high concentration. Subsequently, the polysilicon is etched back to form sidewalls on both sides (source region and drain region side) of the gate oxide film 25 and the address gate 26. Then, the other side wall (source region side) is removed by etching. As a result, one side wall (drain region side) becomes the side wall gate 28.

When the sidewall gate forming step is completed, the source region 22 and the drain region 23 are formed as shown in FIG. 6 (e). That is, using the sidewall gate 28, the ONO film 27, the address gate 26, and the gate oxide film 25 as a mask, the source region 22 and the drain region 23 are ion-implanted with N-type impurities such as phosphorus by implantation. Form in a self-aligned manner.

When the side wall gate forming process is completed, the memory gate 29 is formed as shown in FIGS. 7 (a) to 7 (c). That is, as shown in FIG. 7A, after the BPSG 30a is thickly deposited on the entire surface by the CVD (Cmemical Vapor Deposition) method,
As shown in (b), the reflow process is performed until the upper portion of the sidewall gate 28 is slightly exposed, and then the BPSG 30 is formed.
Make a flat.

Then, as shown in FIG. 7C, the LPC
Polysilicon is deposited on the entire surface by the VD method, and the conductive material such as phosphorus is doped in high concentration to the polysilicon. Next, a resist pattern is formed on the polysilicon. Subsequently, using the resist pattern as a mask, a predetermined region of the polysilicon is etched so that the polysilicon covers a part of the address gate 26 to form a memory gate 29 on the sidewall gate 28.

When the memory gate forming step is completed,
As shown in FIG. 7D, a metallization and passivation film 33 is formed. That is, the BPSG 30b is thickly deposited on the entire surface by the CVD method. Here, the BPSGs 30a and 30b become the interlayer insulating film 30.
Then, a resist is applied on the entire surface, and a hole is formed in the resist only at the wiring outlet. Next, using the resist as a mask, the interlayer insulating film 30 and the ONO film 27 are removed by etching by RIE, and a contact hole 31 is opened on the drain region 23. At this time, although not shown, similarly, the source region 22 and the address gate 26,
Contact holes are also opened in the portions corresponding to the memory gates 29. Then, after removing the resist, Al or the like is deposited by, for example, spattering, and wiring including the drain wiring 32 is formed by mask alignment and RIE. Then, an insulating material such as a nitride film (Si ₃ N ₄ ) is deposited on the entire surface by the CVD method to form the passivation film 33.

As described above, the side wall gate 28 is formed before the memory gate 29 is formed, and ions are implanted by using the side wall gate 28 and the address gate 26 as a mask to form the source region 22 and the drain region 23. Since it is formed in a self-aligned manner (Fig. 6 (d))
(See (e)), the channel length can be shortened even if the address gate 26 and the memory gate 29 are provided. Therefore, it is possible to cope with further miniaturization of the element.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, the case where the P-type silicon substrate is used is described, but the N-type silicon substrate may be used. Further, the charge storage film may be a NO (nitride-oxide) film instead of the ONO film.

[0044]

As is apparent from the above description, according to the present invention, the channel length can be shortened while ensuring high speed operation. Therefore, there is an excellent effect that it contributes to further miniaturization of the element.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the structure of a nonvolatile memory element according to an example of the present invention.

FIG. 2 is an equivalent circuit diagram of a nonvolatile memory device including a nonvolatile memory element.

FIG. 3 is a diagram schematically showing the operation of the nonvolatile memory element at the time of writing information.

FIG. 4 is a diagram schematically showing an operation of a nonvolatile memory element when erasing information.

FIG. 5 is a diagram schematically showing the operation of the nonvolatile memory element at the time of reading information.

FIG. 6 is a schematic cross-sectional view showing a method of manufacturing a nonvolatile memory element in the order of steps.

FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory element following FIG. 6 in step order.

FIG. 8 is a schematic cross-sectional view showing the structure of a conventional nonvolatile memory element.

[Explanation of symbols]

 20 N-type silicon substrate 21 P-well 22 Source region 23 Drain region 24 Channel region 25 Gate oxide film 26 Address gate 27 ONO film 28 Sidewall gate 29 Memory gate

Claims (2)

[Claims] 1. A non-volatile memory element for storing information by injecting or extracting charges, the semiconductor substrate having a predetermined first conductivity type, wherein a predetermined interval is provided on a surface layer of the semiconductor substrate. A source region and a drain region, which are formed by piercing and have a second conductivity type opposite to the first conductivity type, and a channel region formed so as to be sandwiched between the source region and the drain region, the drain region side being predetermined. A gate insulating film formed on a region other than the region; an address gate formed on the gate insulating film; a nitride formed on a predetermined region of the channel region so as to cover a partial region of the address gate; A charge storage film for storing charges including a film, a sidewall gate formed by depositing on the charge storage film corresponding to the side of the drain region of the address gate, On the side wall gate Rabbi, the nonvolatile memory element, characterized in that it comprises a memory gate formed so as to cover a part region of the address gate. 2. A method for manufacturing a nonvolatile memory element according to claim 1, wherein a gate insulating film and an address gate are sequentially formed on a predetermined region of a semiconductor substrate having a predetermined first conductivity type. A step of forming a charge storage film that stores a charge including a nitride film on the semiconductor substrate exposed on one side of the gate insulating film and the address gate in a state of covering a partial region of the address gate, A step of depositing a sidewall gate on a charge storage film corresponding to one side of the address gate, an impurity having a second conductivity type opposite to the first conductivity type using the address gate and the sidewall gate as a mask Implanting ions to form the source and drain regions in a self-aligned manner, and covering a part of the address gate on the sidewall gate. A method of manufacturing a non-volatile memory element, comprising the step of forming a memory gate in such a state.