JP2743571B2 - Semiconductor nonvolatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a semiconductor nonvolatile memory device having a floating gate electrode.

〔Overview〕

The present invention relates to a semiconductor non-volatile memory device in which a main portion of a channel region is formed in a direction substantially perpendicular to a substrate, wherein a surface where a floating gate electrode and a control gate electrode are in contact with each other via an insulating film is also formed on a surface parallel to the substrate direction. By forming, the integration degree is improved without deteriorating the performance.

[Conventional technology]

FIG. 6 is a schematic sectional view showing an example of a conventional semiconductor nonvolatile memory device.

A floating gate electrode 3 is formed on a P-type silicon substrate 1 via a first gate oxide film 2, and a control gate electrode 5 is formed thereon via a second gate oxide film 4. further,
A drain region 7 and a source region 8 doped with an N-type impurity are formed adjacent to a channel region 6 immediately below the gate on the P-type silicon substrate 1 to constitute a semiconductor nonvolatile memory device.

Next, the operation of the semiconductor nonvolatile memory device will be described. First, at the time of writing, a voltage is applied between the drain and the source and a voltage is also applied to the control gate electrode 5 to inject electrons (hot electrons) generated near the drain into the floating gate electrode 3. Floating gate electrode 3
Are held through the smoke-saving film surrounding the floating gate electrode 3. Next, at the time of reading, since the presence or absence of charges is generated in the floating gate electrode 3 in accordance with the presence or absence of writing, the threshold voltage is given and data can be taken out depending on whether or not a channel is formed. Will be. At the time of erasing, the erasing is performed, for example, by irradiating ultraviolet rays to escape electrons accumulated in the floating gate electrode 3.

[Problems to be solved by the invention]

In this conventional semiconductor non-volatile memory device, since its components are arranged horizontally with respect to the surface of the semiconductor substrate,
There is a drawback that it is difficult to improve the degree of integration while maintaining element performance.

In other words, the miniaturization of the semiconductor non-volatile memory device is attempted,
When the channel length is shortened, the electric field concentration near the drain is increased and hot carriers are easily generated, so that a read disturb (soft write) in which writing is performed at a low voltage at the time of reading occurs or a punch-through breakdown voltage is reduced. There is a problem.

In addition, the size of a unit element of a semiconductor nonvolatile memory device is limited by a channel length, a drain extraction electrode contact diameter, and an element separation width. Unless these dimensions are reduced at the same time, the degree of integration cannot be significantly improved. There were drawbacks.

The object of the present invention is to eliminate the disadvantages mentioned above,
An object of the present invention is to provide a semiconductor nonvolatile memory device capable of maintaining and improving performance while improving the degree of integration.

[Means for solving the problem]

The semiconductor nonvolatile memory device of the present invention is configured such that a main portion of a channel region is substantially perpendicular to a semiconductor substrate.
In a semiconductor nonvolatile memory device provided with a floating gate electrode, a control gate electrode, a source and a drain region,
The floating gate electrode and the control gate electrode are in contact with each other via an insulating film on two surfaces, a surface substantially parallel to a direction in which the main part of the channel region is formed, and a surface parallel to the substrate, The source region is formed on the surface of the semiconductor substrate, and the drain region is formed on a surface parallel to the semiconductor substrate and different from the surface of the semiconductor substrate so as to partially contact the channel region.

It is preferable that the surface of the floating gate electrode in contact with the control gate electrode via the insulating film has a substantially L-shaped cross section in a direction perpendicular to the substrate.

[Action]

The arrangement of the source, drain and channel regions is
By using semiconductor pillars to make the main part of the channel region perpendicular to the surface of the semiconductor substrate, the channel length is determined by the height of the semiconductor pillars. It can be miniaturized without performing. By forming the surface where the floating gate electrode and the control gate electrode are in contact with each other via the insulating film not only in a direction perpendicular to the substrate surface but also in two surfaces parallel to the substrate surface, the two gate electrodes Is increased, and the punch-through withstand voltage is improved.

For this reason, it is possible to manufacture a highly integrated semiconductor nonvolatile memory device while maintaining element performance.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a plan view showing a main part of a first embodiment of a semiconductor nonvolatile memory device of the present invention, and FIG. 1B is a schematic view taken along the line AA 'of FIG. 1A. The cross-sectional view and FIG. 1 (c) are schematic cross-sectional views along BB 'in FIG. 1 (a).

In the semiconductor nonvolatile memory device of the first embodiment, a first gate oxide film 2, which is a first gate insulating film, and a polycrystalline structure are formed on the side surface of a silicon pillar 9 formed by processing the surface of a P-type silicon substrate 1. A floating gate electrode 3 made of silicon, a second gate oxide film 4 serving as a second gate insulating film, and a control gate electrode 5 made of polycrystalline silicon are sequentially laminated, and a drain region 7 is formed above a silicon pillar 9. Source regions 8 are formed at the bottoms, respectively. Each silicon pillar, which is a unit element, is separated by an interlayer insulating film 10 and is electrically connected to a memory cell array by a word line 11 made of tungsten silicide and a bit line 12 made of aluminum.

The channel of the unit element transistor is formed on the channel region 6 adjacent to the drain region 7 and the source region 8, that is, on the surface of the silicon pillar 9.

Generally, in a semiconductor nonvolatile memory device having a floating gate electrode, the higher the ratio of the coupling capacitance that the floating gate electrode makes with the substrate and the control gate electrode, the higher the potential of the floating gate electrode can be, and the faster the reading and writing are. And the characteristics are excellent such as an improvement in the punch-through withstand voltage.

1A, the area of the second gate oxide film 4 is larger than that of the first gate oxide film 2, so that the floating gate electrode 3 There is an advantage that a large coupling capacity ratio can be obtained.
Therefore, the writing and reading operations are fast, and a high punch-through withstand voltage can be obtained. Further, the size of the unit element transistor is determined by the diameter of the contact connecting the drain region 7 and the bit line 12 and the distance between the silicon pillars 9, so that miniaturization can be easily performed.

A feature of the present invention is that the silicon pillar 9 shown in FIG.
The first gate oxide film 2, the floating gate electrode 3, the second gate oxide film 4 and the control gate electrode 5 are provided on the vertical surface of the silicon pillar 9, and the drain region 7 is formed on the silicon pillar 9. , A source region 8 is provided at the bottom,
As shown in FIG. 1, the surface of the floating gate electrode 3 in contact with the control gate electrode 5 via the second gate oxide film 4 is also formed on the surface parallel to the substrate surface in contact with the source region 8. The floating electrode 3, the second gate oxide film 4, and the control gate electrode 5 are formed in a substantially L-shaped cross section in a direction perpendicular to the substrate surface.

Next, a method for manufacturing the semiconductor nonvolatile memory device of the present invention will be described. 2 (a) to 2 (d) are schematic cross-sectional views in the main manufacturing process of the first embodiment of FIG. 1, and show cross-sectional views along AA 'in FIG. 1 (a).

First, as shown in FIG. 2A, the surface of the P-type silicon substrate 1 is processed to form a silicon pillar 9, and the surface is thermally oxidized to form the first gate oxide film 2. Then, a polycrystalline silicon film serving as the floating gate electrode 3 is formed by a chemical vapor deposition method, and the surface thereof is thermally oxidized to form a second gate oxide film 4. Next, a polycrystalline silicon thin film serving as the control gate electrode 5 and an oxide film 14 are sequentially formed by a chemical vapor deposition method.

Next, as shown in FIG. 2B, the oxide film 14 is first subjected to anisotropic dry etching to leave only the side wall serving as the surface protection film of the control gate electrode 5. Subsequently, the control gate electrode 5, the second gate oxide film 4, and the floating gate electrode 3 are sequentially removed by anisotropic dry etching. Arsenic is ion-implanted with the first gate oxide film 2 exposed at the top and bottom of the silicon pillar 9 to form the drain region 7 at the top of the silicon pillar 9 and the source region 8 at the bottom. I do.

Then, as shown in FIG. 2 (c), after a boron-doped phosphorus glass (BPSG) film is grown by chemical vapor deposition,
Annealing is performed at about the temperature, and an interlayer insulating film 10 is embedded between the silicon pillars 9. At this time, first, an interlayer insulating film 10 having a thickness enough to bury the upper part of the silicon pillar 9 is buried, the word line forming region shown in FIG. 1 is etched, tungsten silicide is formed by sputtering, and patterning is performed. . After forming the word lines in this way, the interlayer insulating film 10 is further grown.

Finally, as shown in FIG.
A contact hole is opened in the upper part of the substrate, aluminum is grown by a sputtering method, and this is patterned to form a bit line 12.

FIGS. 3 and 4 show the characteristics of the unit element transistor of the first embodiment.

FIG. 3 shows the relationship between the circumference L of the silicon pillar and the drain current _{ID of the} transistor, using the height L of the silicon pillar as a parameter. Here, the applied voltage V _CG = 5V of the control gate electrode and the drain voltage V _D = 1V
The drain current of the transistor was set to _ID . L
And W correspond to the gate length and gate width of the transistor, respectively, and have a relationship of I _D ∝W / L.

FIG. 4 shows the write characteristics of the unit element transistor where L = W = 1.2 μm, and the film thickness d of the control gate electrode is used as a parameter. As the film thickness d increases, the area of the second gate oxide film 4 also increases. As a result, the coupling capacitance ratio increases and the writing speed increases.

FIG. 5 is a schematic sectional view showing the structure of a second embodiment of the semiconductor nonvolatile memory device according to the present invention.

In the second embodiment, as in the first embodiment, the first gate oxide film 2 serving as the first gate insulating film is formed on the side surface of the silicon pillar 9 formed by processing the surface of the P-type silicon substrate 1. A floating gate electrode 3 made of crystalline silicon, a second gate oxide film 4 serving as a second gate insulating film, and a control gate electrode 5 made of polycrystalline silicon are sequentially formed, and a drain region 7 is formed on a silicon pillar 9 and a drain region 7 is formed on a bottom. A source region 8 is formed. Each silicon pillar 9 as a unit element
Are separated by an interlayer insulating film 10 and are electrically coupled as a memory cell array by a word line 11 made of tungsten silicide and a bit line 12 made of aluminum.

The features of the second embodiment are that the source region 8 is offset from the floating gate electrode 3 and the control gate electrode 5 is extended to above the offset channel region 15; Is 20 nm or less.

The operation of the semiconductor nonvolatile memory device according to the second embodiment is as follows: the height of the silicon pillar is 1.0 μm, the circumference of the silicon pillar is 3.2 μm, the thickness of the first gate oxide film 2 is 15 nm, and the channel length of the offset channel region 15 is 0.5. The case of μm will be described.

First, writing is performed by simultaneously applying a control gate electrode voltage of 14 V and a drain voltage of 7 V for 50 μsec or more to generate hot electrons near the drain and inject them into the floating gate electrode 3. Also, erase
By applying a drain voltage of 14 V for 1 second, a Fowler-Nordheim tunnel current flows through the first gate oxide film 2 between the drain and the floating gate electrode. Even if positive charges are stored in the floating gate electrode 3 at the time of erasing, the transistor maintains the enhancement type because the offset channel region 15 exists.

Reading can be performed with a control gate electrode voltage of 5 V and a drain voltage of 5 V.

If the semiconductor nonvolatile memory device of the second embodiment is used,
A flash EEPROM that can be electrically erased in a batch can be easily manufactured.

In the above description of the embodiment, the semiconductor pillar provided on the surface of the semiconductor substrate is taken up. However, the present invention can be similarly applied to a trench provided on the surface of the semiconductor substrate.

〔The invention's effect〕

As described above, according to the present invention, in a semiconductor nonvolatile memory device, a main portion of a channel region of a unit transistor is formed perpendicular to a surface of a semiconductor substrate, and a surface where a floating gate electrode and a control gate electrode are in contact with each other in a vertical direction. Not only that, it is also formed on a surface parallel to the substrate surface and has a substantially L-shaped cross-section and is large, so that the junction capacity is large and the punch-through withstand voltage can be increased.
There is an effect that it can be easily miniaturized without impairing the performance.

[Brief description of the drawings]

FIG. 1A is a plan view showing a first embodiment of the present invention. FIG. 1 (b) is a schematic cross-sectional view along AA 'of FIG. 1 (a). FIG. 1 (c) is a schematic cross-sectional view along BB 'shown in FIG. 1 (a). 2 (a) to 2 (d) are schematic cross-sectional views in main manufacturing steps. FIG. 3 is a graph showing drain current characteristics with respect to the gate width (W). FIG. 4 is a threshold voltage characteristic diagram with respect to the writing time. FIG. 5 is a schematic sectional view showing a second embodiment of the present invention. FIG. 6 is a schematic sectional view showing a conventional example. 1 ... P-type silicon substrate, 2 ... First gate oxide film, 3
...... Floating gate electrode, 4 ... Second gate oxide film, 5 ...
Control gate electrode, 6 channel region, 7 drain region, 8 source region, 9 silicon pillar, 10
... interlayer insulating film, 11 ... word line, 12 ... bit line, 13 ...
... Surface protection film, 14 ... Oxide film, 15 ... Offset channel region.

Claims (2)

(57) [Claims] 1. A semiconductor nonvolatile memory device provided with a floating gate electrode, a control gate electrode, and a source / drain region such that a main portion of the channel region is substantially perpendicular to a semiconductor substrate. The floating gate electrode and the control gate electrode are in contact with each other via an insulating film on two surfaces, a surface substantially parallel to the direction in which the main part is formed, and a surface parallel to the substrate, and the source region is A semiconductor non-volatile memory device formed on the surface of the semiconductor substrate, wherein the drain region is formed in parallel to the semiconductor substrate and partially in contact with the channel region on a surface different from the semiconductor substrate surface. . 2. A semiconductor according to claim 1, wherein a surface of said floating gate electrode in contact with said control gate electrode via said insulating film has a substantially L-shaped cross section in a direction perpendicular to a substrate. Non-volatile storage device.