JPH031574A - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a stereoscopic element structure and to reduce the area of a memory cell by utilizing the sidewall or bottom of a groove formed on the surface of a semiconductor substrate as a channel region of the cell. CONSTITUTION:A thick gate oxide film 12 formed on the sidewall of a groove 25 formed on the surface of a P-type semiconductor substrate 11, a thin gate oxide film 13, a floating gate electrode 14, first and second interlayer oxide films 15, 16 formed on the surface of the substrate 11 and the electrode 14, a control gate electrode 17 having a shape buried partly in the groove 25 for controlling the potential of the electrode 14 by a capacitance coupling, a N<+> type semiconductor region 18 and a N-type semiconductor region 20 (source region) provided on the surface of the substrate, a N<+> type semiconductor region 19 (drain region) formed in the bottom of the groove 25, and a P-type semiconductor region 21 (drain shield) are provided. A part between the drain region and the source region of the sidewall and bottom of the groove 25 becomes a channel region of a transistor.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device, and particularly to a structure and manufacturing method of a floating gate type nonvolatile memory cell that has both a small cell area and an electrical rewrite function.

[Prior Art 1] Conventionally, EPROM and E2PROM have been widely used as nonvolatile semiconductor memory devices whose memory contents can be rewritten. The above-mentioned EPROM has a high degree of integration, large capacity, and the accompanying low cost, while the E"FROM has a high function (easy to use) that allows the memory contents to be rewritten bit by bit electrically (that is, while installed in the device). However, there is a strong demand for a non-volatile semiconductor memory device that has both of these characteristics.Flash type E"FROM has an electrical rewrite function that is limited to chip-based (or block-based) erasing. However, many memory elements with new structures have been proposed and put into practical use to meet this requirement. For example, Floating Ga
teAsymmetric Source/ Drai
A typical example of this type of memory device is an oxide (n-type) memory element. This memory element has a floating gate field effect transistor structure of FAMOS type memory element and one memory element/bit, and is excellent in high integration. Writing in the above element is performed using hot electron injection as in the FAMOS type. On the other hand, chip-to-chip electrical erasing is similar to the conventional E"FROM,
This is done using the electron tunneling phenomenon. Specifically, a high positive voltage is applied to the source region with the control gate electrode and the semiconductor substrate grounded, and a high electric field of IOMV/am or more is applied to the gate oxide film between the floating gate electrode and the source region. As a result, electrons stored in the floating gate electrode are tunnel-emitted to the source region. At this time, while thinning the gate oxide film under the floating gate electrode over the entire surface (making it a tunnel oxide film),
Because the overlapping portion of the floating gate electrode and source region is formed in a self-aligned manner by diffusion and wrapping in the same region,
F can make the area where electrons tunnel extremely small.
This is a characteristic of the AST type. As a result, an externally applied voltage can be efficiently applied to the tunnel oxide film without intentionally increasing the overlapping area between the floating gate electrode and the control gate electrode. That is, electrical erasing at low voltage can be achieved without impairing the fineness of the cell. Note that in a FAST type memory element, writing is performed on the drain side and erasing is performed on the source side, so each junction profile is individually optimized. That is, an electric field concentration type profile is used for the drain junction to increase writing efficiency, while an electric field relaxation type profile is used for the source junction to which a high voltage can be applied during erasing. Such a structure is called a source-drain asymmetric structure. (Problems to be Solved by the Invention) In the conventional technology using the above-mentioned FAST type memory element, there were the following three problems.The first problem is that when performing an erase operation, the semiconductor substrate is This is because the gate oxide film is thinned uniformly over the entire surface of the floating gate electrode, so electrons generated by band-to-band tunneling on the surface of the source region that overlaps with the floating gate electrode. This is due to the hole out of the hole pair flowing out to the semiconductor substrate side, and is an essential phenomenon.The existence of this hole leakage current significantly increases the current consumption during erase operation. - The number of memory bits that can be erased simultaneously is limited. Also, as holes are removed to the semiconductor substrate side,
On the source region surface, the deep depletion state that causes band-to-band tunneling continues steadily throughout the erase operation, so the accompanying hole injection and trapping into the gate oxide film (tunnel oxide film) cannot be ignored. As a result, the controllability and reliability of the erase operation are impaired. The second problem is that the gate oxide film is thinned uniformly over the entire surface of the floating gate electrode, so when one of the memory elements arranged in an array is selected for a write operation, the cell The so-called drain disturb phenomenon, in which the threshold voltages of other memory elements connected to the same data line decrease, becomes noticeable. In other words, since the gate oxide film is also thinned at the end of the gate electrode on the drain region side, the electric field strength at the end of the drain region increases significantly during so-called half-selection, when a write voltage is applied only to the data line. , an avalanche occurs that cannot be ignored. A portion of the hot holes generated here are injected from the semiconductor substrate into the floating gate electrode, thereby lowering the threshold voltage. Furthermore, a mode in which electrons are emitted from the floating gate electrode to the drain region due to the write voltage applied to the data line cannot be ignored. The third problem is the fact that in the above-mentioned conventional FAST type memory element, since the elements are arranged in a plane, there is naturally a limit to miniaturization of the cell area. A first object of the present invention is to provide a structure and manufacturing method for an electrically rewritable nonvolatile memory element that has a smaller cell area than a conventional FAST type memory element. A second object of the present invention is to reduce current consumption (leakage current) during erase operation compared to conventional FAST type memory elements.
Another object of the present invention is to provide a structure and manufacturing method of an electrically rewritable nonvolatile memory element that has excellent controllability and reliability in erasing operations. A third object of the present invention is to provide a structure and manufacturing method for an electrically rewritable nonvolatile memory element that has improved drain disturb resistance without impairing the electrical erase characteristics of conventional FAST memory elements. Our goal is to provide the following. [Means for Solving the Problems] The above-mentioned objective is to solve the problem by
This is achieved by using the sidewall or bottom of either the trench or the hole as the channel region of the memory element. The second and third objectives are to adjust the thickness of the gate insulating film to a film suitable for electron tunneling in the region where the floating gate electrode overlaps either the source region or the drain region at the sidewall portion. This is achieved by locally thinning the film down to a thick layer. At this time, the locally thinned region needs to be present only in a predetermined portion of the overlapping region, that is, inside the high concentration source or drain region. Hereinafter, the existence of a thin film region only in a predetermined portion of the entire overlap region will be described below.
It is expressed as 'localizing the thinned region.' The thickness of the thinned part of the gate insulating film is 5.
It is desirable that the thickness be about 15 nm or more, and on the other hand,
The thickness of the part that has not been thinned is greater than 15 nm and is 11
It is desirable to set it to about 00n or less.

[For use]

By utilizing the sidewall or bottom of a step, groove, or hole provided on the surface of a semiconductor substrate as a channel region of a memory element, it becomes possible to realize a three-dimensional element structure and reduce the cell area. be able to. In addition, as will be described in detail in FIG. 15 below, the gate insulating film on the sidewall is locally thinned at the portion where the floating gate electrode and the source region (or drain region) overlap, and this thinned region is By localizing the source (or drain) inside the high concentration region, leakage current flowing to the semiconductor substrate during erasing operation can be removed. This is because holes generated by band-to-band tunneling (generated in the portion where the source region overlaps the floating gate electrode) no longer flow toward the semiconductor substrate. This makes it possible to perform the erase operation with the low current consumption inherent to tunnel erase, and also prevents undesirable hole injection and trapping phenomena into the gate oxide film, ensuring controllability and reliability of the erase operation. enable. Furthermore, since the gate oxide film is thicker on the drain region (or source region) side where hot electron injection programming is performed, undesirable electric field concentration caused in a half-selected state where a high programming voltage is applied only to the drain is alleviated. be done. As a result, electron tunneling and hole generation and injection, which cause threshold voltage fluctuations, are suppressed.
Drain half-select day starving is no longer a problem. In this way, improvements in erasing characteristics and drain half-selection disturb resistance, which have conventionally been in a trade-off relationship, can be simultaneously achieved.

【Example】

(Example 1) A first example of the present invention will be described below with reference to FIGS. 1 to 15. FIG. 1 is a cross-sectional view of a 4-bit memory cell of this embodiment, FIG. 2 is a plan view thereof (for 8 bits), and FIG. 3 is a configuration diagram of a memory cell array and peripheral circuit using the above memory cell. , FIGS. 4 to 9, and FIGS. 11 to 13.
The figure is a cross-sectional view of the same part as in Figure 1 (A-A' section of the plan view shown in Figure 2) in the process of manufacturing the memory cell, and Figure 10 is the same as Figure 2 in the process of manufacturing the memory cell. The plan view of the part, Fig. 14, is taken from B-B of the plan view shown in Fig. 2.
15 are potential diagrams inside the memory cell for explaining the junction leakage current reduction mechanism during erase operation in this embodiment. First, an outline of the operation of the memory cell array circuit will be explained using FIG. In FIG. 3, 31 is an X decoder that selects the word line WL, 34 is a word line drive circuit, 32 is a Y decoder that selects the data line DL and source line SL, 33 is a readout
This is a write/erase circuit. Also, Qm is a memory cell,
It consists of one insulated gate field effect transistor element having a floating gate electrode and a control gate electrode. The control gate electrode is connected to word line WL. Further, the drain region is connected to the data line DL, and the source region is connected to the source line SL. The array configuration is of a so-called virtual grounding type, and it is necessary to select a source line in addition to a data line during successive write operations. That is, the ground voltage Vss of the circuit, for example, Ov, is applied to the selected source line, and the unselected source lines are separated one by one and electrically opened during a write operation, and are electrically opened during a read operation. The potential is set to be the same as the read data line potential which will be described later. On the other hand, during erase operation. An erase voltage Vpp (IE), for example 12V, is applied to all source lines. At this time, all bits on the chip are erased simultaneously. Regarding the data line DL, a predetermined write voltage V pp (VD) (for example, 6V) is applied to the selected data line during the write operation. At this time, the unselected data lines are kept at the ground potential Vss. During a read operation, a predetermined continuous voltage (for example, IV) is simultaneously applied to all data lines. Also,
During the erase operation, all the data lines are separated one by one at the Y decoder and electrically opened to prevent unnecessary channel current from flowing from the source region to the drain region as the erase operation progresses. Regarding the word line WL, a predetermined continuous voltage (for example, 5V) and a predetermined write voltage Vpp (VW) (for example, 12V) are applied to the selected word line during the continuous write operation. At this time, unselected word lines are kept at the ground potential Vss. On the other hand, during the erase operation, all word lines are set to the ground voltage Vss. Next, the structure and characteristics of the memory cell according to this embodiment will be described using FIGS. 1 and 2. An insulated gate field effect transistor, which is a memory cell, has a thick gate oxide film 12) a thin gate oxide film 1 formed on the side wall of a trench 25 provided on the surface of a P-type semiconductor substrate 11.
3. Floating gate electrode 14) Substrate 11 and floating gate electrode 1
The first glabellar oxide film 15 and the second glabellar oxide film 16 formed on the surface of the gate electrode 4 are partially embedded in the groove 25, and the potential of the floating gate electrode 14 is controlled by capacitive coupling. Control gate electrode 1.7) n provided on the substrate surface
The 10-type semiconductor region 18, the n-type semiconductor region 20 (source region), and the n0-type semiconductor region 19 (
(drain region) and a p-type semiconductor region 21 (drain shield). The gate oxide films 12 and 13 described above are both made of silicon oxide films formed by thermal oxidation of the semiconductor substrate 11, and have a film thickness of about 10 nm at the thin part 13 and about 30 nm at the thick part 12. The n÷ type semiconductor region 18 (source region) and the floating gate electrode 14 face each other with the thin gate oxide film 13 in between, and this region becomes an electron tunnel region. The thin gate oxide film 13 extends by 0.2 μm in the depth direction of the trench sidewall. Note that this thin gate oxide film portion is localized only in the inner portion of the n-type semiconductor region 18 and does not protrude into the n-type semiconductor region 2o. The first and second interlayer oxide films 15 and 16 are formed on the semiconductor substrate 11 (single crystal silicon) or the floating gate electrode 14 (
Polycrystalline silicon) consists of a silicon oxide film whose surface is thermally oxidized, and has a thickness of approximately 100 nm, 20 to 30 m, respectively.
It has a film thickness of about nm. The control gate electrode 17 is made of, for example, a second layer of polycrystalline silicon film, a part of which is buried in the trench 25 and functions to control the potential of the floating gate electrode through capacitive coupling, and is integrated with the word line WL. and extends over the substrate surface. The n-type semiconductor region 19 has a junction depth of about 0.2 μm, and serves as the drain of the memory transistor.
A data line is formed along the bottom surface of the groove 25. This diffusion layer data line is connected to an aluminum data line 23 running in parallel on the third glabellar insulating film 22. Further, a p-type semiconductor region 21 is formed to cover the drain region, thereby preventing punch-through during erase operation and improving channel hot electron injection efficiency during write operation. The carrier concentration of the p-type semiconductor region 21 is 5
10''/am' and extends to a depth of about 0.4 μm.
serves as the source of the memory transistor, and forms a source line between the trench 25 on the substrate surface and the adjacent trench. This diffusion layer source line is connected to the third glabella insulating film 22.
It is connected to an aluminum source line 24 running in parallel above. The junction depth of the above-mentioned n-type semiconductor region 18 is about 0.3 μm, and the sidewall portion of the trench 25 in which the thin gate oxide film 12 (electron tunnel region) is formed is completely covered with the n÷-type semiconductor region 18. Covered. On the other hand, the n-type semiconductor region 20 is provided so as to be interposed between the n-type semiconductor region 18 and the P- type semiconductor substrate 11, and serves to increase the breakdown voltage of the source junction. The carrier concentration of the n-type semiconductor region 20 is about I x 1019/am3 at the interface with the n-type semiconductor region 18, the junction depth is about 0.5 μm, and the junction breakdown voltage at this time exceeds 17V. . Of the sidewalls and bottom of the trench 25, a portion between the drain region and the source region becomes the channel region of the transistor. The third interlayer oxide film 22 is made of, for example, phosphosilicate glass (PS
G) Control gate electrode 17 (word line WL) consisting of a film
and aluminum data line 23. It acts as an interlayer insulating film between the source lines 24. Write, erase, and read operations of stored information in the memory cell are performed by applying the voltages already explained in FIG. 3 to each region. First, in writing, the n+ type semiconductor region 19 of the drain region is
Among the hot carriers generated at the channel side end, some hot electrons are injected into the floating gate electrode 14, and the threshold voltage as seen from the control gate electrode 17 increases. On the other hand, in erasing, electrons held in the floating gate electrode 14 are tunnel-emitted through the thin gate oxide film 13 to the n+ type semiconductor region 18, which is a part of the source region, and are The value voltage will be lower. Furthermore, successive reading is performed by detecting the difference in threshold voltage between the written state and erased state as a difference in channel current. Furthermore, by providing a control circuit on the chip that automatically stops erasing when the threshold voltage of the memory transistor reaches approximately 1V during erasing operation, 1-element/bit type flash E"FROM can be (Manufacturing method) Next, a method of manufacturing the above memory cell will be explained with reference to FIGS. 4 to 14. As shown in FIG. After growing a surface oxide film 41 by thermal oxidation, the substrate 11 is grown using the photoresist film pattern 42 as a mask.
Grooves 25 having a width of 1 μm and a depth of 1 μm are formed at a pitch of 2 μm on the surface of the substrate. After forming the groove 25, the photoresist film pattern 4
2 and the surface oxide film 41 are removed. Next, as shown in FIG. 5, the surface of the substrate 11 and the groove 2 are
A thick gate oxide film 1 is formed by thermal oxidation on the side and bottom surfaces of 5.
After growing 2', a photoresist film 43 is buried in the trench 25 using an etch-back technique. Next, using the photoresist film 43 as a mask, the substrate 1 is
The thick gate oxide film 12' on the surface of the substrate 11 and the side walls of the groove 25 is etched by a wet etching method, and as shown in FIG. ′ is removed. After this wet etching, the photoresist film 43 buried in the trench 25 is removed. Next, as shown in FIG. 7, a thin gate oxide film 13 of 10 nm is grown again by thermal oxidation on the surface of the substrate 11 from which the thick gate oxide film 12' has been removed and on the side walls of the trench 25. At this time, the thick gate oxide film 12' remaining on the lower side wall and bottom of the trench 25 also increased in thickness, and finally reached a thickness of 30 nm.
This results in a thick gate oxide film 12. Next, as shown in FIG. 8, the surfaces of the gate oxide films 12 and 13 are deposited by chemical vapor deposition (CVD).
A polycrystalline silicon film 14' having a thickness of 250 nm is deposited. Next, an n-type impurity such as phosphorus (P) is added to the polycrystalline silicon film 14' at a high concentration (I x 10"/cm3 or more) by thermal diffusion or ion implantation, and the sheet resistance is set to 1. The conductivity is made to be about Ω/hole or less.Next, as shown in FIG. 9, anisotropic dry etching is applied to the entire surface of the polycrystalline silicon film 14' to form the grooves 25 that appear to have a large effective film thickness. Polycrystalline silicon film 14' along the sidewalls
leave. At this time, the selectivity of the anisotropic dry etching with respect to the underlying gate oxide films 12 and 13 was 10 or more. FIG. 10 is a plan view showing the polycrystalline silicon film 14' processed along the sidewalls of the groove 25. The polycrystalline silicon film on the surface of the substrate 11 and the bottom of the trench 25 has been completely removed. Further, the polycrystalline silicon film 14' is processed once again at the same time as the control gate electrode in a later step, and finally becomes the floating gate electrode 14. Next, as shown in FIG. 11, after the surface of the polycrystalline silicon film 14' is covered with an oxide film of about 20 nm by thermal oxidation, the surface of the substrate 11 is coated by repeating a photoresist masking process and an ion implantation process. is arsenic (As)
5X101s/cm" and phosphorus (P) 4X10"/
cm” and arsenic (As) IXI on the bottom of the groove 25.
O”/cm2 and boron (B) IX1014/0m2 are selectively introduced respectively. This is followed by heating at 1000°C for 6
By performing high-temperature heat treatment for 0 minutes, the n-type semiconductor region 18 and the n-type semiconductor region 20 constituting the source region,
An n-shaped semiconductor region 19) constituting a drain region and a p-type semiconductor region 21 shielding the drain region are respectively formed. As described above, by performing the step of forming the gate oxide film 12.13 before the step of forming the n-type semiconductor region 18, etc., the gate oxide film can be removed from the substrate before adding impurities. As a result, a high quality gate oxide film can be obtained. Next, the 50 nm thick silicon nitride film deposited by the CVD method is processed by anisotropic dry etching, leaving the silicon nitride film only on the side walls of the polycrystalline silicon film 14'. By performing thermal oxidation using this silicon nitride film as a mask, a first glabellar oxide film 15 is grown on the surface of the substrate 11 and the bottom of the groove 25, as shown in FIG. The thickness of this first interlayer oxide film 15 is 1100n. Furthermore, after removing the silicon nitride film with hot phosphoric acid, thermal oxidation is performed again to grow a second interlayer oxide film 16 with a thickness of 25 nm on the side wall of the polycrystalline silicon film 14'. Next, as shown in FIG. 13, a second polycrystalline silicon film 17' is deposited on the surfaces of the first and second interlayer oxide films by CVD.
Deposit by method. The thickness of this film is 300 nm. Next, an n-type impurity such as phosphorus (P) is added to the polycrystalline silicon film 17' by thermal diffusion or ion implantation.
After adding at a high concentration (lx102o/cm3 or more),
Using the photoresist film pattern as a mask, processing is performed by anisotropic dry etching to form the control gate electrode 17 (word line WL) shown in FIGS. 1 and 2. Further, following the processing of the control gate electrode 17, a polycrystalline silicon film 14' is formed using the same photoresist film pattern as a mask.
Then, floating gate electrodes 14 separated for each bit are formed. Next, a phosphosilicate glass (PSG) film is deposited by CVD to form a third interlayer oxide film. Subsequently, as shown in FIG. 2, contact holes 26 are formed above the source region on the surface of the substrate 11 and the drain region on the bottom surface of the groove 25. Next, as shown in FIG. 14, tungsten is buried in the contact hole to form a metal plug 26, and electrodes are taken out from the n-type semiconductor regions 18 and 19. Finally, an aluminum film is deposited and processed to form an aluminum data line 23 and an aluminum source line 2.
4 is formed, and the manufacturing process of the memory cell is completed. According to this embodiment described above, the following effects can be obtained. (1) By using the sidewalls of the trenches provided on the surface of the semiconductor substrate as channels of transistors, the cell structure becomes three-dimensional, and a fine memory cell can be realized compared to the conventional FAST type memory cell. For example, when a 0.5 μm level process technology is used, the cell area per bit is approximately 2 μm2. (2) A thin gate oxide film that tunnels electrons is provided inside the n÷-type semiconductor region that constitutes the source region, and the gate oxide film becomes thicker at the edges of the same n-type semiconductor region. As shown, the n÷ type semiconductor region 6 (corresponding to 18 in FIG. 1) and the floating gate electrode 3 (corresponding to 14 in FIG.
The thick gate insulating film 2 (corresponding to 12 in FIG.
The side wall surface is not in an inverted state in the portion. This region acts as an energy barrier for holes, and band-to-band tunneling occurs in the thin gate insulating film 2' (corresponding to 13 in Figure 1).
ling) can be prevented from flowing to the P-type semiconductor substrate 1. As a result, the leakage current between the n-type semiconductor region and the substrate during erase operation is significantly reduced (less than 1 pA per cell).
It becomes possible to perform the erase operation with the low current consumption inherent in tunnel erase. Furthermore, since the holes are accumulated under the thin gate insulating film 2' without flowing out into the P-type semiconductor substrate 1, the deep depression state that caused the hole generation is immediately eliminated. This suppresses undesirable hole injection and trapping phenomena into the gate oxide film, making it possible to ensure controllability and reliability of the erase operation. (3) On the drain region side where the write operation is performed, the gate oxide film thickness can be increased independently from the tunnel region on the source side, so the drain disturb resistance during write half selection is improved without impairing the erase speed. Ru. As a result, it becomes possible to expand the design margin of the write drain voltage. (4) Since the spread of the thin gate oxide film is determined by the wet etching time, the relationship between the spread and the n-type semiconductor region can be precisely controlled within a chip, between chips, between wafers, and between lots. becomes. (5) Since the thin gate oxide film that tunnels electrons is formed by oxidizing a low-concentration semiconductor substrate, there are fewer traps at the interface and in the film. This is effective in increasing the reliability of rewriting operations. (Embodiment 2) Hereinafter, a second embodiment of the present invention will be described using FIGS. 16 to 18. 16 and 17 are cross-sectional views of two bits of the memory cell of this embodiment, and FIG. 18 is a plan view thereof (for four bits). Note that FIG. 16 corresponds to section AA' in FIG. 18, and FIG. 17 corresponds to section BB' in FIG. 18. The configuration diagram and operation of a memory cell array and peripheral circuits using the above memory cells are the same as in FIG. 3 of the first embodiment, and will not be described here. The structure and characteristics of the memory cell according to this embodiment will be described below with reference to FIGS. 16 to 18. An insulated gate field effect transistor, which is a memory cell, has a thin gate oxide film 53) formed on the sidewalls of a trench 65 provided on the surface of a P-type semiconductor substrate 51) and a thick gate oxide film 52) formed on the sidewalls and bottom surface. Gate electrode 54. A first glabellar oxide film 55 formed on the surface of the substrate 51, and a second glabellar oxide film 5 formed on the surface of the floating gate electrode 54.
6. A control gate electrode 5 that controls the potential of the floating gate electrode 54 through capacitive coupling. 7) An n-type semiconductor region 58 and an n-type semiconductor region 60 formed on the surface of the substrate 51 in contact with the groove 65.
(source region), n+ type semiconductor region 59 (drain region), and P-type semiconductor region (drain shield). Both gate oxide films 52 and 53 are formed on the semiconductor substrate 51.
The thin portion 53 is made of a silicon oxide film formed by thermal oxidation of
The thick portion 52 has a film thickness of about 10 nm, and the thick portion 52 has a film thickness of about 30 nm. The n+ type semiconductor region 58 and the floating gate electrode 54 face each other with the thin gate oxide film 53 in between, and this region becomes an electron tunnel region. In addition,
The thin gate oxide film 53 has a thickness of 0.2μ in the depth direction of the trench sidewall.
It has spread about m. The first and second interlayer oxide films 55 and 56 are formed on the semiconductor substrate 51 (single crystal silicon) or the floating gate electrode 54 (
They are made of silicon oxide films whose surfaces are thermally oxidized (polycrystalline silicon), and have film thicknesses of approximately 1100 nm and 20 to 30 nm, respectively. The control gate electrode 57 is made of, for example, a second layer of polycrystalline silicon film, functions to control the potential of the floating gate electrode 54 through capacitive coupling, and extends over the substrate surface integrally with the word fiWL. . The n-type semiconductor region 59 has a junction depth of about 0.2 μm, and serves as the drain of the memory transistor.
A data line is formed between the parallel groove 65 and the adjacent groove. This diffusion layer data line is an aluminum data line running in parallel on the third interlayer insulating film 62.
i63 through a tungsten metal plug 85 embedded in the contact hole 66. Further, a p-type semiconductor region 61 is formed so as to cover the drain region, thereby realizing punch-through prevention during erase operation and improvement of channel hot electron injection efficiency during write operation. The carrier concentration of the p-type semiconductor region 61 is 5
10"/cm3, and extends to a depth of about 0.4 μm. Also, the n-medium semiconductor region 58 and the n-type semiconductor region 60
serves as the source of the memory transistor, and forms a source line between the trench 65 on the substrate surface and the adjacent trench. This diffusion layer source line is connected to the third interlayer insulating film 62.
It is connected to an aluminum source line 64 running in parallel thereon via a tungsten metal plug 85 embedded in a contact hole 66 . The junction depth of the n-type semiconductor region 58 is about 0.3 μm, and the sidewall portion of the trench 65 in which the thin gate oxide film 52 (electron tunnel region) is formed is completely covered by the n-medium semiconductor region 58. has been done. On the other hand, the n-type semiconductor region 60 is provided to be interposed between the n-medium semiconductor region 58 and the p- type semiconductor substrate 51, and serves to increase the breakdown voltage of the source junction. The carrier concentration of this n-type semiconductor region 60 is I x 10"/cm at the interface with the n-medium semiconductor region 58.
The junction depth is approximately 0.5 μm, and the junction breakdown voltage at this time exceeds 17V. Of the sidewalls and bottom of 1 m65, the portion between the drain region and the source region becomes the channel region of the transistor. Further, the third glabellar oxide film 62 is made of, for example, phosphosilicate glass (P
SG) film, and the control gate electrode 57 (word line WL
) and the aluminum data line 63 ) and the source line 64 . Writing, erasing, and reading operations of stored information in a memory cell are performed by applying the voltages described in FIG. 3 of the first embodiment to each region. In writing, some hot electrons among hot carriers generated at the channel side end of the n-type semiconductor region 59 in the drain region are injected into the floating gate electrode 54, and the threshold voltage as seen from the control gate electrode increases. becomes higher. On the other hand, in erasing, electrons held in the floating gate electrode 54 are tunnel-emitted through the thin gate oxide film 53 to the n-medium semiconductor region 58, which is a part of the source region, and the threshold voltage as seen from the control gate electrode is becomes lower. Also, reading. This is performed by detecting the difference in threshold voltage between the written state and erased state as a difference in channel current. Furthermore, by providing a control circuit on the chip that automatically stops erasing when the threshold voltage of the memory transistor reaches approximately 1V during erasing operation, a 1-element/bit type flash E2FROM can be realized. This is the same as in the first embodiment. According to this embodiment described above, effects similar to (2), (3), (4), and (5) described in the first embodiment can be obtained.

【Effect of the invention】

According to the present invention, it is possible to realize an electrically rewritable microscopic nonvolatile memory cell that consumes little current during an erase operation and has excellent reliability. This cell enables flash type (chip-batch erase type) which has higher integration density than conventional ultraviolet erase type EP ROM.
It becomes possible to realize E”FROM. 4)

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a memory cell according to a first embodiment of the present invention, FIG. 2 is a plan view of a memory cell according to a first embodiment of the present invention, and FIG. 3 is a diagram of a memory cell array and peripheral circuit according to a first embodiment of the present invention. 4 to 14 are diagrams showing the manufacturing process of the memory cell of Example 1 of the present invention, and FIG. 15 is a diagram showing the inside of the memory cell for explaining the mechanism for reducing junction leakage current during erase operation in the present invention. 16 and 17 are cross-sectional views of a memory cell according to a second embodiment of the present invention, and FIG. 18 is a plan view of a memory cell according to a second embodiment of the present invention. Explanation of symbols> 1...p-type semiconductor substrate 2...gate oxide film 2
″...Gate oxide film thinning region 3...Floating gate electrode 4...Interlayer insulating film 5...
...Control gate electrode 6...n-type semiconductor region (part of source region) 7...
・N-type semiconductor region (part of source region) 1...P-type semiconductor substrate 2...Thick gate oxide film 2'...Thick gate oxide film 3...Thin gate oxide film (tunnel oxide film) )4...
Floating gate electrode 4'...Polycrystalline silicon film 5...First glabellar oxide film 6...Second interlayer oxide film 17...Control gate electrode 7'...Polycrystalline silicon film 8... . . . n-type semiconductor region (part of source region) 9 . . .
・n ten type semiconductor region (part of drain region) 0...n
type semiconductor region (part of source region) 1...p type semiconductor region (drain shield) 2...third interlayer oxide film 23...aluminum data line DL (connected to drain region) 24... Aluminum source line SL (connected to source region) 25... Groove 26 on semiconductor substrate surface... Contact hole 31... X decoder 32... Y decoder 33... Read, write, erase circuit 34... ...Word line drive circuit 41...Surface oxide film 42...Photoresist film 43...Photoresist film 44...Surface oxide film 45...Tungsten plug 51...P- type semiconductor substrate 52... ... Thick gate oxide film 53 ... Thin gate oxide film (tunnel diagonal film) 54
...Floating gate electrode 55...First interlayer oxide film 56...Second glabellar oxide film 57...Control gate electrode 58...N0 type semiconductor region (part of source region) 59
. . . n-type semiconductor region (part of the drain region) 60.
...n-type semiconductor region (part of source region) 61...p
type semiconductor region (drain shield) 62...Third eyebrow oxide film 63...Aluminum data line DL (connected to drain region) 63...Aluminum source line SL (connected to source region) 65...Semiconductor Groove 66 on the substrate surface...Contact hole 85...Tungsten plug. WL...Wide line DL...Data line S
L...source line

Claims (1)

[Claims] 1) An insulated gate field effect transistor having a floating gate electrode surrounded by an insulating film, the sidewall of at least one of a step, a groove, or a hole provided on the surface of a semiconductor substrate. 1. A nonvolatile semiconductor memory device characterized in that at least one of the top and bottom portions is used as an inversion channel portion of the insulated gate field effect transistor. 2) An insulated gate field effect transistor having a floating gate electrode surrounded by an insulating film, and using a side wall of at least one of a step, a groove, or a hole provided on the surface of a semiconductor substrate as an inversion channel part. A high concentration impurity region of a conductivity type opposite to that of the semiconductor substrate provided at the bottom of the step, groove, or hole is used as a drain region, and is provided on the surface of the semiconductor substrate in contact with the step, groove, or hole. A nonvolatile semiconductor memory device characterized in that a highly concentrated impurity region having a conductivity type opposite to that of the semiconductor substrate is used as a source region. 3) An insulated gate field effect transistor having a floating gate electrode surrounded by an insulating film, in which the floating gate is connected to a sidewall of at least one of a step, a groove, and a hole provided on the surface of a semiconductor substrate. A nonvolatile semiconductor memory device characterized in that a part of a gate insulating film of an electrode is locally made thinner than other parts. 4) An insulated gate field effect transistor having a floating gate electrode surrounded by an insulating film, in which the floating gate is connected to a side wall of at least one of a step, a groove, and a hole provided on the surface of the semiconductor substrate. A portion of the gate insulating film of the electrode is locally made thinner than other portions, and a high concentration impurity region of a conductivity type opposite to that of the semiconductor substrate formed on the surface of the semiconductor substrate is in contact with the side wall. A nonvolatile semiconductor memory device characterized in that the locally thinned region described above is provided inside the region. 5) By applying a high voltage with a polarity that reverse biases the region to the high concentration impurity region, charges (electrons or holes) are generated in the locally thinned portion of the gate insulating film.
4. The nonvolatile semiconductor memory according to claim 4, wherein the nonvolatile semiconductor memory is configured to generate a high electric field that causes a tunnel transition, and extract the charges stored in the floating gate electrode to the high concentration impurity region. Device. 6) The nonvolatile semiconductor memory device according to any one of claims 1 to 5, wherein information is retained even when power is cut off by storing charges (electrons or holes) in the floating gate electrode. 7) The nonvolatile semiconductor memory according to any one of claims 1 to 5, further comprising means for determining the presence or absence or amount of charges (electrons or holes) stored in the floating gate electrode from an external terminal. Device. 8) The nonvolatile semiconductor memory device according to any one of claims 1 to 5, further comprising means for controlling the potential of the floating gate electrode from an external terminal. 9) The nonvolatile semiconductor memory device according to any one of claims 1 to 5, further comprising a control gate electrode that controls the potential of the floating gate electrode through capacitive coupling. 10) When manufacturing the nonvolatile semiconductor memory device according to claim 4, a step of forming the gate insulating film is performed before the step of forming the high concentration impurity region. A method for manufacturing a semiconductor memory device. 11) A method for manufacturing a nonvolatile semiconductor memory device, characterized by including at least the following steps (a) to (c). (a) A process of forming at least one of steps, grooves, and holes on the surface of the semiconductor substrate. (b) A step of growing a first gate oxide film on at least the sidewall portions of the steps, grooves, and holes. (c) selectively removing the first gate oxide film from a predetermined portion of the side wall portion adjacent to the surface of the semiconductor substrate; (d) A step of growing a second gate oxide film, which is thinner than other parts, in a predetermined portion from which the first gate oxide film has been removed as described above.