JP2000138300A - Nonvolatile semiconductor storage device and its writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the operating voltage value of a memory cell of MONOS type, etc., to a value not larger than 10 V, while keeping intact its well disturbance characteristic and its high-speed writing characteristic. SOLUTION: In a memory transistor (M11, etc.), a gate electrode and gate insulation films, including a tunnel insulation film, are laminated on the semiconductor-channel forming region provided on the surface of a substrate to provide discretely in the form of a plane charge storing means in the gate insulation film. The memory transistor has, above the gate electrode or a wiring layer connected with the gate electrode (e.g. word line WL1, etc.), a pull-up electrode closing thereto via a dielectric film. The pull-up electrode is connected with a pull-up gate biasing circuit 102 for applying a predetermined voltage to the pull-up electrode. The pull-up gate biasing circuit 102 feeds to the pull-up electrode through a capacitive coupling, via a selective transistor ST0 a voltage tending to boost the gate electrode (the word line WL1, etc.).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage means (for example, a MONOS type or MNOS type) which is discretized planarly in a gate insulating film between a channel forming region of a memory transistor and a gate electrode. A charge trap in the nitride film, a charge trap near the interface between the top insulating film and the nitride film, or a small-diameter conductor, and electrically injects charges (electrons or holes) into the charge storage means. The present invention relates to a nonvolatile semiconductor memory device having a basic operation of storing and extracting data and a writing method thereof.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory, an FG in which charge storage means (floating gate) for holding charges is continuous in a plane is used.
In addition to the (Floating Gate) type, the charge storage means is discretized planarly, for example, MONOS (Metal-Oxide-Nitride).
-Oxide Semiconductor) type.

In a MONOS type nonvolatile semiconductor memory,
The nitride film [Six Ny (0
<X <1, 0 <y <1)] because carrier traps in the film or at the interface between the top oxide film and the nitride film are spatially discrete (that is, in the plane direction and the film thickness direction) and spread. In addition to the tunnel insulating film thickness,
It depends on the energy and spatial distribution of the charge trapped by the carrier trap in the xNy film.

When a leak current path is generated locally in the tunnel insulating film, a large amount of charge leaks through the leak path in the FG type, and the charge retention characteristic is apt to be deteriorated. Since the means is spatially discretized, local charges around the leak path only leak locally through the leak path, and the charge retention characteristics of the entire storage element are unlikely to deteriorate. Therefore, MO
In the NOS type, the problem of deterioration of the charge retention characteristics due to the thinning of the tunnel insulating film is not as serious as in the FG type. Therefore, the scaling property of the tunnel oxide film in the micro memory transistor having an extremely short gate length is MON
The OS type is superior to the FG type.

For a nonvolatile memory such as the MONOS type described above, in which charge storage means of a memory transistor is discretely planarized, cost reduction per bit and high integration are realized to realize a large-scale nonvolatile memory. Is 1
It is essential to realize a transistor type cell structure. However, in a conventional nonvolatile memory such as a MONOS type, a two-transistor type in which a selection transistor is connected to a memory transistor is mainstream, and various studies are currently being conducted to establish a one-transistor cell technology.

In order to establish the one-transistor cell technology, it is necessary to optimize the device structure centered on the gate insulating film including the charge storage means and to improve the reliability, as well as to improve the disturb characteristics. As one measure for improving the disturb characteristics of the MONOS type nonvolatile memory, the tunnel insulating film is formed to have a normal thickness (1.6 nm to 2.0 nm).
(nm) are being studied in the direction of setting the thickness to be thicker.

In order to reduce the cost per bit of the nonvolatile memory and to increase the degree of integration, it is necessary to reduce the area of the peripheral circuit in addition to the miniaturization of the memory cell itself. In the area reduction of the peripheral circuit, from the viewpoint of securing reliability due to the miniaturization of the memory cell and reducing the circuit load of the peripheral circuit,
It is important to reduce the write voltage and the erase voltage.

[0008]

SUMMARY OF THE INVENTION However, MONOS
In a nonvolatile semiconductor memory in which charge storage means is discretely planarized such as a type, when the tunnel insulating film thickness is set relatively thick, the tunnel probability in the tunnel insulating film differs between electrons and holes. And the magnitude (absolute value) of the erase voltage becomes asymmetric. For example, ONO
When the film thickness is 2.9 / 5.0 / 3.5 nm, the write voltage is usually 10 V to 12 V and the erase voltage is -7 V to -8 V
About. In this case, the asymmetry of the write / erase voltage is not remarkable when the tunnel insulating film is about 2 nm.
This is caused by the increase in the film thickness from about nm to about 2.9 nm.

Therefore, in the conventional nonvolatile semiconductor memory of the MONOS type or the like, although the operating voltage is lower than that of the FG type, it is difficult to maintain the effect of improving the disturb characteristics by increasing the thickness of the tunnel insulating film. There is an issue of how to further reduce the voltage. Especially when the operating voltage is asymmetric, the higher voltage (usually,
It is necessary to lower the voltage so that the write voltage approaches the lower voltage (usually the erase voltage).

An object of the present invention is to provide a memory cell array such as a MONOS type, which has a better tunneling film scaling property than an FG type, in which a charge is accumulated in a carrier trap or the like which is discretized in a plane, and which performs a basic operation. An object of the present invention is to provide a nonvolatile semiconductor memory device having a cell structure capable of reducing an operating voltage during high-speed writing while maintaining characteristics. Another object of the present invention is to provide a writing method for a nonvolatile semiconductor memory device including a suitable bias setting method for the cell structure.

[0011]

A nonvolatile semiconductor memory device according to the present invention comprises a substrate, a semiconductor channel formation region provided on the substrate surface, and a tunnel insulating film provided on the channel formation region. A gate insulating film, a gate electrode provided on the gate insulating film, and charge storage means provided in the gate insulating film and discretely planarized at least in a plane facing the channel formation region A memory transistor having a plurality of memory transistors having a plurality of memory transistors arranged in a word direction and a bit direction, the memory transistors being close to (at least the upper surface of) the gate electrode or a wiring layer connected to the gate electrode via a dielectric film. It has a pull-up electrode.

In addition, there is provided a pull-up gate bias means for applying a predetermined voltage to the pull-up electrode. Preferably, a plurality of gate electrodes of the memory transistor are connected to each of a plurality of word lines, and a selection transistor is connected between the pull-up gate bias means and the pull-up electrode, and the pull-up gate bias means Supplies a voltage in a direction in which the precharged word line is further boosted by capacitive coupling to the pull-up electrode via the selection transistor.

A writing method for a nonvolatile semiconductor memory device according to the present invention is directed to a gate insulating film including a substrate, a semiconductor channel forming region provided on the substrate surface, and a tunnel insulating film provided on the channel forming region. A memory, comprising: a gate electrode provided on the gate insulating film; and charge storage means provided in the gate insulating film and discretely planarized at least in a plane facing the channel formation region. What is claimed is: 1. A writing method for a nonvolatile semiconductor memory device comprising a plurality of transistors arranged in a word direction and a bit direction, the method comprising: pulling a gate electrode or a wiring layer connected to the gate electrode (at least the upper surface) through a dielectric film. A step of applying a predetermined voltage to the up electrode to increase the potential of the gate electrode. Preferably, the method includes a step of applying a program voltage of 10 V or less to a gate electrode of the selected memory transistor. By applying the program voltage before applying the voltage to the pull-up electrode, the gate electrode is precharged in advance, and then the gate electrode is further boosted by applying the voltage to the pull-up electrode.

The nonvolatile semiconductor memory device and the writing method according to the present invention are of an AND type, DINOR.
It is suitable for a NOR type or a NAND type including those in which bit lines and source lines such as a HiCR type are hierarchized.
Further, the present invention is suitable for a fine NOR type cell configuration in which bit lines or source lines are wired in a meandering manner. further,
The present invention relates to a MONOS type or MNOS type or the like including a nitride film or an oxynitride film on a tunnel insulating film in a gate insulating film, or a small-diameter conductor insulated from each other on a tunnel insulating film in a gate insulating film. It is suitable for a small particle size conductor type containing.

In the nonvolatile semiconductor memory device and the writing method according to the present invention, the gate electrode or the word line can be boosted in accordance with, for example, the voltage applied to the gate electrode or the pull-up electrode capacitively coupled to the word line. it can. Therefore, the word line applied voltage (program voltage) at the time of writing can be reduced as compared with the conventional case. Further, when the program voltage and the word line applied voltage (erase voltage) at the time of erasing are asymmetric, it is possible to lower the higher voltage so as to approach the lower voltage. For example, the operating voltage is asymmetric, that is, the program voltage is 10 V to 12 V,
When the erase voltage is -7 V to -8 V, the program voltage having a high voltage can be reduced without lowering the program speed (write speed). Thus, a nonvolatile semiconductor memory having an operating voltage of 10 V or less can be realized with the writing speed set to, for example, 1 msec or less.
Further, by reducing the program voltage until it becomes symmetric with the erase voltage, the configuration of the high voltage generating circuit for generating the operating voltage can be greatly simplified.

In the FG type non-volatile semiconductor memory, the absolute value of the program voltage and the erase voltage are almost the same (for example, 17V to 20V) in the whole channel tunnel injection / tunnel discharge type in which scaling is advantageous. , Never asymmetric. Therefore, even if the low-voltage technique of the present invention is applied to writing in the FG type nonvolatile semiconductor memory, the asymmetry of the operating voltage is increased. In addition, since the erase voltage is not reduced, the FG type still requires a large negative voltage of −17 V to −20 V as the erase voltage. Therefore, in the FG type, no matter how much the program voltage is reduced,
The configuration of the operating voltage generation circuit cannot be simplified very much.

In the nonvolatile semiconductor memory device and the writing method thereof according to the present invention, in addition to the above-described configuration, it is desirable to add a configuration capable of improving the disturb characteristic in order to realize a one-transistor cell. That is, in the nonvolatile semiconductor memory device according to the present invention, the memory transistor includes a source region in contact with the channel formation region;
A drain region that is separated from the source region and is in contact with the channel formation region; a plurality of gate electrodes of the memory transistor are connected to each of the plurality of word lines; and the source region or the drain region is electrically connected to the word line. The source region and / or the drain region of the memory transistor in which the gate electrode is connected to the word line selected at the time of writing and is connected to the common line in the bit direction that intersects in a substantially insulated state, Write inhibit voltage supply means for supplying a reverse bias voltage which becomes a reverse bias to the channel forming region via the common line, and applying a reverse bias voltage to the unselected word line with respect to the channel forming region at the time of writing. And non-selected word line bias means for supplying.

The write inhibit voltage supply means preferably supplies the reverse bias voltage to the source region and / or the drain region, thereby erroneously writing and / or erroneously writing the memory transistor connected to the selected word line. Bias to a voltage that will not be erased by mistake. The non-selected word line bias means preferably supplies the voltage in the reverse bias direction to the non-selected word line, thereby causing the memory transistor connected to the non-selected word line to be erroneously written and / or Bias to a voltage that will not be erased by mistake. The unselected word line bias means preferably biases the gate electrode with respect to the source region to an inhibit gate voltage or less.

Preferably, when the reverse bias voltage is applied in a state where the gate electrode of the memory transistor has the same potential as the channel formation region, a depletion layer is formed from the source region and the drain region to the channel formation region. Extend and unite. Further, the reverse bias voltage is applied with the gate electrode of the memory transistor having its gate electrode at the same potential as the channel formation region, and a depletion layer extends from the source region and the drain region to the channel formation region to unite. When the gate length is shorter than.

In a writing method for a nonvolatile semiconductor memory device according to the present invention, a memory in which a gate electrode is connected to a word line selected at the time of writing among a plurality of word lines commonly connecting the gate electrodes in a word direction. Through a bit-direction common line crossing the source region and / or the drain region of the transistor while being electrically insulated from the word line and coupling to the source region or the drain region,
A reverse bias voltage, which is a reverse bias, is applied to the channel formation region, and a voltage in a direction in which the channel formation region is reverse biased is applied to a non-selected word line during writing.

In the application of the reverse bias voltage, preferably, the same voltage is applied to both the source region and the drain region. Preferably, a program voltage is applied to a selected word line (precharge), a voltage is applied to the unselected word line, the reverse bias voltage is applied to the source region and / or the drain region, and a predetermined voltage is applied to a pull-up electrode. The application is performed in the order of application.

In the above-described nonvolatile semiconductor memory device and write method according to the present invention, as described above, the operating voltage is reduced or the asymmetry is corrected, that is, the write voltage is reduced when the write voltage is lower than the erase voltage. In addition to the above, for example, by a non-selected word line bias means, a gate of a non-selected memory transistor connected to a non-selected word line is inverted with respect to a channel formation region (for example, a substrate, a well, or a semiconductor thin film such as an SOI layer). Since the voltage in the direction of the bias is applied, for example, the electric field component perpendicular to the substrate in the direction of extracting electrons is reduced. For this reason, the upper limit of the write inhibit voltage (inhibit S / D voltage) range for the source and drain regions of the unselected memory transistors connected to the selected word line is, for example, twice or more the voltage value of the related art. Thus, the write inhibit voltage range is greatly expanded.

The expansion of the inhibit S / D voltage range is more conspicuous as the gate length is shorter, as opposed to the FG type.
This is a phenomenon peculiar to a nonvolatile memory device in which charge storage means such as an ONOS type is discretized in a plane. This phenomenon is related to the degree of depletion of the channel formation region due to the application of the inhibit S / D voltage, and the application of the gate voltage is effective in expanding the range of the inhibit S / D voltage. That is, in a non-volatile memory device in which the charge storage means is discretized in a plane, in the fine gate region having a short gate length, most of the channel is set under a voltage setting such that the potential of the non-selected word line is equal to the potential of the channel formation region. The fact that the formation region is depleted and an electric field component for extracting electric charges to the substrate side occurs in most of the channels is a factor that makes it impossible to secure a disturbance margin. This deterioration phenomenon is particularly remarkable when a depletion layer spreads from a source or a drain to a channel formation region and is united. Then, the application of a voltage to the unselected word line in the present invention causes a reduction in the electric field component.

On the other hand, in the FG type, when a reverse bias voltage is applied to the drain or the source, if the gate length is long, the voltage between the floating gate and the drain or the source becomes large, and the disturb margin is small. If the gate length is short, the coupling ratio between the drain or source and the floating gate increases, and the component of the floating gate voltage proportional to the change in the drain or source voltage also increases, and the disturb margin is rather improved. This improvement is particularly remarkable when the depletion layer spreads from the drain and source to the channel formation region and is united. Therefore, it is not necessary to apply a reverse bias voltage to the non-selected word line of the FG type element having a short gate length. As a result, the application of the reverse bias voltage is
This is effective for an FG type element having a long gate length. Therefore, application of, for example, a positive voltage to the non-selected word lines has a special meaning in a nonvolatile memory device in which the charge storage means is discretized in a plane, and the write disturb characteristic is improved by an operation different from that of the FG type. This is extremely effective for speeding up writing.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a diagram showing a schematic configuration of a source-separated NOR type nonvolatile semiconductor memory according to this embodiment.

In the nonvolatile memory device 100 of this embodiment, N
Each memory cell of the OR-type memory cell array is composed of one memory transistor. As shown in FIG. 1, memory transistors M11 to M22 are arranged in a matrix, and these transistors are wired by word lines, bit lines, and separated source lines. That is, each drain of the memory transistors M11 and M12 adjacent in the bit direction is connected to the bit line BL1, and each source is connected to the source line SL1. Similarly, each drain of the memory transistors M21 and M22 adjacent in the bit direction is connected to the bit line BL2, and each source is connected to the source line SL2. The gates of the memory transistors M11 and M21 adjacent in the word direction are connected to the word line WL1, and similarly, the gates of the memory transistors M12 and M22 adjacent in the word direction are connected to the word line WL2. In the entire memory cell array, such cell arrangement and connection between cells are repeated.

In this embodiment, a pull-up electrode is provided above the gate electrode of each memory transistor via a dielectric film, as will be described in detail later. The pull-up electrode of each memory transistor is commonly connected to, for example, a pull-up line wired in the word direction. That is, the pull-up electrodes of the memory transistors M11 and M21 adjacent in the word direction are connected to the pull-up line PL1, and similarly, the memory transistors M12 adjacent in the word direction are connected.
And M22 are connected to a pull-up line PL2.

A pull-up gate bias circuit 102 is connected to the pull-up lines PL1, PL2,... Via a common selection transistor ST0. The pull-up gate bias circuit 102 is a circuit for boosting a word line to a predetermined potential at the time of writing, and thereby a write voltage (hereinafter, referred to as a program voltage or a precharge voltage) applied to a word line selected at the time of writing. ) Can be reduced. In this control, it is necessary to make the word line electrically floating after the application of the program voltage. Therefore, each word line WL1, WL2,.
Are connected to a word line selection circuit (row decoder) (not shown) via the selection transistors ST1, ST2,.

FIG. 2 shows, as an example of a specific cell arrangement pattern, a fine NO using a self-alignment technique and a meandering source line.
It is a schematic plan view of an R-type cell array.

In this fine NOR type cell array 70, element isolation regions 71 such as trenches or LOCOS are arranged in the form of parallel stripes long in the bit direction (vertical direction in FIG. 2) on the surface of a p-well (not shown). Element isolation region 71
, Each word line WLm-2, WLm-1, WL
m and WLm + 1 are wired at equal intervals. This word line structure is composed of a laminated film of a tunnel insulating film, a nitride film, a top insulating film, and a gate electrode, as described later. Although not particularly shown, for example, pull-up lines of the same pattern are arranged on a word line via a dielectric film.

In the active region within the space between the element isolation regions, a source region and a drain region are alternately formed in a space separated from each word line, for example, by introducing an n-type impurity at a high concentration. The source and drain regions are
Its size is defined only in the word direction (horizontal direction in FIG. 2) by the interval between the element isolation regions 71 such as trenches or LOCOS, and in the bit direction only by the word line interval. Therefore, the source region and the drain region are formed very uniformly since almost no mask alignment error is introduced with respect to variations in size and arrangement.

Around each word line, only a sidewall is formed, and a contact hole for connecting a bit line and a contact hole for connecting a source line are formed twice with respect to a source region and a drain region. It is formed while diverting technology at the same time. Moreover, the above process does not require a photomask. Therefore, as described above, the size and arrangement of the source region and the drain region are uniform, and the size of the contact hole for connecting the bit line or the source line formed two-dimensionally in self-alignment with the source region and the drain region. It is also very uniform. Further, the contact hole has a size that is almost maximum with respect to the area of the source region and the drain region.

The source lines SLn-1, SLn, and SLn + 1, which are wired in the bit direction thereover, meander over the element isolation region 71 and the source region while avoiding the drain region. It is connected to each lower source region via a contact hole for connection. On the source line, bit lines BLn-1 and BLn-1 are interposed via a second interlayer insulating film.
Ln and BLn + 1 are wired at equal intervals. This bit line is located above the active region, and is connected to each of the underlying drain regions via a contact hole for connecting the bit line.

In the cell pattern having such a structure, as described above, the formation of the source region and the drain region is hardly affected by the mask alignment, and the contact hole for connecting the bit line and the contact hole for connecting the source line are formed. However, since the contact hole is formed by diverting the self-alignment technique twice, the contact hole does not become a limiting factor for reducing the cell area, and the source wiring and the like can be formed with the minimum line width F of the wafer process limit. Since there is almost no wasted space, 6F ²
And a very small cell area close to

FIG. 3 is a sectional view showing the element structure of the MONOS type memory transistor according to this embodiment.

In FIG. 3, reference numeral 1 denotes a semiconductor substrate such as a silicon wafer having n-type or p-type conductivity, 1a denotes a channel formation region, and 2 and 4 denote a source region and a drain region of the memory transistor. In the present invention, the “channel forming region” refers to a region where a channel through which electrons or holes conduct is formed inside the surface side. The “channel forming region” in this example corresponds to a portion sandwiched between the source region 2 and the drain region 4 in the semiconductor substrate 1. The source region 2 and the drain region 4 are regions having high conductivity formed by introducing an impurity of a conductivity type opposite to that of the channel formation region 1a into the semiconductor substrate 1 at a high concentration, and have various forms. Normally, an LDD (Lightly
In many cases, a low-concentration impurity region called “doped drain” is provided.

On the channel forming region 1a, a gate electrode 8 of the memory transistor is stacked via a gate insulating film 6. The gate electrode 8 is generally made of polysilicon (doped poly-Si) doped with p-type or n-type impurities at a high concentration and made conductive, or a laminated film of doped poly-Si and refractory metal silicide. . A pull-up electrode 18 is stacked on the gate electrode 8 with a dielectric film 16 interposed therebetween. The pull-up electrode 18 is generally made of doped poly-Si,
Alternatively, it is composed of a laminated film of doped poly-Si and refractory metal silicide.

The gate insulating film 6 in this embodiment is composed of a tunnel insulating film 10, a nitride film 12, and a top insulating film 14 in order from the lower layer. Tunnel insulating film 10
Is silicon oxide (SiO ₂ ) formed by thermal oxidation
However, in this example, the film is made of a nitrided oxide film obtained by nitriding SiO ₂ . Electron conduction through the tunnel insulating film 10 is performed using direct tunneling. The thickness of the tunnel insulating film 10 can be determined within a range of 2.0 nm to 3.6 nm according to the intended use, and is set to 2.8 nm here. Nitride film 12
Is, for example, 5.0 nm of silicon nitride (Six Ny (0
<X <1, 0 <y <1)). The top insulating film 14 needs to form deep carrier traps in the vicinity of the interface with the nitride film 12 at a high density.
For example, it is formed by thermally oxidizing a nitride film after film formation. When the top insulating film 14 is formed by CVD, this trap is formed by heat treatment. The thickness of the top insulating film 14 is
In order to effectively prevent holes from being injected from the gate electrode 8 and to prevent the number of times data can be rewritten, a minimum thickness of 3.0 nm, preferably 3.5 nm or more is required.

Next, an example of a method for manufacturing a memory transistor having such a configuration will be briefly described focusing on a step of forming a gate insulating film and a step of patterning a gate.

First, a rough flow of a basic manufacturing method will be described. An element isolation region is formed, a well is formed, and ion implantation for adjusting a threshold voltage is performed on the prepared semiconductor substrate 1 as necessary. After that, a stacked pattern of a gate insulating film 6, a gate electrode 8, a dielectric film 16 and a pull-up electrode 18 is formed on the active region of the semiconductor substrate 1, and the source / drain regions 2 and 4 are formed in a self-aligned manner. Then, an interlayer insulating film is formed and a contact hole is formed, a source / drain electrode is formed, and if necessary, an upper layer wiring is formed via an interlayer insulating layer, an overcoat film is formed, and a pad opening step is performed. Then, the nonvolatile memory transistor is completed.

In the step of forming the gate insulating film 6, first, the silicon substrate 1 is thermally oxidized by high-temperature short-time thermal oxidation (RTO) in an atmosphere in which diluted oxygen is mixed in nitrogen.
Next, high-temperature short-time thermal nitridation (RTN) is performed on the thermal oxide film in an ammonia atmosphere at, for example, a furnace temperature of 1000 ° C. and a processing time of 1 minute, thereby forming the tunnel insulating film 10.
(Final thickness 2.8 nm). Next, decompression CV
The nitride film 12 is deposited thicker by the method D so that the final film thickness becomes 5.0 nm. This CVD, for example,
The process is performed at a substrate temperature of 650 ° C. using an introduced gas in which dichlorosilane (DCS) and ammonia are mixed. In the formation of the silicon nitride film on the nitrided oxide film, if necessary, the pretreatment (wafer pretreatment) of the base surface and the film formation conditions may be optimized in order to suppress an increase in the roughness of the finished film surface. In this case, if the wafer pretreatment is not optimized, the surface morphology of the silicon nitride film is poor and accurate film thickness measurement cannot be performed. Therefore, after sufficiently optimizing the wafer pretreatment, the film is subjected to the next thermal oxidation step. The film thickness is set in consideration of the reduced silicon nitride film. For example, the surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form a top insulating film 14 of about 3.5 nm. This thermal oxidation is performed, for example, in a H ₂ O atmosphere at a furnace temperature of 950 ° C. As a result, a deep carrier trap having a trap level (an energy difference from the conduction band of silicon nitride) of about 2.0 eV or less is formed at a density of about 1 to 2 × 10 ¹³ cm ⁻² . The thermally oxidized silicon film (top insulating film 14) is formed to a thickness of 1.6 nm with respect to the nitride film 12 having a thickness of 1 nm. At this ratio, the thickness of the underlying nitride film decreases, and the final thickness of the nitride film 12 becomes 5 nm.

After forming the gate insulating film 6 in this manner, a film serving as the gate electrode 8 and a dielectric film 16 are formed. At this time, HTO (High tempe) is used as the dielectric film 16.
(rature chemical vapor deposited Oxide) or CVD
-A SiO ₂ film is formed to a thickness of, for example, about 10 nm. On the dielectric film 16, a conductive film to be a pull-up electrode 18 is formed. Thereafter, the conductive film serving as the pull-up electrode 18, the dielectric film 16, the conductive film serving as the gate electrode 8, and the gate insulating film 6
Is continuously etched by, for example, RIE. This completes the patterning of the gate electrode and the pull-up electrode. Thereafter, the nonvolatile memory transistor is completed through the above-described steps.

Next, the write operation of the nonvolatile memory having such a configuration will be described. Here, as shown in FIG. 1, the non-selected cell A depends on the connection relationship with the selected cell S.
To C. That is, the non-selected cell connected to the same selected word line WL1 as the selected cell S is A, and the cell connected to the non-selected word line WL2 is connected to the same selected source line SL1 and selected bit line BL1 as the selected cell S. The selected unselected cell is defined as C, and the unselected cell connected to the selected word line WL2 and connected to the unselected source line SL2 and the unselected bit line BL2 is defined as B.

FIG. 4 shows conditions for setting the write bias voltage for these four types of cells. First, the bit line BL1 and the source line SL1 to which the selected cell S is connected are held at a low-level voltage, for example, a ground potential of 0 V, and the other non-selected bit lines BL2 and source line SL2 are supplied with a high-level voltage, for example, 5 V Set. When the substrate potential is 0 V, a predetermined voltage, for example, 3.7 V is applied to the unselected word line WL2. In this state, a program voltage of 10 V or less, for example, 8 V is applied to the word line WL1 to which the selected cell S is connected via the selection transistor ST1 to precharge the selected word line WL1. Therefore, the potential of the gate electrode of the memory transistor constituting the selected cell S rises to about 8 V, but writing is not yet performed at this potential.

Next, the selection transistor ST1 connected to the selected word line WL1 is turned off, and the selected word line WL1 is turned off.
1 is electrically floating. Then, the selection transistor ST0 to which the pull-up line is connected is turned on,
The pull-up gate bias circuit 102 applies a predetermined voltage of 10 V or less, for example, 8 V to the pull-up line PL1 to which the selected cell S is connected. As a result, the voltage of the selected word line WL1 is raised to a voltage at which writing is possible. The final word line potential Vw after this boosting is expressed by the following equation.

[0046]

Vw = Vpc + C × Vpull (1)

Here, Vpc is the precharge voltage of the word line, C is the capacitance coupling ratio between the pull-up electrode and the word line,
Vpull indicates a voltage applied to the pull-up electrode (pull-up voltage).

In the above example, the precharge voltage Vpc and the pull-up voltage Vpull are both 8V. Here, assuming that the capacitance coupling ratio C is 0.5, the word line potential Vw after boosting is 12 V from the above equation (1). As a result, in the memory transistor M11 of the selected cell S, charges (electrons) are tunnel-injected into the charge storage means (carrier trap) from the entire surface of the channel formation region 1a of the semiconductor substrate 1, and the threshold voltage Vth changes to change the data. Is written.

FIG. 5 is a graph showing the write / erase characteristics of the nonvolatile memory transistor. In FIG.
If the threshold voltage Vth for defining the end of writing is defined as 2 V or more, the writing time is 0.2 m at a word line applied voltage of 12 V.
In 20 seconds, the word line applied voltage of 10 V is about 20 msec, and the word line applied voltage of 8 V is not completed even in 10 seconds. In the writing according to the present embodiment, the word line potential can be increased to 12 V beyond the maximum voltage 8 V used for writing by word line boosting.
High speed writing of about ec can be achieved. Further, it is possible to reduce the voltage applied to the word line until the absolute value is substantially the same between the time of writing and the time of erasing. As a result, it is possible to simplify the configuration of an operating voltage generation circuit (not shown) configured using high breakdown voltage transistors, and to achieve a reduction in chip area and power consumption.

Second Embodiment The present embodiment relates to a nonvolatile semiconductor memory having an isolated source type fine NOR type cell in which bit lines and source lines are hierarchized. FIG. 6 is a diagram showing a schematic configuration of the nonvolatile semiconductor memory according to the present embodiment.

In the nonvolatile memory device 110 of this example, the bit lines are hierarchized into main bit lines and sub-bit lines, and the source lines are hierarchized into main source lines and sub-source lines. The sub-bit line SBL1 is connected to the main bit line MBL1 via the selection transistor S11, and the sub-bit line SBL2 is connected to the main bit line MBL2 via the selection transistor S21. The sub-source line SSL1 is connected to the main source line MSL via the selection transistor S12, and the sub-source line SSL is connected via the selection transistor S22.
2 are connected.

The memory transistors M11 to M1n are provided between the sub bit line SBL1 and the sub source line SSL1.
Are connected in parallel, the sub bit line SBL2 and the sub source line SS
The memory transistors M21 to M2n are connected in parallel with L2. The n memory transistors connected in parallel to each other and two select transistors (S1
1 and S12 or S21 and S22) constitute a unit block constituting the memory cell array.

The gates of the memory transistors M11, M21,... Adjacent in the word direction are connected to the word line WL1. Similarly, memory transistors M12, M2
, Are connected to the word line WL2.
Each gate of the memory transistors M1n, M2n,... Is connected to a word line WLn. Are controlled by a selection line SG1, and the selection transistors S12, S22,... Are controlled by a selection line SG2.

Each memory transistor has, for example, the structure shown in FIG. 3, and a pull-up electrode is provided above a gate electrode via a dielectric film. As in the first embodiment, the pull-up electrode of each memory transistor is commonly connected to, for example, a pull-up line wired in the word direction.
Specifically, each pull-up electrode of memory transistors M11 and M21 is connected to pull-up line PL1, each pull-up electrode of memory transistors M12 and M22 is connected to pull-up line PL2, and each pull-up electrode of memory transistors M1n and M2n. The up electrode is connected to the pull-up line PLn. As in the first embodiment, the pull-up line PL
, PLn, are connected to a pull-up gate bias circuit 102 via a selection transistor ST0.

In the present embodiment, as in the first embodiment, the program voltage is reduced by boosting the word line.
Alternatively, since the program voltage and the erase voltage can be made symmetric, the configuration of the operating voltage generation circuit can be simplified.

The bit line and the source line are hierarchized, and the selection transistor S11 or S21 separates the parallel main transistor group in the unselected unit block from the main bit line MBL1 or MBL2. This is significantly reduced, which is advantageous for speeding up and reducing power consumption. Further, the selection transistor S12 or S2
By the operation of 2, the sub source line is separated from the main source line,
The capacity can be reduced.

In addition, a pseudo contactless structure in which the sub-wiring (sub-bit line and sub-source line) is formed of an impurity region can be provided, and the effective cell per bit has the same level as the NOR type cell shown in the first embodiment. Area can be realized.
For example, by using a trench isolation technique, a self-alignment fabrication technique (for example, a self-alignment contact formation technique used in the fine NOR type cell shown in FIG. 2), the occupied area becomes 6
A fine cell of F ² (F is the minimum design rule) can be manufactured. At the time of its manufacture, the sub-bit lines SBL1, SBL2
Alternatively, the sub source lines SSL1 and SSL2 may be formed of impurity regions or impurity regions to which silicide is attached, and the main bit lines MBL1 and MBL2 may be formed of metal wiring.

Further, the operation of writing the entire channel and erasing the entire channel can be adopted. Using the write / erase operation for the entire channel,
Since it is not necessary to use a double diffusion layer structure for suppressing the interband tunnel current in the drain or source impurity region, the source and drain impurity regions of the memory transistor are compared with the operation of extracting the accumulated charge from the impurity region. Excellent scalability. As a result, the scaling property of the cell is excellent, so that a memory transistor having a finer gate length can be realized.

Third Embodiment FIG. 7 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory according to this embodiment. The nonvolatile semiconductor memory 120 according to the present embodiment has the same configuration of the memory cell array and the same memory transistor structure as the first embodiment. Further, a configuration for boosting the gate electrode of the memory transistor, that is, as shown in FIG. 7, a pull-up electrode is provided on the memory transistor, and a pull-up line PL is provided on the pull-up electrode.
1 and PL2, and a pull-up gate bias circuit 102 is connected to the pull-up lines PL1 and PL2 via a selection transistor ST0, as in the first and second embodiments.

The nonvolatile semiconductor memory 1 according to the present embodiment
At 20, the new configuration is different from that of the first embodiment, that is, a reverse bias voltage is applied to the source region 2 and / or the drain region 4 (FIG. 3) of the unselected memory transistor connected to the common line in the bit direction. A write inhibit voltage supply circuit 122 and a non-selected word line voltage supply circuit 124 connected to the word line and applying a reverse bias voltage to the gate electrode 8 of the non-selected cell with respect to the channel forming region 1a are added.

Here, the "common line" refers to a line in which a source region or a drain region is directly connected in common between a plurality of memory transistors in a bit direction (in a column direction) or capacitively coupled. A so-called booster plate or the like corresponds to the source line. The example of FIG. 7 is a case where the common line is a bit line and a source line. In addition, “reverse bias voltage” refers to a source region or a drain region,
A voltage in a direction in which a pn junction formed between the semiconductor substrate or the bulk region of the semiconductor layer where the channel formation region is formed is reversely biased. Further, “a direction in which a reverse bias is applied to the channel formation region” refers to a direction in which the voltage application based on the potential of the channel formation region is on the plus side or the minus side. Specifically, the direction is positive when the conductivity type of the channel formation region is p-type, and is negative when the conductivity type of the channel formation region is n-type.

The write inhibit voltage supply circuit 122 and the unselected word line voltage supply circuit 124 provide the gate electrode 8, the source region 2 and the drain region 4 of the unselected memory transistor prior to programming the selected cell.
By applying a predetermined voltage to the non-selected cells A and B shown in FIG. 7, erroneous writing or erasing is prevented, and the program disturb margin is greatly improved.

Next, the write operation will be described.

When writing data to the selected cell S, first,
When the substrate potential is 0 V, a predetermined voltage, for example, 3.5 V is applied to the non-selected word line WL2 by the non-selected word line bias circuit 124. When the substrate potential is 0 V, a predetermined reverse bias voltage, for example, 5 V is applied to the unselected source line SL2 and the unselected bit line BL2 by the write inhibit voltage supply circuit 122. At this time, the selected source line SL1 and the selected bit line BL1 are connected to the ground potential 0
Hold at V. In this state, after applying a program voltage (for example, 8 V) to the selected word line WL1, the selected word line WL1 is brought into a floating state, and a pull-up voltage (for example, 8 V) is applied to the pull-up line PL1 by the pull-up gate bias circuit 102. ) Is applied. Then, in the memory transistor M11 of the selected cell S, its gate electrode 8 is
For example, the voltage is raised to about 12 V. As a result, charges are injected into the charge storage means (carrier trap) from the entire surface of the channel forming region 1a by tunneling, and the threshold voltage Vth changes to write data. If the bias voltage is applied in the order of voltage application to the non-selected word line, reverse bias voltage application, program voltage application, and pull-up voltage application as described above, the non-selected cell B is less likely to be disturbed. preferable.

In this writing method, the unselected word line W
By applying, for example, a positive voltage to L2, the disturb margin of the unselected cell B is expanded, and the unselected cell B is not erroneously written or erased. Further, by applying a reverse bias voltage to the unselected bit line BL2 and the unselected source line SL2, it is possible to prevent the non-selected cell A from being in a write state due to the application of the program voltage of the selected word line. The selected cell B is not erroneously written (and erroneously erased).

The fact that the voltage applied to the selected word line WL in this embodiment is reduced from, for example, about 12 V to about 8 V means that the same effect as in the first embodiment, that is, the reduction in operating voltage,
In addition to the correction of asymmetry, there is an effect that it is advantageous for preventing disturbance of the non-selected cells A and B.

The above description has been directed to the prevention of disturbance. In addition to this, it is necessary to check whether there is any problem with the withstand voltage (junction withstand voltage) when the source and the drain are reversely biased, and to confirm the main device characteristics. There is.

[Withstand Voltage of Memory Transistor] The current-voltage characteristics when the gate voltage is 0 V were examined in both the write state and the erase state. As a result, it was found that the breakdown voltage of the junction was about 10 V and did not depend on the written state or the erased state. However, it was found that the rising voltage in the sub-breakdown region near 3 V to 5 V was different between the written state and the erased state.

The gate voltage dependence of the current-voltage characteristics in the written state was examined. The breakdown voltage did not show the gate voltage dependency, and the rise voltage in the sub-breakdown region showed the gate voltage dependency. The sub-breakdown region is presumed to be caused by the band-to-band tunneling phenomenon on the surface of the drain / source region at the gate edge portion. However, since the current level is small, it is considered that this is not a problem here. Also, the breakdown voltage of about 10 V does not directly affect the inhibit characteristics because the upper limit of the source / drain applied voltage (inhibit S / D voltage) is about 7.5 V. From the above, 0.1
It has been found that the junction breakdown voltage does not become a limiting factor of the program disturb characteristic in the 8 μm MMONOS type memory transistor.

[Main Device Characteristics] The current-voltage characteristics in the written state and the erased state were examined. When the gate voltage was 0 V, the current value of the unselected cell at a drain voltage of 1.5 V was about 1 nA. The read current in this case is 10 μA
As described above, it is considered that an erroneous read of a non-selected cell does not occur. Therefore, the gate length is 0.18 μm.
It has been found that the MONOS type memory transistor of m has a sufficient margin of the punch-through withstand voltage at the time of reading. In addition, the read disturb characteristics at a gate voltage of 1.5 V were also evaluated, and a read time of 3 × 10 ⁸ sec or more was possible.

Data rewriting characteristics under write conditions (program voltage: 8 V, program time: 0.2 msec) and erase conditions (gate voltage at erase: -7 V, erase time: 100 msec) were examined. It was found that the number of times of data rewriting was good because the carrier traps were spatially discretized, and satisfied 1 × 10 ⁶ times. The data retention characteristic is 85 after 1 × 10 ⁶ data rewrites.
C., 10 years satisfied.

As described above, the MONOS of the 0.18 μm generation
It was confirmed that sufficient characteristics were obtained as a type nonvolatile memory transistor. FIG. 8 shows a table summarizing the above various characteristics.

In this embodiment, the upper limit of the inhibit S / D voltage of the non-selected cell B connected to both the non-selected word line and the non-selected bit line is obtained by applying, for example, a positive bias voltage to the non-selected word line. It was experimentally confirmed that the program disturb margin can be increased in a 0.18 μm generation MONOS nonvolatile memory. As a result of examining the gate length dependency of this effect, it was particularly remarkable in a region where the gate length was shorter than 0.2 μm. The effect of this improvement is that in the conventional case where the gate voltage is 0 V, the channel formation region is depleted by the reverse bias voltage, and O
The electric field component in the direction in which the retained charges in the NO film are pulled out to the substrate side is increased, and this is applied to shift the gate voltage to the channel forming region in the reverse bias direction (the positive direction in the present embodiment).
Is reduced by the application of a biasing voltage. It has also been found that raising the upper limit of the inhibit S / D voltage increases the program disturb margin of the non-selected cells A connected to the same non-selected bit line. Further, as a result of experimentally examining the withstand voltage of the transistor, it was found that the withstand voltage of the transistor was higher than the inhibit S / D voltage and did not become a limiting factor of the program inhibit characteristic. It was confirmed that there was no effect on the main device characteristics. The data indicating the expansion of the program disturb margin can be applied to the MONOS type memory transistor having a gate length of 0.18 μm generation or later based on the principle.

The expansion of the program disturb margin facilitates the realization of a one-transistor cell having a single memory cell transistor. To achieve this, it is necessary to increase the disturb margin and to use an enhanced memory cell that does not cause the depletion of the threshold voltage of the memory transistor. The thickness can be increased, whereby the threshold voltage in the erasing characteristics is less likely to be depleted, and a memory characteristic saturated with enhancement is obtained. In this aspect, a one-transistor cell is easily realized.

In a one-transistor cell, it is not necessary to arrange a selection transistor for each memory cell, so that the cell area can be reduced, and the cost and the capacity can be increased by reducing the chip area. As a result, the NO of the FG type nonvolatile memory
A large-capacity MONOS nonvolatile memory having a cell area equivalent to that of an R type, an AND type, a NAND type, or a DINOR type can be realized at low cost. Furthermore, since the thickness of the tunnel insulating film is relatively large, injection of holes into the charge storage means is suppressed, and as a result, deterioration of the tunnel insulating film due to holes is suppressed, and write / erase repetition characteristics (endurance characteristics) are improved. I do. Note that the write inhibit voltage supply circuit in this example can be used for effective enhancement operation by reading information in a state in which the source region is reverse-biased. Facilitated.

Fourth Embodiment In this embodiment, a modification of the element structure of the MONOS type nonvolatile memory will be described. FIG. 9 is a sectional view showing an element structure of the MONOS type memory transistor.

The MONOS nonvolatile memory of the present embodiment is different from the first embodiment in that the gate insulating film 20 of the present embodiment includes an oxynitride film 22 instead of the nitride film 12. is there. Other configurations, that is, the semiconductor substrate 1, the source region 2, the drain region 4, the channel forming region 1a, the tunnel insulating film 10, the top insulating film 14, the gate electrode 8, the dielectric film 16, and the pull-up electrode 18
This is the same as the embodiment. The oxynitride film 22 is, for example, 5.
It has a thickness of 0 nm.

In the manufacture of the memory transistor having such a structure, after the tunnel insulating film 10 is formed, the oxynitride film 22 is formed.
Is deposited thicker by, for example, a low pressure CVD method so that the final film thickness becomes 5.0 nm. This CVD is
For example, the process is performed at a substrate temperature of 650 ° C. using an introduction gas in which dichlorosilane (DCS), ammonia and N ₂ O are mixed. An oxynitride film (SiOx Ny film;
In the formation of 0 <x <1, 0 <y <1), the pre-processing (wafer pre-processing) of the base surface and the film forming conditions may be optimized in advance, as necessary, as in the first embodiment. . After that, similarly to the first embodiment, the MONOS type memory transistor is completed through the formation and processing of each film to be the top insulating film 14, the gate electrode 8, the dielectric film 16, and the pull-up electrode 18. Also in the case of the present embodiment, similar to the third embodiment, good characteristics were obtained as a one-transistor cell. Further, similar to the first to third embodiments, the effect of pulling up the potential of the gate electrode was obtained.

Fifth Embodiment This embodiment is a nonvolatile semiconductor device using a large number of mutually insulated Si nanocrystals embedded in a gate insulating film and having a particle size of, for example, 10 nanometers or less, as charge storage means of a memory transistor. The present invention relates to a storage device (hereinafter, referred to as a Si nanocrystal type).

FIG. 10 is a sectional view showing the element structure of this Si nanocrystal type memory transistor. The Si nanocrystal nonvolatile memory of the present embodiment is different from the first embodiment in that the gate insulating film 30 of the present embodiment is different from the first embodiment in that the tunnel insulating film 10 is replaced with the nitride film 12 and the top insulating film 14.
That is, the Si nanocrystal 32 as the upper charge storage means and the oxide film 34 thereon are formed between the Si nanocrystal 32 and the gate electrode 8. Other configurations, that is, the semiconductor substrate 1, the channel formation region 1a, the source region 2, the drain region 4, the tunnel insulating film 10, the gate electrode 8, the dielectric film 16, and the pull-up electrode 18 are the same as those in the first embodiment.

The size (diameter) of the Si nanocrystal 32 is
However, it is preferably 10 nm or less, for example, about 4.0 nm, and individual Si nanocrystals are spatially separated by the oxide film 34 at an interval of, for example, about 4 nm. The tunnel insulating film 10 in this example is slightly thicker than in the first embodiment because of the fact that the charge storage means (Si nanocrystal 32) is closer to the substrate side, and from 2.6 nm to 4.
It can be appropriately selected within a range up to 0 nm. Here, 3.
The thickness was about 2 nm.

In the manufacture of the memory transistor having such a configuration, a plurality of Si nanocrystals 42 are formed on the tunnel oxide film 10 by, for example, a plasma CVD method after the formation of the tunnel insulating film 10. Further, the oxide film 44 is formed by, for example, reducing
To form a film. In this low pressure CVD, the source gas is DC
The mixed gas of S and N ₂ O and the substrate temperature are, for example, 700 ° C. At this time, the Si nanocrystals 32 are embedded in the oxide film 34, and the surface of the oxide film 34 is flattened. If the planarization is insufficient, a new planarization process (eg, CMP) may be performed. Thereafter, the Si nanocrystal type memory transistor is completed by forming and processing each film to be the gate electrode 8, the dielectric film 16, and the pull-up electrode 18.

The thus formed Si nanocrystal 32
Function as carrier traps discretized in the plane direction. The trap level can be estimated by a band discontinuity with the surrounding silicon oxide, and the estimated value is about 3.
It is about 1 eV. Individual Si nanocrystals 32 of this size can hold several injected electrons. Note that the Si nanocrystal 32 may be made smaller to hold a single electron.

With respect to the Si nanocrystal type nonvolatile memory having such a configuration, data retention characteristics were examined by a Landkist back tunneling model. In order to improve the data retention characteristics, it is important to increase the trap level and increase the distance between the charge center of gravity and the semiconductor substrate 1. Therefore, the simulation using the Landkist model as a physical model yields a trap level of 3.1e.
Data retention in the case of V was studied. As a result, it was found that by using a deep carrier trap having a trap level of 3.1 eV, good data retention was exhibited even when the distance from the charge retaining medium to the channel formation region 1a was relatively short at 3.2 nm. The results were as follows.

Next, low voltage programming was examined. The write time in this example is 1 msec or less at a low program voltage of 3 V, and the word line boosting effect of the pull-up electrode works effectively.
High-speed writing of the Si nanocrystal type was demonstrated.

Sixth Embodiment This embodiment relates to a nonvolatile semiconductor memory device (hereinafter referred to as a fine divided FG type) using a large number of finely divided floating gates embedded in an insulating film and separated from each other as charge storage means of a memory transistor. About).

FIG. 11 is a sectional view showing the element structure of this finely divided FG type memory transistor. The finely divided FG type nonvolatile memory of the present embodiment is different from the first embodiment in that the memory transistor is formed on the SOI substrate and the gate insulating film 40 of the present embodiment is formed of a nitride film 12 A finely divided floating gate 42 as a charge storage means on the tunnel insulating film 10 and an oxide film 44 thereon are formed between the gate electrode 8 instead of the gate insulating film 10 and the top insulating film 14. is there. Among other configurations, the tunnel insulating film 10, the gate electrode 8, the dielectric film 16
And the pull-up electrode 18 is the same as in the first embodiment. The finely divided floating gate 42, together with the Si nanocrystal 32 of the fifth embodiment, corresponds to a specific example of the “small grain size conductor” in the present invention.

As the SOI substrate, SIMOX (Separation by Impl) in which oxygen ions are implanted into a silicon substrate at a high concentration and a buried oxide film is formed at a position deeper than the substrate surface.
An anted oxygen substrate or a bonded substrate in which an oxide film is formed on the surface of one silicon substrate and bonded to another substrate are used. The SOI substrate formed by such a method and shown in FIG. 11 includes a semiconductor substrate 46, an isolation oxide film 48, and a silicon layer 50. In the silicon layer 50, a channel formation region 50a, a source region 2, and a drain region are provided. 4 are provided.

The finely divided floating gate 42 is formed by processing a normal FG type floating gate into fine poly-Si dots having a height of, for example, about 5.0 nm and a diameter of, for example, 8 nm. The tunnel insulating film 10 in this example is slightly thicker than in the first embodiment, but is formed much thinner than a normal FG type, and is appropriately selected from a range of 2.5 nm to 4.0 nm according to the intended use. it can. Here, the thinnest film thickness is 2.5 nm.

In manufacturing a memory transistor having such a configuration, after a tunnel insulating film 10 is formed on an SOI substrate, a polysilicon film (final thickness: 5 nm) is formed on the tunnel insulating film 10 by, for example, a plasma CVD method. ) Is formed.
In this plasma CVD, the source gas is a mixed gas of DCS and ammonia, and the substrate temperature is, for example, 650 ° C. Next, the polysilicon film is processed into fine poly-Si dots having a diameter of, for example, up to 8 nm by using, for example, an electron beam exposure method. This poly-Si dot functions as a finely divided floating gate 42 (charge storage means). Thereafter, an oxide film 44 is formed by, for example, about 9 nm by low pressure CVD while burying the finely divided floating gate 42. In this low pressure CVD, the source gas is DCS
And a mixed gas of N ₂ O and a substrate temperature of, for example, 700 ° C. At this time, the finely divided floating gate 42 is embedded in the oxide film 44, and the surface of the oxide film 44 is flattened. If the planarization is insufficient, a new planarization process (eg, CMP) may be performed. After that, the finely divided FG type memory transistor is completed by forming and processing the respective films to be the gate electrode 8, the dielectric film 16, and the pull-up electrode 18.

As to the fact that the floating gate is finely divided using the SOI substrate in this way, as a result of evaluating the characteristics of a prototype device, it was confirmed that the expected good characteristics could be obtained.

Modifications In the first to sixth embodiments described above, various modifications are possible.

The pull-up lines PL1, PL2,... In the first to third embodiments are connected to the pull-up gate bias circuit 1 via selection transistors having different pull-up lines.
02 and the pull-up gate bias circuit 102
May be individually controlled by pull-up lines PL1, PL2,.

Further, the cell pattern is not limited to FIG. 2, and the element structure is not limited to FIG. 3 and FIGS. For example, the pull-up electrode 18 only needs to be close to the gate electrode 8 with the dielectric film 16 interposed therebetween.
It does not have to be the same pattern as. In order to increase the capacitance coupling ratio between the two electrodes 8, 18, it is preferable that the pull-up electrode 18 covers the upper surface and the side surface of the gate electrode 8. The pull-up electrode 18 may be formed in a plate shape for each area in units of a predetermined number of blocks without being separated.
Further, the source region 2 and the drain region 4 may not be formed by introducing impurities, but may have a configuration in which an inversion layer is induced in accordance with a voltage applied to an electrode adjacent via an insulating film. In this case, the source line and the bit line are capacitively coupled to the source region 2 and the drain region 4.

In the description of the third embodiment, it is assumed that the write inhibit voltage supply circuit 122 simultaneously applies the same reverse bias voltage to both the source region 2 and the drain region 4 of the memory transistor. In the present invention, the reverse bias voltage is not limited to the same voltage, and a reverse bias voltage may be applied to one of the source region 2 and the drain region 4 and the other may be open. It is also possible to apply different voltages to the source line and the bit line.

As a fine cell structure in which bit lines or source lines are hierarchized, in addition to the so-called AND type configuration shown in FIG. 6, for example, a DINOR type, so-called HiCR type, and two adjacent source lines are connected. Fine NOR composed of isolated source type cell arrays shared by regions
The present invention can be applied to a mold cell. Also, the present invention can be applied to a so-called NAND type cell structure,
In this case, although not particularly shown, n memory transistors M1 connected in parallel in each unit block in FIG.
1 to M1n or M21 to M2n are connected in series between the selection transistors S11 and S12 or between the selection transistors S21 and S22.

The "planar discrete charge storage means" in the present invention includes a carrier trap of a bulk of a nitride film, a carrier trap formed near an interface between an oxide film and a nitride film, silicon or the like, and has a particle size of, for example, 10 nm. The following refers to a finely divided floating gate or the like made of nanocrystals, polysilicon, and the like which are insulated from each other and divided into fine dots. Therefore, in the embodiments other than the above embodiment, the present invention can be applied even if the gate insulating film is an MNOS type in which a NO (Nitride-Oxide) film is used.

The present invention can be applied not only to a stand-alone nonvolatile memory but also to an embedded nonvolatile memory integrated with a logic circuit on the same substrate. Note that the combination of the first to third embodiments and the fourth to sixth embodiments is arbitrary, and as in the sixth embodiment, S
The use of the OI substrate is applicable to the memory transistor structures of the first to fifth embodiments.

[0099]

According to the nonvolatile semiconductor memory device and the write method of the present invention, the voltage of the gate electrode (or word line) of the memory transistor pre-charged by the write voltage is changed to the voltage applied to the pull-up electrode. Can be boosted. Therefore, the writing voltage can be reduced without lowering the writing speed. In particular, when the write voltage is higher than the erase voltage and is asymmetric, the asymmetry between the write voltage and the erase voltage can be corrected, and the operating voltage can be reduced to 10 V or less. In addition, the program disturb margin for the non-selected memory transistor is increased, and as a result, it is easy to realize a one-transistor cell having a single memory cell transistor.

[Brief description of the drawings]

FIG. 1 shows a source separation NOR according to a first embodiment of the present invention.
FIG. 1 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory of a type.

FIG. 2 is a schematic plan view of a fine NOR type cell array using a self-alignment technique and a meandering source line as an example of a specific cell arrangement pattern.

FIG. 3 is a cross-sectional view showing an element structure of the MONOS type memory transistor according to the first embodiment.

FIG. 4 is a diagram showing setting conditions of write bias voltages for four types of cells defined in FIG.

FIG. 5 is a graph showing write / erase characteristics of a nonvolatile memory transistor.

FIG. 6 is a diagram illustrating a schematic configuration of a nonvolatile semiconductor memory according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory according to a third embodiment of the present invention.

FIG. 8 is a table showing various characteristics of the nonvolatile semiconductor memory.

FIG. 9 is a sectional view showing an element structure of a MONOS type memory transistor according to a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating an element structure of a Si nanocrystal memory transistor according to a fifth embodiment of the present invention.

FIG. 11 is a sectional view showing an element structure of a finely divided FG memory transistor according to a sixth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a, 50a ... Channel formation area, 2
... Source region, 4 ... Drain region, 6,20,30,4
0: gate insulating film, 8: gate electrode, 10: tunnel insulating film, 12: nitride film, 14: top insulating film, 16: dielectric film, 18: pull-up electrode, 22: oxynitride film, 32 ...
Si nanocrystal, 34, 44 oxide film, 42 fine division floating gate, 46 semiconductor substrate, 48 isolation oxide film, 50 silicon layer, 70 fine NOR type cell array, 71 element isolation region, 100, 110, 120 ...
Non-volatile semiconductor memory, 102 ... pull-up gate bias circuit (pull-up gate bias means), 122 ...
Write inhibit voltage supply circuit (write inhibit voltage supply means), 124... Non-selected word line bias circuits (non-selected word line bias means), M11 to M22
... Memory transistors, S11, ST0, etc. Selected transistors, A to C, unselected cells, S, selected cells, PL1, etc., pull-up lines, BL1, etc., bit lines, MBL1, etc., main bit lines, SBL, sub-bit lines , SL1, etc. source line,
MSL: Main source line, SSL: Sub source line, WL1, etc.
Word line, Vth: threshold voltage.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) ER14 ER21 GA01 GA03 GA05 GA09 HA02 JA02 JA04 JA32 JA35 KA03 KA12 LA09 LA10 LA12 LA16 LA20 MA02 MA19 MA20 PR03 PR13 PR16 PR21 PR29

Claims (40)

[Claims] A substrate, a semiconductor channel forming region provided on the substrate surface, a gate insulating film including a tunnel insulating film provided on the channel forming region, and a gate insulating film provided on the gate insulating film. A plurality of memory transistors each having a gate electrode and charge storage means provided in the gate insulating film and discretely planarized at least in a plane facing the channel formation region are arranged in a word direction and a bit direction. A non-volatile semiconductor memory device according to claim 1, further comprising a pull-up electrode adjacent to the gate electrode or a wiring layer connected to the gate electrode via a dielectric film. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a pull-up gate bias means for applying a predetermined voltage to said pull-up electrode. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said pull-up electrode is close to at least an upper surface of said gate electrode or a wiring layer connected to said gate electrode via said dielectric film. 4. A plurality of word lines each having a plurality of gate electrodes connected to said memory transistor, a selection transistor connected between said pull-up gate bias means and said pull-up electrode, and 3. The nonvolatile semiconductor memory device according to claim 2, wherein the means supplies a voltage in a direction in which the precharged word line is further boosted by capacitive coupling to the pull-up electrode via the selection transistor. 5. The memory transistor includes a source region in contact with the channel formation region, and a drain region separated from the source region and in contact with the channel formation region. A plurality of gate electrodes are connected, and the source region or the drain region is coupled to a common line in a bit direction that intersects with the word line while being electrically insulated from the word line, and the gate electrode is connected to a word line selected at the time of writing. A source region of the connected memory transistor and / or
Or write inhibit voltage supply means for supplying, via the common line, a reverse bias voltage in which the region becomes reverse biased with respect to the channel forming region, to the drain region; 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: non-selected word line bias means for supplying a voltage in a reverse bias direction. 6. The write inhibit voltage supply means supplies the reverse bias voltage to the source region and / or the drain region to erroneously write and / or write to the memory transistor connected to the selected word line.
6. The nonvolatile semiconductor memory device according to claim 5, wherein the bias is applied to a voltage that is not erased erroneously. 7. The non-selected word line bias means supplies a voltage in the reverse bias direction to the non-selected word line, thereby causing the memory transistor connected to the non-selected word line to be erroneously written and written. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the bias is applied to a voltage that is not erased erroneously. 8. The nonvolatile semiconductor memory device according to claim 5, wherein said unselected word line bias means biases said gate electrode with respect to said source region to an inhibit gate voltage or less. 9. A depletion layer extends from the source region and the drain region to the channel forming region when the reverse bias voltage is applied with the gate electrode of the memory transistor being at the same potential as the channel forming region. 6. The non-volatile semiconductor storage device according to claim 5, which is combined. 10. The gate length of the memory transistor is
6. The gate length when the reverse bias voltage is applied in a state where the gate electrode is set to the same potential as the channel formation region, and a depletion layer extends from the source region and the drain region to the channel formation region and is united. 3. The nonvolatile semiconductor memory device according to 1. 11. A source region in contact with the channel formation region, a drain region separated from the source region and in contact with the channel formation region, a source line commonly connecting the source regions in a bit direction, and the drain region. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: a bit line commonly connecting the gate electrodes in a bit direction; and a word line commonly connecting the gate electrodes in a word direction. 12. A source region in contact with the channel formation region, a drain region separated from the source region and in contact with the channel formation region, a sub-source line commonly connecting the source regions in a bit direction, A main source line commonly connecting the source lines in the bit direction; a sub-bit line commonly connecting the drain regions in the bit direction; a main bit line commonly connecting the sub-bit lines in the bit direction; 2. The semiconductor device according to claim 1, further comprising: a selection transistor connected between the source line and the main source line, between the sub-bit line and the main bit line, and a word line commonly connecting the gate electrodes in a word direction. 3. Non-volatile semiconductor storage device. 13. The memory device according to claim 1, wherein the plurality of memory transistors are connected in series between a first selection transistor connected to a bit line and a second selection transistor connected to a common potential line. Non-volatile semiconductor storage device. 14. A source region in contact with the channel formation region, a drain region separated from the source region and in contact with the channel formation region, a plurality of element isolation regions for insulating and separating the memory transistors from each other; Or a common line that commonly connects the drain regions in the bit direction, and a word line that connects a plurality of the gate electrodes in the word direction, wherein the plurality of element isolation regions are formed in a bit direction line separated from each other, The common line intersects with the word line in an electrically insulated state, is connected to one of the source region and the drain region, and avoids the other region. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is wired so as to be detoured above. 15. The plurality of element isolation regions are formed in a parallel stripe shape having substantially the same region width and separation width as the word lines, and are formed on sidewalls of the word lines on the source region and the drain region, respectively. A self-aligned contact hole is opened by the formed sidewall insulating layer, and a common line wired around the element isolation region connects the one region in common via the self-aligned contact hole. 15. The nonvolatile semiconductor memory device according to claim 14, wherein the wiring is meandering in the bit direction while being wired. 16. The charge accumulating means does not have conductivity as a whole surface facing the channel forming region when there is no transfer of electric charge at least to the outside.
3. The nonvolatile semiconductor memory device according to 1. 17. The nonvolatile semiconductor memory device according to claim 16, wherein said gate insulating film includes a tunnel insulating film on said channel formation region, and a nitride film or an oxynitride film on said tunnel insulating film. 18. The semiconductor device according to claim 16, wherein the gate insulating film includes a tunnel insulating film on the channel forming region, and small-diameter conductors formed on the tunnel insulating film and insulated from each other as the charge storage means. 14. The nonvolatile semiconductor memory device according to claim 1. 19. The nonvolatile semiconductor memory device according to claim 18, wherein said small-diameter conductor has a particle size of 10 nanometers or less. 20. A substrate, a channel forming region of a semiconductor provided on the surface of the substrate, a gate insulating film including a tunnel insulating film provided on the channel forming region, and provided on the gate insulating film. A plurality of memory transistors each having a gate electrode and charge storage means provided in the gate insulating film and discretely planarized at least in a plane facing the channel formation region are arranged in a word direction and a bit direction. A writing method for a nonvolatile semiconductor memory device, comprising applying a predetermined voltage to a pull-up electrode adjacent to the gate electrode or a wiring layer connected to the gate electrode via a dielectric film to increase a potential of the gate electrode. A writing method for a nonvolatile semiconductor memory device including steps. 21. The writing method for a nonvolatile semiconductor memory device according to claim 20, further comprising a step of applying a program voltage of 10 V or less to a gate electrode of said selected memory transistor. 22. The nonvolatile semiconductor memory according to claim 20, wherein the pull-up electrode applies the predetermined voltage from at least an upper surface of the gate electrode or a wiring layer connected to the gate electrode via the dielectric film. Device writing method. 23. A source transistor and / or a drain transistor of a memory transistor having a gate electrode connected to a word line selected at the time of writing among a plurality of word lines commonly connecting the gate electrode in a word direction. A reverse bias voltage which is reversely biased with respect to the channel forming region is applied to the channel forming region via a common line in the bit direction which intersects with the source region or the drain region while electrically intersecting with the line. 21. The method according to claim 20, wherein a voltage is applied to a non-selected word line in a direction in which a reverse bias is applied to the channel forming region. 24. The memory transistor connected to the selected word line is biased to a voltage that is not erroneously written and / or erased by applying the reverse bias voltage to the source region and / or the drain region. 24. The writing method of the nonvolatile semiconductor memory device according to 23. 25. By applying a voltage in the reverse bias direction to the unselected word line, the memory transistor connected to the unselected word line is biased to a voltage that does not cause erroneous writing and / or erasing. Claim 2
4. The writing method of the nonvolatile semiconductor memory device according to item 3. 26. The writing method for a nonvolatile semiconductor memory device according to claim 23, wherein the gate electrode is biased to be equal to or lower than an inhibit gate voltage with respect to the source region by applying a voltage to the unselected word line. 27. The writing method according to claim 23, wherein the same voltage is applied to both the source region and the drain region when the reverse bias voltage is applied. 28. The nonvolatile semiconductor memory device, comprising: a source region in contact with the channel formation region; a drain region separated from the source region and in contact with the channel formation region; and the source region commonly connected in a bit direction. 21. The writing method of the nonvolatile semiconductor memory device according to claim 20, comprising: a source line to be connected; a bit line that commonly connects the drain regions in a bit direction; and a word line that commonly connects the gate electrodes in a word direction. . 29. The nonvolatile semiconductor memory device, comprising: a source region in contact with the channel formation region; a drain region separated from the source region and in contact with the channel formation region; and the source region commonly connected in a bit direction. A sub-source line, a main source line commonly connecting the sub-source lines in the bit direction, a sub-bit line commonly connecting the drain regions in the bit direction, and a common connection in the bit direction. A main bit line, a selection transistor connected between the sub source line and the main source line, a sub transistor between the sub bit line and the main bit line, and a word line commonly connecting the gate electrode in a word direction. 21. The writing method for a nonvolatile semiconductor memory device according to claim 20, comprising: 30. The memory device according to claim 20, wherein the plurality of memory transistors are connected in series between a first selection transistor connected to a bit line and a second selection transistor connected to a common potential line. A writing method for a nonvolatile semiconductor memory device. 31. The reverse bias voltage may include a source line commonly connecting the source regions in a bit direction, and / or
The voltage applied in the direction of the reverse bias is applied through a bit line that commonly connects the drain regions in the bit direction, and the voltage in the direction of the reverse bias is applied through a word line that commonly connects the gate electrodes in the word direction. 24. The writing method of the nonvolatile semiconductor memory device according to 23. 32. The memory transistor has a source region in contact with the channel formation region, and a drain region in contact with the channel formation region in a manner separated from the source region, and is formed on the substrate surface so as to be separated from each other. A plurality of element isolation regions that insulate and isolate the memory transistors from each other are formed in a bit line, and intersect with a word line that connects a plurality of gate electrodes of the memory transistors in a word direction while being electrically insulated; A common line that connects the source region or the drain region in the bit direction is connected to one of the source region and the drain region, and is formed on the element isolation region so as to avoid the other region. 21. The writing method for a nonvolatile semiconductor memory device according to claim 20, wherein the wiring is bypassed. 33. The plurality of element isolation regions form a parallel stripe shape having substantially the same region width and separation width as the word lines, and are formed on sidewalls of the word lines on the source region and the drain region, respectively. A self-aligned contact hole is opened by the formed sidewall insulating layer, and a common line wired around the element isolation region is meandering in the bit direction while commonly connecting the one region. 33. The writing method for a nonvolatile semiconductor memory device according to claim 32, wherein the writing is performed. 34. The charge accumulating means does not have conductivity as a whole surface facing the channel forming region when at least no electric charge moves to / from the outside.
0. The writing method of the nonvolatile semiconductor memory device according to 0. 35. The nonvolatile semiconductor memory device according to claim 34, wherein said gate insulating film includes a tunnel insulating film on said channel formation region, and a nitride film or an oxynitride film on said tunnel insulating film. Method. 36. The gate insulating film according to claim 34, wherein the gate insulating film includes a tunnel insulating film on the channel forming region, and small-diameter conductors formed on the tunnel insulating film and insulated from each other as the charge storage means. The writing method of the nonvolatile semiconductor memory device described in the above. 37. The writing method for a nonvolatile semiconductor memory device according to claim 36, wherein a particle diameter of said small-diameter conductor is 10 nanometers or less. 38. The writing method according to claim 21, wherein a program voltage is applied to said gate electrode, and a predetermined voltage is applied to said pull-up electrode of said selected memory transistor. 39. A voltage in the reverse bias direction is applied to the unselected word line, and the source region and / or the drain region of a memory transistor connected to the selected word line are connected to the unselected word line via the common line. 24. The writing method of the nonvolatile semiconductor memory device according to claim 23, wherein a reverse bias voltage is applied, a program voltage is applied to the selected word line, and a predetermined voltage is applied to the pull-up electrode. 40. A selection transistor is connected to each of the word line and the pull-up electrode, and when a program voltage is applied to the selected word line, the selection transistor on the pull-up electrode side is controlled to be non-conductive, 40. The method according to claim 39, wherein the selection transistor of the selected word line is controlled to be non-conductive when a predetermined voltage is applied to the pull-up electrode.