JP2001024075A - Nonvolatile semiconductor memory and writing thereof' - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory transistor having a charge storage means such as FG, MONOS, etc., which can be suitably scaled to a gate length of 0.13 μm or less. SOLUTION: The memory includes a source region 2, a drain region 4, a gate insulating film 6 provided on a channel formation region 1a and having a charge storage means (charge trap) therein, and a gate electrode 8 provided thereon. An impurity concentration profile of the channel formation region 1a, source region 2 and/or drain region 4 is set to be varied to gradually increase a junction breakdown voltage of the source region 2 and/or drain region 4 from an impurity concentration profile optimum for suppressing a threshold reduction caused when a gate length is shortened to a predetermined rate (e.g. 10% or less). For example, when the profile is set so that the threshold is reduced by 15% or more, a short channel effect can be inhibited. As a result, even when the channel impurity concentration is relatively high, a write inhibit voltage can be applied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a charge storage means (for example, a floating gate of FG type, a nitride film of MONOS type or MNOS type) inside a gate insulating film between a channel forming region of a memory transistor and a gate electrode. Charge trap in the vicinity, a charge trap near the interface between the top insulating film and the nitride film, or a small-diameter conductor, etc.), and charge (electrons or holes) is charged to the charge storage means.
And a writing method therefor.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory, an FG in which charge storage means (floating gate) for holding charges is continuous in a plane is used.
In addition to the (Floating Gate) type, the charge accumulation means (charge trap) is discretized in a plane, for example, MONOS (Met
al-Oxide-Nitride-Oxide Semiconductor) type.

In an FG type non-volatile memory transistor, a floating gate made of polysilicon or the like is stacked on a semiconductor channel formation region via a gate insulating film, and an ONO (Oxide-Nitride-) is formed on the floating gate. Oxide) A control gate is laminated via an inter-gate insulating film such as a film.

On the other hand, in a MONOS type nonvolatile memory transistor, a tunnel insulating film made of, for example, a silicon oxide film or a nitrided oxide film, or an intermediate insulating film made of a nitride film or a nitrided oxide film is formed on a semiconductor channel formation region. A top oxide film made of a silicon oxide film is sequentially stacked, and a gate electrode is formed on the top insulating film.

In a MONOS type nonvolatile semiconductor memory,
The nitride film [Six Ny (0
<X <1, 0 <y <1)] because carrier traps in the film or at the interface between the top oxide film and the nitride film are spatially discrete (that is, in the plane direction and the film thickness direction) and spread. In addition to the tunnel insulating film thickness,
It depends on the energy and spatial distribution of the charge trapped by the carrier trap in the xNy film.

When a leak current path is locally generated in the tunnel insulating film, a large amount of charge leaks through the leak path in the FG type and the charge retention characteristic is apt to be deteriorated. Are spatially discretized, local charges around the leak path only leak locally through the leak path, and the charge retention characteristics of the entire memory element are unlikely to deteriorate. For this reason, MON
In the OS type, the problem of deterioration of the charge retention characteristics due to the thinning of the tunnel insulating film is not as serious as in the FG type. Therefore, the scaling property of the tunnel oxide film in the very small memory transistor having a very short gate length is expressed by MONO.
The S type is superior to the FG type.

[0007] For the above-mentioned nonvolatile memory, such as the FG type nonvolatile memory or the MONOS type, in which the charge storage means of the memory transistor is discretely planarized, cost reduction per bit and high integration are achieved to achieve a large-scale nonvolatile memory. In order to realize a nonvolatile memory, it is essential to realize a one-transistor type cell structure. But especially MON
In a non-volatile memory such as an OS type, a two-transistor type in which a selection transistor is connected to a memory transistor is mainstream, and various studies are currently being conducted for establishing a one-transistor cell technology.

In order to establish one-transistor cell technology,
In addition to optimizing the device structure centering on the gate insulating film including the charge storage means and improving the reliability, it is necessary to improve the disturb characteristics. As one measure for improving the disturb characteristics of the MONOS nonvolatile memory,
The tunnel insulating film has a normal thickness (1.6 nm to 2.0 n).
m) Studies are under way to set the thickness to be thicker.

In a one-transistor cell, since there is no select transistor in the cell, it is important how to reduce the disturbance of the memory transistor in an unselected cell connected to the same common line as the cell to be written. is there. Therefore, a technique has already been proposed in which a write inhibit voltage is applied to a source impurity region and a drain impurity region of an unselected memory transistor via a bit line or a source line, thereby preventing erroneous writing and erroneous erasing of the unselected memory transistor. Have been.

[0010]

However, mainly from the viewpoint of suppression of the short channel effect, the formation position of the junction surface of the source / drain impurity region becomes gradually shallower with scaling of the element size, and the source / drain impurity region becomes smaller. In addition, since the impurity concentration of the channel formation region needs to be increased, the impurity concentration profile becomes close to a step junction and has a junction with an abrupt concentration gradient (abrupt junction). In this steep junction, the junction with a gentle concentration gradient (g
raded junction), the junction withstand voltage is lower.
As a result, when the impurity concentration of the channel formation region is increased in order to shorten the gate length of the nonvolatile memory transistor, the write inhibit voltage applied to the non-selected cells in order to prevent program disturb during the memory cell operation is reduced. The junction withstand voltage of the source and the drain becomes low, so that an inhibit voltage at the time of writing cannot be applied to the source / drain impurity region.

An object of the present invention is to provide a memory transistor which basically operates by accumulating charges in a floating gate of an FG type or a carrier trap which is discretized in a plane in a MONOS type or the like which has excellent scaling properties of a tunnel insulating film. Is to provide a nonvolatile semiconductor memory device having a structure suitable for a case where the gate length becomes extremely short. Another object of the present invention is to provide a writing method for a nonvolatile semiconductor memory device including a suitable bias setting method for the transistor structure.

[0012]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a source region and a drain region formed on a surface portion of a semiconductor with a channel forming region interposed therebetween;
A non-volatile semiconductor storage device including a memory transistor provided on a channel formation region and including a gate insulating film including a charge storage means therein and a gate electrode on the gate insulating film, wherein the channel formation region, The impurity concentration profile of the source region and / or the drain region is determined based on the optimum impurity concentration profile that suppresses a decrease in the threshold value of the memory transistor that occurs when the gate length is reduced to a predetermined ratio. It has been changed to increase the junction breakdown voltage of the drain region.

Preferably, a plurality of the memory transistors are provided,
Bits that are arranged in a word direction and a bit direction, a plurality of gate electrodes of the memory transistor are connected to each of a plurality of word lines, and the source region or the drain region intersects with the word lines in an electrically insulated state. A source line and / or a drain region of the memory transistor in which a gate electrode is connected to a word line selected at the time of writing; Further, there is provided write inhibit voltage supply means for applying a write inhibit voltage lower than the junction withstand voltage via the common line.

Preferably, the impurity concentration profile of the memory transistor is set so that the threshold value is 15% or more lower than the threshold value of a memory transistor having a sufficiently long gate length. Preferably, an impurity peak concentration in the channel formation region of the memory transistor is higher than 4 × 10 ¹⁷ cm ⁻³ . This concentration is equivalent to, for example, about 9 to 10 V in terms of junction withstand voltage.
Greater than the write inhibit voltage value of the type. further,
Preferably, the gate length of the memory transistor is 0.1
3 μm or less. If the scaling of the impurity concentration profile is continued as it is in the conventional case, in the MONOS type, the magnitude relationship between the junction breakdown voltage and the write inhibit voltage (about 5 V) is reversed around the gate length of 0.13 μm. On the other hand, F
In the G type, the write inhibit voltage is about 8V and MON
Since the gate voltage is higher than that of the OS type, the magnitude relationship between the write inhibit voltage and the junction withstand voltage is already reversed near the gate length of 0.18 μm.

The present invention is suitable for a non-volatile memory device of a source line isolation NOR type and a NOR type in which source lines and bit lines are hierarchized. Further, with respect to the memory transistor structure, the present invention can be applied to the FG type.
Particularly suitable for a non-volatile memory device such as an ONOS type or a fine particle type having a small-diameter conductor such as a nanocrystal, in which the charge storage means is discretized in a plane at least in a plane opposed to the channel formation region. is there. This is because a nonvolatile memory transistor in which these charge storage means are discretized in a plane has excellent scaling properties of the tunnel insulating film as compared with the FG type. In this case, the charge accumulating means does not have conductivity on the entire surface facing the channel forming region when at least there is no transfer of electric charge between itself and the outside.

In the nonvolatile semiconductor memory device having such a configuration, the short channel effect (especially,
From the viewpoint of roll-off), when the thickness of the source / drain impurity region is reduced and the concentration is increased, and the junction breakdown voltage is lower than the write inhibit voltage at a gate length of 0.13 μm or less, the junction breakdown voltage is increased. This is addressed by changing the impurity concentration profile. The reason for introducing a new viewpoint regarding the setting of the impurity profile is that the decrease in the threshold value of the memory transistor can be dealt with to some extent by changing the setting of the read gate voltage, and the erase state is checked while checking the threshold value. This is because it can be corrected by the erase verify to be adjusted. That is, the present invention focuses on the fact that in a nonvolatile semiconductor memory device, a decrease in the threshold value of a transistor does not have as serious an effect as a logic device.

A writing method for a nonvolatile semiconductor memory device according to the present invention includes a source region and a drain region formed on a surface portion of a semiconductor with a channel formation region interposed therebetween, and a charge storage provided on the channel formation region and internally. A memory device comprising a gate insulating film including means and a gate electrode on the gate insulating film, wherein the impurity concentration profile of the channel forming region, the source region and / or the drain region is generated when the gate length is reduced. A writing method of a nonvolatile semiconductor memory device having a memory transistor having a direction in which the junction withstand voltage of the source region and / or the drain region is increased from an optimum impurity concentration profile for suppressing a decrease in the threshold value of the transistor to a predetermined ratio. In writing, the source region or the drain region is It becomes reverse biased with respect Yaneru formation region, and a low write inhibit voltage than the junction breakdown voltage, and applies the source region, at least one of the drain region.

In the writing method of the nonvolatile semiconductor memory device according to the present invention having such a configuration, at the time of writing, the write inhibit voltage for reversely biasing the pn junction with the channel formation region is applied to at least one of the source region and the drift region. Apply. This reverse bias application is made possible for the first time in a region with a gate length of 0.13 μm or less because the junction withstand voltage of the source / drain impurity region is reduced. This makes it difficult for non-selected cells to be disturbed via the collinear line (source line, bit line or word line) when writing to the selected cell.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a diagram showing a schematic configuration of a source-separated NOR type nonvolatile semiconductor memory according to an embodiment of the present invention.

In the nonvolatile memory device 90 of this embodiment, NO
Each memory cell of the R-type memory cell array is composed of one memory transistor. As shown in FIG. 1, memory transistors M11 to M22 are arranged in a matrix, and these transistors are wired by word lines, bit lines, and separated source lines. That is, each drain of the memory transistors M11 and M12 adjacent in the bit direction is connected to the bit line BL1, and each source is connected to the source line SL1. Similarly, each drain of the memory transistors M21 and M22 adjacent in the bit direction is connected to the bit line BL2, and each source is connected to the source line SL2. The gates of the memory transistors M11 and M21 adjacent in the word direction are connected to the word line WL1, and similarly, the gates of the memory transistors M12 and M22 adjacent in the word direction are connected to the word line WL2. In the entire memory cell array,
Such cell arrangement and inter-cell connection are repeated.

FIG. 2 is a schematic plan view of a fine NOR type cell array using a self-alignment technique as an example of a specific cell arrangement pattern. FIG. 3 is a perspective view seen from a cross-sectional side along the line AA ′ in FIG.

In this fine NOR type cell array 100,
As shown in FIG. 3, an element isolation insulating layer 102 is formed on a surface of a p-type semiconductor substrate 101 (a p-well is also possible) from a trench, LOCOS, or the like. Element isolation insulating layer 1
02 are arranged in parallel stripes long in the bit direction (vertical direction in FIG. 2) as shown in FIG. Each of the word lines WL1, W
L2, WL3, WL4,... Are wired at equal intervals.
As will be described later, this word line is formed by stacking a gate insulating film including a tunnel insulating film, a nitride film, and a top insulating film, and a gate electrode. In the present embodiment, the gate length (word line width) is reduced to 0.13 μm or less, for example, 0.1 μm.

In the active region within the interval between the element isolation insulating layers 102, for example, an n-type impurity is introduced at a high concentration in the space between the word lines, and the source region S and the drain region D are alternately formed. I have. The size of the source region S and the drain region D is defined only by the interval between the element isolation insulating layers 102 such as trenches or LOCOS in the word direction (horizontal direction in FIG. 2), and only by the word line interval in the bit direction. Is defined by Therefore, the source region S and the drain region D are formed very uniformly since almost no mask alignment error is introduced with respect to variations in size and arrangement.

The upper part and the side wall of the word line are covered with an insulating layer. That is, the offset insulating layers are arranged in the same pattern above the word lines WL1, WL2,.
Sidewall insulating layers are formed on both side walls of a laminated pattern including an offset insulating layer, a gate electrode (word line) thereunder, and a gate insulating film. By the offset insulating layer and the sidewall insulating layer, an elongated self-aligned contact is opened along the word line in a space between the word lines.

A conductive material is alternately embedded in the self-aligned contact so as to partially overlap the source region S or the drain region D, thereby forming a bit contact plug BC and a source contact plug SC. In forming the bit contact plug BC and the source contact plug SC, a conductive material is deposited so as to fill the entire area of the self-aligned contact, and a resist pattern for an etching mask is formed thereon. At this time, the resist pattern is slightly larger than the width of the self-aligned contact, and a part thereof is overlapped with the element isolation insulating layer. Then, using the resist pattern as a mask, the conductive material around the resist pattern is removed by etching. Thereby, the bit contact plug BC
And source contact plug SC are simultaneously formed.

The recess around the contact is filled with an insulating film (not shown). The bit lines BL1, BL2, BL2, BL2, BL2,
And the source lines SL contacting the source contact plugs SC are formed alternately in a parallel stripe shape.

In this fine NOR type cell array 100, the contact formation with respect to the bit line or the source line
This is achieved by forming self-aligned contacts and plugs. By the formation of the self-aligned contact, the insulation from the word line is achieved, and the exposed surface of the source region S or the drain region D is formed uniformly. Then, formation of the bit contact plug BC and the source contact plug SC is performed on the exposed surface of the source region S or the drain region D in the self-aligned contact contact. Therefore, the size of the plug contact surface of each plug in the bit direction is substantially determined by the formation of the self-aligned contact, and the contact area varies accordingly.

It is easy to insulate and separate the bit contact plug BC or the source contact plug SC from the word line. That is, an offset insulating layer is formed at once when forming a word line, and thereafter, a sidewall insulating layer is formed only by forming an insulating film and etching the entire surface (etchback). In addition, since the bit contact plug BC and the source contact plug SC, and furthermore, the bit line and the source line are formed by patterning the same layer of conductive layer, the wiring structure is extremely simple, the number of steps is small, The structure is advantageous to keep manufacturing costs low. In addition, since there is almost no wasted space, the formation of each layer requires the minimum line width F of the wafer process limit.
Can be manufactured with a very small cell area close to 8F ² .

FIG. 4 is a sectional view showing the element structure of the MONOS type memory transistor according to this embodiment.

In FIG. 4, reference numeral 1 denotes a semiconductor substrate or well such as a silicon wafer having n-type or p-type conductivity,
1a indicates a channel forming region, and 2 and 4 indicate a source region and a drain region of the memory transistor. In the present invention, the “channel forming region” refers to a region where a channel through which electrons or holes conduct is formed inside the surface side. The “channel formation region” in this example corresponds to a portion sandwiched between the source region 2 and the drain region 4 in the semiconductor substrate or the well 1. The source region 2 and the drain region 4
This is a region having a high conductivity formed by introducing an impurity of a conductivity type opposite to that of the channel forming region 1a into the semiconductor substrate 1 at a high concentration, and has various modes. Usually source area 2
In addition, a low-concentration region called an LDD (Lightly Doped Drain) is often provided at a substrate surface position of the drain region 4 facing the channel formation region 1a.

On the channel forming region 1a, a gate electrode 8 of a memory transistor is stacked via a gate insulating film 6. The gate electrode 8 is generally made of polysilicon (doped poly-Si) doped with p-type or n-type impurities at a high concentration and made conductive, or a laminated film of doped poly-Si and refractory metal silicide. . The length (gate length) of the gate electrode 8 in the channel direction is 0.13 μm or less,
For example, it is about 0.1 μm.

The gate insulating film 6 in this embodiment is composed of a tunnel insulating film 10, a nitride film 12, and a top insulating film 14 in order from the lower layer. Tunnel insulating film 10
Is silicon oxide (SiO ₂ ) formed by thermal oxidation
In this example, a short-time thermal oxidation method (RTO method) may be used.
An oxide film is formed by thermal nitridation (RT
N treatment). The thickness of the tunnel insulating film 10 can be determined within a range of 2.0 nm to 3.5 nm according to the intended use.
It is set to 7 nm.

The nitride film 12 is made of, for example, a 5.0 nm silicon nitride (Six Ny (0 <x <1, 0 <y <1)) film. This nitride film 12 is, for example,
It is manufactured by VD (LP-CVD) and contains many carrier traps in the film. The nitride film 12 exhibits a pool Frenkel type (PF type) electric conductivity.

The top insulating film 14 needs to form deep carrier traps in the vicinity of the interface with the nitride film 12 at high density. For this reason, the top insulating film 14 is formed, for example, by thermally oxidizing the formed nitride film. When the top insulating film 14 is formed by CVD, this trap is formed by heat treatment. The thickness of the top insulating film 14 must be at least 3.0 nm, preferably at least 3.5 nm, in order to effectively prevent holes from being injected from the gate electrode 8 and to prevent the number of times data can be rewritten. It is.

In designing a miniaturized memory transistor, usually, the minimum channel length L is calculated using the Brews equation shown in the following equation (1) as an empirical equation for suppressing a short channel effect in a CMOS logic device or the like.
min is determined.

[0036]

Lmin = 0.4 × [rj × d × (Ws + Wd) ² ] ^1/3 (1)

Here, rj is the junction depth of the source / drain impurity region, d is the thickness of the gate insulating film in terms of a silicon oxide film, Ws is the length of the depletion layer extending from the source end,
Wd indicates the length of the depletion layer extending from the drain end. The Brews equation is defined to include the short channel effect to some extent, and the degree of the decrease (roll-off) of the threshold is within 10% of the threshold in the long channel. The specification of the roll-off within 10% is used for a normal logic transistor or a DRAM memory transistor in order to suppress the variation of the threshold value.

According to this equation, the minimum channel length is 0.13
μm (corresponding to a gate length of about 0.18 to 0.23 μm), the channel impurity concentration is 1 × 10 ¹⁸ c
In the case where m ⁻³ and the equivalent oxide thickness of the gate insulating film are 9.5 nm, LDD is required to effectively suppress the short channel effect.
It is understood that it is necessary to set the junction depth to 50 nm or less. On the other hand, it was also found that when the LDD junction depth was further reduced, the junction breakdown voltage was reduced. In the one-transistor type MONOS memory cell, application of a so-called write inhibit voltage for reversely biasing a pn junction to a source / drain region of a non-selected cell at the time of writing as described later is essential for normal operation. Therefore, a further decrease in the source-drain junction breakdown voltage makes it difficult to realize a one-transistor type MONOS memory cell with a fine gate length of 0.13 μm or less. In other words, the design specification of a normal CMOS logic device that suppresses the roll-off within 10% is 0.13 μm.
1-transistor type MO having a fine gate length of less than m
It has been found that it is difficult to apply the method to the NOS memory cell as it is.

Therefore, in the present invention, the roll-off of the threshold value is intentionally allowed to be 10% or more, whereby the design margin of the impurity concentration profile of the channel formation region and the source / drain region is enlarged, and as a result, the source Improving the drain junction breakdown voltage is proposed as a new design guideline when miniaturizing the gate length to 0.13 μm or less. As a result, a write disturb voltage can be applied, and the MONOS memory transistor can be further miniaturized.

More specifically, in the memory transistor (FIG. 4) according to the present embodiment, although not shown, the impurity concentration profile of the channel formation region is defined by employing a retrograde well whose impurity concentration peak is deeper than the surface. Its peak impurity concentration is 5 to 20 × 10 ¹⁷ cm ^−3.
Within this range, the junction depth of the LDD is set to 100 nm or less. The converted value of the oxide film thickness of the gate insulating film 6 is 10 nm.
In the following cases, the roll-off of the threshold is allowed to be 15% or more (in some cases, 50% or more is possible). With such a concentration profile design, a MONOS memory transistor having a gate length of about 0.1 μm is realized.

In manufacturing a memory transistor having such a configuration, first, an element isolation region, a well, an ion implantation for adjusting a threshold voltage, and the like are performed on the prepared semiconductor substrate 1 as necessary. At the time of forming the well, an impurity concentration profile design for increasing a junction breakdown voltage with a source / drain region to be formed later is performed as needed based on the above design guideline. Next,
On the active region of the semiconductor substrate 1, a laminated film of the gate insulating film 6, the gate electrode 8, and the offset insulating layer (not shown) is laminated by the above-mentioned materials, film thicknesses and respective film forming methods, and this laminated film is collectively formed. And process in the same pattern. When the thickness of the tunnel insulating film 10 of the gate insulating film 6 (ONO film: tunnel insulating film / nitride film / top insulating film) is increased to, for example, about 3 nm, a typical value of the ONO film thickness specification is 3 0.0 nm / 5.0 nm / 3.5 nm. In this case, the converted value of the silicon oxide film thickness of the ONO film is 9 nm. Source / drain regions 2 and 4 are formed in self-alignment with the formed laminated pattern. At this time, an impurity concentration profile design for increasing the junction withstand voltage is performed based on the above design guidelines. Subsequently, a self-aligned contact is formed by forming a sidewall insulating layer, and a bit contact plug BC and a source contact plug SC are formed on the source / drain regions 2 and 4 exposed by the self-aligned contact. After burying these plugs with an interlayer insulating film, forming bit lines and source lines on the interlayer insulating film, forming an upper layer wiring through an interlayer insulating layer, performing an overcoat film formation, and a pad opening step as required. After that, the nonvolatile memory transistor is completed.

In the present embodiment, as a means for further improving the disturb characteristic, as shown in FIG. 1, the source region 2 and / or the drain region 4 ( 4) a write inhibit voltage supply circuit 92 for applying a reverse bias voltage, and a non-selected word line voltage connected to a word line and applying a reverse bias voltage to the gate electrode 8 of a non-selected cell with respect to the channel forming region 1a. And a supply circuit 94.

Here, the "common line" refers to a line in which a source region or a drain region is directly connected in common between a plurality of memory transistors in a bit direction (in a column direction) or capacitively coupled. A so-called booster plate or the like corresponds to the source line. FIG. 1 shows a case where the common line is a bit line and a source line. The “reverse bias voltage” refers to a voltage in a direction in which a pn junction formed between a source region or a drain region and a semiconductor substrate or a bulk region of a semiconductor layer in which a channel formation region is formed is reversely biased. . Further, “a direction in which a reverse bias is applied to the channel formation region” refers to a direction in which the voltage application based on the potential of the channel formation region is on the plus side or the minus side. Specifically, the conductivity type of the channel formation region is p
The direction in the case of the mold is on the plus side, and the direction in the case of the n-type is on the minus side.

The write inhibit voltage supply circuit 92 and the unselected word line voltage supply circuit 94 apply a predetermined voltage to the gate electrode 8, the source region 2, and the drain region 4 of the unselected memory transistor prior to the programming of the selected cell. This prevents erroneous writing or erasing of the non-selected cells A and B in FIG. 1 in particular, and significantly improves the program disturb margin.

Next, the write operation of the nonvolatile memory having such a configuration will be described.

Here, as shown in FIG. 1, non-selected cells A to C are defined according to the connection relationship with the selected cell S. That is, the non-selected cell connected to the same selected word line WL1 as the selected cell S is A, and the cell connected to the non-selected word line WL2 is connected to the same selected source line SL1 and selected bit line BL1 as the selected cell S. The selected unselected cells are connected to C, the unselected cells connected to the selected word line WL2, and the unselected cells connected to the unselected source line SL2 and the unselected bit line BL2 are set to B.
Is defined.

FIG. 5 shows an example of setting conditions of the write bias voltage for these four types of cells. When writing data to the selected cell S, first, the non-selected word line bias circuit 9
4, the selected word line WL1 and the unselected word line W
When the substrate potential is 0 V at L2, a predetermined voltage, for example, 4.5
V is applied. When the substrate potential is 0 V, a predetermined reverse bias voltage, for example, 5 V is applied to the unselected source line SL2 and the unselected bit line BL2 by the write inhibit voltage supply circuit 92. At this time, the selected source line S
L1 and the selected bit line BL1 are held at the ground potential of 0V. In this state, the word line W connected to the selected cell S is
The applied voltage of L1 is increased from a predetermined voltage (4.5 V) to a program voltage (for example, 12 V).

FIG. 6A shows an MO having a gate length of 0.1 μm.
4 shows a hysteresis characteristic of a NOS type nonvolatile memory transistor. FIG. 6B shows typical write / erase characteristics. As shown in FIG. 6A, a good hysteresis voltage difference (hysteresis window) of the memory was obtained. In addition, as a condition for obtaining a sufficient threshold window width, the writing time is set to the word line applied voltage 1
0.7 msec at 2V, 1m at word line applied voltage of 11V
sec, and the erasing time was 80 msec by applying a voltage of -8V.

In this writing method, the unselected word line W
By applying, for example, a positive voltage to L2, the disturb margin of the unselected cell B is expanded, and the unselected cell B is not erroneously written or erased. Further, by applying a reverse bias voltage to the non-selected bit line BL2 and the non-selected source line SL2, it is possible to prevent the non-selected cell A from being in a write state due to the application of the program voltage of the selected word line WL1. Cell B is not erroneously written (and erroneously erased). As for the order of applying the bias voltage at this time, it is preferable that the application of the voltage to the non-selected word line, the application of the reverse bias voltage, and the application of the program voltage as described above are less likely to cause the non-selected cell B to be disturbed.

Although the above description has been directed to the prevention of disturbance, it has been examined that the withstand voltage (junction withstand voltage) of the source and the drain expanded in the present invention is at a level that does not cause a problem when reverse biasing is performed. It is necessary to confirm the long dependence and the main device characteristics.

[Withstand Voltage of Memory Transistor] The current-voltage characteristics of the memory transistor in the erased state were examined under the condition of a gate voltage of 4 V, using the channel impurity concentration as a parameter. The result is shown in the graph of FIG. Here, the junction breakdown voltage is defined by a drain current of 1 nA / μm.
From the graph, the junction breakdown voltage depends on the channel impurity concentration,
There was a tendency that the higher the channel impurity concentration, the lower the junction breakdown voltage. Channel impurity dose of 15 × 10 ¹² c
In the case of m ^-2 , the highest peak concentration is shown, and the value is 7 to
It becomes 8 × 10 ¹⁷ cm ⁻³ . At this time, a junction withstand voltage of 7 V was obtained.

[Gate Length Dependence of Inhibit Voltage] FIG. 8 shows the gate length dependence of the lower limit value of the source / drain inhibit voltage. Write voltage Vpp is 1
The lower limit value of the inhibit voltage under the condition up to 2 V was about 5 V, and showed almost no dependence on the gate length. However, the write voltage Vpp slightly depends on the write voltage Vpp.
When pp is 10 V, the lower limit of the inhibit voltage is 4 to 4.3.
It has dropped to about V.

The gate voltage dependence of the current-voltage characteristic in the erased state was examined. The breakdown voltage did not show the gate voltage dependency, and the rise voltage in the sub-breakdown region showed the gate voltage dependency. The sub-breakdown region is presumed to be caused by the band-to-band tunneling phenomenon on the surface of the drain / source region at the gate edge portion. However, since the current level is small, it is considered that this is not a problem here.

As described above, the junction withstand voltage of about 7 V is equal to the source voltage.
Although the lower limit of the drain applied voltage (inhibit S / D voltage) is about 5 V, there is a sufficient margin, and it has been confirmed that the inhibit voltage can be applied to the source region and / or the drain region. . Also,
As can be seen from FIG. 7, when the write voltage Vpp is 10 V, the lower limit of the inhibit voltage drops to about 4 V. Therefore, even if the peak impurity concentration of the channel formation region is 2 × 10 ¹⁸ cm ⁻³ and the junction breakdown voltage is 5 V, the memory transistor Turned out to work without problems.

[Main Device Characteristics] Current in Erase State
The voltage characteristics of the read current and the leak current obtained by examining the voltage characteristics are shown in the graph of FIG. When the gate voltage was 0 V, the leakage current value of the unselected cells at a drain voltage of 1.2 V was about 3 nA. The read current in this case is 30
Since the current is equal to or more than μA, it is considered that erroneous reading of the non-selected cell does not occur. Therefore, a gate length of 0.1
It has been found that the margin of the punch-through breakdown voltage at the time of reading is sufficient in the MONOS type memory transistor of μm.

The read disturb characteristics after 100,000 data rewrites were also evaluated, and the results are shown in FIG. The threshold window width after 10 years after data rewriting 100,000 times was 0.5 V or more, which was a level that can be sufficiently detected by the sense amplifier. Therefore, it was found that a read time of 10 years or more was possible.

Write conditions (program voltage: 12 V,
The data rewriting characteristics were examined under the programming time: 0.7 msec) and the erasing condition (erasing gate voltage: -8 V, erasing time: 80 msec), and the results are shown in FIG. It was found that the number of times of data rewriting was satisfactory because the carrier traps were spatially discretized, and satisfied 1 × 10 ⁵ times. Although data is not shown here, 1 ×
It was also confirmed that 10 ⁶ times of data rewrite is also possible. The data retention characteristics satisfy 85 ° C. and 10 years after data rewriting 1 × 10 ⁵ times.

As described above, the MONOS in which the gate length is scaled to 0.1 μm is improved by changing the impurity concentration profiles of the channel formation region, the source region and the drain region from the optimum values for the short channel effect and improving the junction breakdown voltage. It was confirmed that a non-volatile memory transistor was realized and sufficient characteristics were obtained. In addition, the actual cell operation could be verified.

In the non-volatile memory device, since there is usually a sequence for aligning the threshold values of the memory transistors in the erased state by erase verify, it is easy to compensate for the decrease in the threshold value of each memory transistor. Can be. Therefore, the relaxation of the roll-off specification of the threshold value in the nonvolatile memory does not cause a problem as much as the logic device.

Second Embodiment This embodiment is a case where the gate length is scaled to 85 nm in the same device structure as in FIG.

FIG. 12 shows a MONOS having a gate length of 85 nm.
1 shows the current-voltage characteristics of a type memory transistor. From the figure, it can be seen that the junction withstand voltage is 7 V, and there is a sufficient margin with respect to the source / drain inhibit voltage 5 V.

FIG. 13 shows a read current from a selected cell and a leak current from an unselected cell. Since the gate length is further scaled from 100 nm of the first embodiment to 85 nm, when the drain voltage is scaled to 1.1 V accordingly, an increase in leak current due to punch-through current was expected. However, in practice, the impurity concentration of the channel formation region could be increased to a peak concentration of 8 × 10 ¹⁷ cm ⁻³ , so that the ratio between the read current and the leak current was slightly higher than that in the case where the gate length was 0.1 μm. Although it is decreasing, it has more than three digits.

FIG. 14 shows the read current characteristics of the memory cell in the erased state. 1.1V read drain voltage
The read current was 33.5 μA / μm at a read gate voltage of 1.5 V and 59.7 μA / μm at a read gate voltage of 2 V.

FIG. 15 shows data rewriting characteristics of a MONOS memory transistor having a gate length of 85 nm. It has been found that the threshold window width up to 100,000 times is sufficiently large that data can be rewritten up to 100,000 times. Although no particular data is shown, it was confirmed that the data could be rewritten up to 1 million times.

FIG. 16 shows the read disturb characteristics after 10,000 data rewrites. The window width of the threshold value extrapolated from the measured value is 0.5 V or more after 10 years, which indicates that continuous reading for 10 years is possible.

As described above, by increasing the impurity concentration of the channel formation region to a peak concentration of 8 × 10 ¹⁷ cm ^-3 , the gate length is further reduced to less than 0.1 μm.
It was confirmed that a 5 nm MONOS nonvolatile memory was feasible.

The third and fourth embodiments show modifications of the element structure of the nonvolatile memory.

Third Embodiment This embodiment is a non-volatile semiconductor using a large number of mutually insulated Si nanocrystals embedded in a gate insulating film and having a grain size of, for example, 10 nanometers or less, as charge storage means of a memory transistor. The present invention relates to a storage device (hereinafter, referred to as a Si nanocrystal type).

FIG. 17 is a sectional view showing an element structure of the Si nanocrystal type memory transistor. The Si nanocrystal nonvolatile memory of the present embodiment is different from the first embodiment in that the gate insulating film 30 of the present embodiment is different from the first embodiment in that the tunnel insulating film 10 is replaced with the nitride film 12 and the top insulating film 14.
That is, the Si nanocrystal 32 as the upper charge storage means and the oxide film 34 thereon are formed between the Si nanocrystal 32 and the gate electrode 8. Other configurations, that is, the semiconductor substrate 1, the channel formation region 1a, the source region 2, the drain region 4, the tunnel insulating film 10, the gate electrode 8, the dielectric film 16, and the pull-up electrode 18 are the same as those in the first embodiment.

The size (diameter) of the Si nanocrystal 32 is
However, it is preferably 10 nm or less, for example, about 4.0 nm, and individual Si nanocrystals are spatially separated by the oxide film 34 at an interval of, for example, about 4 nm. The tunnel insulating film 10 in this example is slightly thicker than the first embodiment because of the fact that the charge storage means (Si nanocrystals 32) is closer to the substrate side, and ranges from 2.6 nm to 5.
It can be appropriately selected within a range up to 0 nm. Here, 4.
The thickness was about 0 nm.

In the manufacture of the memory transistor having such a configuration, after the formation of the tunnel insulating film 10, a plurality of Si nanocrystals 32 are formed on the tunnel oxide film 10 by, for example, a plasma CVD method. Further, the oxide film 34 is formed to a thickness of, for example, about 7 nm by LP-CV so as to bury the Si nanocrystal 32.
D is formed. In this LP-CVD, the source gas is a mixed gas of DCS and N ₂ O, and the substrate temperature is, for example, 700 ° C.
And At this time, the Si nanocrystals 32 are embedded in the oxide film 34, and the surface of the oxide film 34 is flattened. If planarization is insufficient, a new planarization process (eg, CMP, etc.)
It is good to do. Thereafter, a gate electrode 8 is formed, and a step of collectively patterning the gate laminated film is performed, thereby completing the Si nanocrystal type memory transistor.

The thus formed Si nanocrystal 32
Function as carrier traps discretized in the plane direction. The trap level can be estimated by a band discontinuity with the surrounding silicon oxide, and the estimated value is about 3.
It is about 1 eV. Individual Si nanocrystals 32 of this size can hold several injected electrons. Note that the Si nanocrystal 32 may be made smaller to hold a single electron.

With respect to the Si nanocrystal type nonvolatile memory having such a configuration, the data retention characteristics were examined using a Landkist back tunneling model. In order to improve the data retention characteristics, it is important to increase the trap level and increase the distance between the charge center of gravity and the semiconductor substrate 1. Therefore, the simulation using the Landkist model as a physical model yields a trap level of 3.1e.
Data retention in the case of V was studied. As a result, it was found that by using a deep carrier trap having a trap level of 3.1 eV, good data retention was exhibited even when the distance from the charge retention medium to the channel formation region 1a was relatively short, 4.0 nm. The results were as follows.

As in the first embodiment, the gate length is set to 0.1.
The operation of a one-transistor cell having a 1 μm fine memory transistor was confirmed. Next, low voltage programming was considered. The write time in this example was 1 msec or less at a low program voltage of 5 V, and the high-speed write performance of the Si nanocrystal type was demonstrated.

Fourth Embodiment This embodiment is directed to a nonvolatile semiconductor memory device (hereinafter referred to as a finely divided FG type) using a large number of finely divided floating gates embedded in an insulating film and separated from each other as charge storage means of a memory transistor. About).

FIG. 18 is a sectional view showing the element structure of this finely divided FG type memory transistor. The finely divided FG type nonvolatile memory of the present embodiment is different from the first embodiment in that the memory transistor is formed on the SOI substrate and the gate insulating film 40 of the present embodiment is formed of a nitride film 12 A finely divided floating gate 42 as a charge storage means on the tunnel insulating film 10 and an oxide film 44 thereon are formed between the gate electrode 8 instead of the gate insulating film 10 and the top insulating film 14. is there. Among other configurations, the tunnel insulating film 10 and the gate electrode 8 are the same as in the first embodiment. The finely divided floating gate 42, together with the Si nanocrystal 32 of the third embodiment, corresponds to a specific example of the “small grain size conductor” in the present invention.

As an SOI substrate, SIMOX (Separation by Impl) in which oxygen ions are implanted into a silicon substrate at a high concentration and a buried oxide film is formed at a position deeper than the substrate surface.
An anted oxygen substrate or a bonded substrate in which an oxide film is formed on the surface of one silicon substrate and bonded to another substrate are used. The SOI substrate formed by such a method and shown in FIG. 18 includes a semiconductor substrate 46, an isolation oxide film 48, and a silicon layer 50. In the silicon layer 50, a channel formation region 50a, a source region 2, and a drain region are provided. 4 are provided. Note that a glass substrate, a plastic substrate, a sapphire substrate, or the like may be used instead of the semiconductor substrate 46.

The finely divided floating gate 42 is formed by processing a normal FG type floating gate into fine poly-Si dots having a height of, for example, about 5.0 nm and a diameter of, for example, 8 nm. The tunnel insulating film 10 in this example is slightly thicker than in the first embodiment, but is formed much thinner than a normal FG type, and is appropriately selected from a range of 2.5 nm to 4.0 nm according to the intended use. it can. Here, the thinnest film thickness is 2.5 nm.

In the manufacture of a memory transistor having such a configuration, after a tunnel insulating film 10 is formed on an SOI substrate, a polysilicon film (final film thickness: 5 nm). In this LP-CVD, the source gas is a mixed gas of DCS and ammonia, and the substrate temperature is, for example, 650 ° C. Next,
For example, using an electron beam exposure method, the polysilicon film is processed into fine polysilicon dots having a diameter of, for example, up to 8 nm. This poly-Si dot functions as a finely divided floating gate 42 (charge storage means). afterwards,
An oxide film 44 is formed to a thickness of, for example, about 9 nm by LP-CVD while burying the finely divided floating gate 42. In this LP-CVD, the source gas is DCS
And a mixed gas of N ₂ O and a substrate temperature of, for example, 700 ° C. At this time, the finely divided floating gate 42 is embedded in the oxide film 44, and the surface of the oxide film 44 is flattened. If the planarization is insufficient, a new planarization process (eg, CMP) may be performed. Thereafter, the gate electrode 8 is formed, and the finely divided FG type memory transistor is completed through a step of collectively patterning the gate laminated film.

As to the fact that the floating gate is finely divided using the SOI substrate as described above, as a result of evaluating the characteristics of a prototype device, it was confirmed that the expected good characteristics could be obtained. Further, in the same manner as in the first embodiment, the operation of a one-transistor cell having a fine memory transistor with a gate length of 0.1 μm was confirmed.

[0081] In the first to fourth embodiments have been described above modification, and various modifications are possible.

First, as the cell structure, an isolated source NOR type in which bit lines and source lines are hierarchized can be adopted. FIG. 19 shows a circuit configuration of this NOR type memory cell array. FIG. 20 is a plan view showing a pattern example of the NOR type memory cell array, and FIG. 21 is a perspective view seen from a cross-sectional side along the line BB 'in FIG.

In this nonvolatile memory device 110, bit lines are hierarchized into main bit lines and sub-bit lines, and source lines are hierarchized into main source lines and sub-source lines. The sub-bit line SBL1 is connected to the main bit line MBL1 via the selection transistor S11, and the sub-bit line SBL2 is connected to the main bit line MBL2 via the selection transistor S21. Also, the main source line MSL (MS in FIG. 21)
L1 and MSL2), a sub-source line SSL1 is connected via a selection transistor S12, and a sub-source line SSL2 is connected via a selection transistor S22.

The memory transistors M11 to M1n are provided between the sub bit line SBL1 and the sub source line SSL1.
Are connected in parallel, the sub bit line SBL2 and the sub source line SS
The memory transistors M21 to M2n are connected in parallel with L2. The n memory transistors connected in parallel to each other and two select transistors (S1
1 and S12 or S21 and S22) constitute a unit block constituting the memory cell array.

The gates of the memory transistors M11, M21,... Adjacent in the word direction are connected to the word line WL1. Similarly, memory transistors M12, M2
, Are connected to the word line WL2.
Each gate of the memory transistors M1n, M2n,... Is connected to a word line WLn. Are controlled by a selection line SG1, and the selection transistors S12, S22,... Are controlled by a selection line SG2.

In this fine NOR type cell array 110,
As shown in FIG. 21, a p-well 112 is formed on a surface of a semiconductor substrate 111. The p-well 112 is formed by burying an insulator in a trench, and is insulated and separated in the word line direction by element isolation insulating layers 113 arranged in parallel stripes.

Each p-well portion separated by the element isolation insulating layer 112 becomes an active region of the memory transistor. On both sides in the width direction in the active region, n-type impurities are introduced at a high concentration in parallel stripes spaced apart from each other, thereby forming a sub-bit line SBL and a sub-source line SSL. Each word line WL is orthogonal to these sub-bit lines SBL and sub-source lines SSL via an insulating film.
1, WL2, WL3, WL4,... Are wired at equal intervals. As will be described later, this word line is formed by stacking a gate insulating film including a tunnel insulating film, a nitride film, and a top insulating film, and a gate electrode. In the present embodiment, the gate length (word line width) is reduced to 0.13 μm or less, for example, 0.1 μm. Sub-bit line SB
P well portion 112a between L and sub-source line SSL
Then, the intersection with each word line becomes the channel formation region of the memory transistor, the sub-bit line portion in contact with the channel formation region functions as the drain, and the sub-source line portion functions as the source.

As in the case of FIG. 3, the upper part and the side wall of the word line are covered with an offset insulating layer and a side wall insulating layer (in this example, a normal interlayer insulating layer is also possible). The sub-bit lines SBL are provided at predetermined intervals on these insulating layers.
, And a source contact plug SC reaching the sub-source line SSL. These plugs BC and SC are, for example,
There are provided about 128 memory transistors in the bit line direction. In addition, the main bit lines MBL1 and BL contacting the insulating layer with the bit contact plugs BC.
, And main source lines MSL1, BL2,... Contacting on the source contact plug SC are alternately formed in parallel stripes.

In this fine NOR type cell array 100, bit lines and source lines are hierarchized, and it is not necessary to form a bit contact plug BC and a source contact plug SC for each memory cell. Therefore, there is basically no variation in the contact resistance itself. Bit contact plug BC and source contact plug S
C is provided, for example, for every 128 memory cells. When this plug formation is not performed in a self-aligned manner,
No offset insulating layer and sidewall insulating layer are required. That is, only a process of embedding the memory transistor by thickly depositing a normal interlayer insulating film is sufficient. Thus, in this example, there is an advantage that the process can be further simplified.

The sub wiring (sub bit line, sub source line)
From there is almost no wasted space as a pseudo contactless structure constituted by the impurity region, when subjected to the application of each layer the minimum line width F of the wafer process limits can be produced by cell area very small close to 8F ^2. Further, the bit lines and the source lines are hierarchized, and the selection transistors S11
Alternatively, since S21 separates the parallel main transistor group in the unselected unit block from the main bit line MBL1 or MBL2, the capacity of the main bit line is significantly reduced,
This is advantageous for high speed and low power consumption. Further, by the operation of the selection transistor S12 or S22, the sub-source line can be separated from the main source line, and the capacitance can be reduced. In order to further increase the speed, the sub-bit lines SBL1 and SBL1
BL2 or the sub-source lines SSL1 and SSL2 are formed of impurity regions to which silicide is attached, and the main bit lines MBL
1 and MBL2 may use metal wiring.

Further, a NAND cell system can also be adopted. In the NAND type, each of the memory transistors M11 to M11 in a unit block constituting the memory cell array of FIG.
1n or M21 to M1n are connected in series instead of in parallel. In this case, there is no distinction between the sub-bit line and the sub-source line, and it becomes the channel forming impurity region of the NAND string. Other DI (not shown)
The present invention can be applied to a NOR type cell, which is a so-called HiCR type and is composed of a separated source type cell array in which a source line is shared by two adjacent source regions.

In the description of the first embodiment, it is assumed that the write inhibit voltage supply circuit 92 simultaneously applies the same reverse bias voltage to both the source region 2 and the drain region 4 of the memory transistor. In the present invention, the reverse bias voltage is not limited to the same voltage, and a reverse bias voltage may be applied to one of the source region 2 and the drain region 4 and the other may be open. It is also possible to apply different voltages to the source line and the bit line.

The “planar discrete charge storage means” in the present invention includes a carrier trap formed in the bulk of the nitride film and a carrier trap formed near the interface between the oxide film and the nitride film. (Nitride-Oxid
e) The present invention is applicable to an MNOS type film.

The present invention can be applied not only to a stand-alone nonvolatile memory but also to an embedded nonvolatile memory integrated with a logic circuit on the same substrate. The use of the SOI substrate as in the fourth embodiment is applicable to the memory transistor structures of the first to third embodiments.

[0095]

According to the nonvolatile semiconductor memory device and the writing method of the present invention, the impurity concentration profiles of the channel formation region, the source region and the drain region of the memory transistor are changed from the optimum values for the short channel effect. By improving the junction breakdown voltage, it is possible to realize a nonvolatile memory transistor in which the gate length is scaled to 0.1 μm or less while applying a write inhibit voltage to prevent erroneous writing and erasing of unselected cells.

[Brief description of the drawings]

FIG. 1 shows a source separation NOR according to a first embodiment of the present invention.
FIG. 1 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory of a type.

FIG. 2 shows an example of a specific cell arrangement pattern according to the first embodiment of the present invention.
It is a schematic plan view of an R-type cell array.

FIG. 3 is a perspective view of the cell array of FIG. 2 according to the first embodiment of the present invention, as viewed from a cross-sectional side along line AA ′.

FIG. 4 is a sectional view showing an element structure of the MONOS type memory transistor according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of setting conditions of a write bias voltage for four types of cells in the first embodiment of the present invention.

FIG. 6 shows a first embodiment of the present invention.
5 is a graph showing hysteresis characteristics and write / erase characteristics of a 1 μm MONOS type nonvolatile memory transistor.

FIG. 7 is a graph showing current-voltage characteristics of a memory transistor in an erased state according to the first embodiment of the present invention.

FIG. 8 is a graph showing a gate length dependency of a lower limit value of a source / drain inhibit voltage in the first embodiment of the present invention.

FIG. 9 is a graph showing the voltage dependence of a read current and a leak current obtained from current-voltage characteristics in an erased state in the first embodiment of the present invention.

FIG. 10 is a graph showing read disturb characteristics after 100,000 times of data rewriting in the first embodiment of the present invention.

FIG. 11 is a graph showing data rewrite characteristics in the first embodiment of the present invention.

FIG. 12 shows a second embodiment of the present invention, in which the gate length is 8
5 is a graph showing current-voltage characteristics of a 5-nm MONOS memory transistor.

FIG. 13 is a graph showing voltage dependence of a read current and a leak current in a second embodiment of the present invention.

FIG. 14 is a graph showing read current characteristics of a memory cell in an erased state according to the second embodiment of the present invention.

FIG. 15 shows a gate length of 8 in the second embodiment of the present invention.
4 is a graph showing data rewriting characteristics of a 5 nm MONOS memory transistor.

FIG. 16 is a graph showing read disturb characteristics after 10,000 data rewrites in the second embodiment of the present invention.

FIG. 17 is a cross-sectional view illustrating an element structure of a Si nanocrystal memory transistor according to a third embodiment of the present invention.

FIG. 18 is a sectional view showing an element structure of a finely divided FG memory transistor according to a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a circuit configuration of a NOR type memory cell array as another application example of the memory cell system in the embodiment of the present invention.

20 is a plan view showing a pattern example of the NOR type memory cell array of FIG. 19;

21 is a perspective view seen from a cross-sectional side along the line BB ′ in FIG. 20;

[Explanation of symbols]

1, 101, 111: semiconductor substrate, 1a, 50a: channel forming region, 2, S: source region, 4, D: drain region, 6, 30, 40: gate insulating film, 8: gate electrode, 10: tunnel insulating Film, 12 nitride film, 14 top insulating film, 32 nanocrystal Si, 34, 44 oxide film,
42: finely divided floating gate, 46: semiconductor substrate, 48: isolation oxide film, 50: silicon layer, 90, 1
00, 110 ... fine NOR type memory cell array, 92 ...
Write inhibit voltage supply circuit (write inhibit voltage supply means), 94 ... non-selected word line bias circuit (non-selected word line bias means), 102, 113 ...
Element isolation insulating layer, 112 ... p well, M11 to M22 ...
Memory transistors, S11, ST0, etc .... Selection transistors, A to C: Unselected cells, S: Selected cells, BL1, etc.
Bit line, MBL1, etc .... Main bit line, SBL ... Sub bit line, SL1, etc .... Source line, MSL ... Main source line, SSL
1 etc .: sub-source line, WL1 etc ... word line, BC ... bit contact plug, SC ... source contact plug.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) H01L 27/115 F term (reference) 5B025 AA07 AC01 AE05 5F001 AA01 AA14 AA19 AA34 AA43 AB02 AD17 AD18 AD22 AD51 AD52 AE02 AE08 AF06 AG21 5F083 EP09 EP18 EP22 EP63 EP68 EP77 GA09 GA11 GA15 GA24 GA30 JA04 JA35 JA39 JA53 KA01 KA05 KA11 LA12 LA16 LA20 MA03 MA06 MA20 PR21 PR29

Claims (25)

[Claims] 1. A source region and a drain region formed on a surface portion of a semiconductor with a channel forming region interposed therebetween, a gate insulating film provided on the channel forming region and including charge storage means therein, and the gate insulating film A non-volatile semiconductor memory device having a memory transistor having an upper gate electrode, wherein the impurity concentration profile of the channel formation region, the source region and / or the drain region is generated when a gate length is reduced. A nonvolatile semiconductor memory device in which a junction withstand voltage of a source region and / or a drain region is increased from an optimum impurity concentration profile for suppressing a decrease in a threshold value of a memory transistor to a predetermined ratio. A plurality of memory transistors arranged in a word direction and a bit direction; a plurality of gate electrodes of the memory transistor connected to each of a plurality of word lines; and a source region or a drain region connected to the word line. A source region and / or a source region of the memory transistor having a gate electrode connected to a word line selected at the time of writing and coupled to a bit line common line that intersects while being electrically insulated.
2. The semiconductor device according to claim 1, further comprising: a write inhibit voltage supply unit configured to apply, via the common line, a write inhibit voltage, which is reverse biased to the channel formation region and lower than the junction withstand voltage, to the drain region. 14. The nonvolatile semiconductor memory device according to claim 1. 3. The non-volatile memory according to claim 1, wherein the impurity concentration profile of the memory transistor is set so that the threshold value is 15% or more lower than the threshold value of a memory transistor having a sufficiently long gate length. Semiconductor storage device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein an impurity peak concentration in a channel formation region of said memory transistor is higher than 4 × 10 ¹⁷ cm ⁻³ . 5. The gate length of said memory transistor is:
2. The nonvolatile semiconductor memory device according to claim 1, wherein the thickness is 0.13 [mu] m or less. 6. A source line for commonly connecting the source regions in the bit direction, a bit line for commonly connecting the drain regions in the bit direction, and a word line for commonly connecting the gate electrodes in the word direction. 2. The nonvolatile semiconductor memory device according to claim 1, comprising: 7. The source line includes a sub-source line commonly connecting the source regions in the bit direction, and a main source line commonly connecting the sub-source lines in the bit direction. 7. The nonvolatile semiconductor memory device according to claim 6, comprising: a sub-bit line commonly connecting said drain regions in the bit direction; and a main bit line commonly connecting said sub-bit lines in the bit direction. 8. The nonvolatile semiconductor memory device according to claim 1, wherein said charge storage means is discretized in a plane at least in a plane facing said channel formation region. 9. The non-volatile semiconductor device according to claim 1, wherein said charge storage means does not have conductivity as a whole surface facing said channel forming region when there is no transfer of electric charge at least to the outside. Storage device. 10. The nonvolatile semiconductor memory device according to claim 9, wherein said gate insulating film includes a tunnel insulating film on said channel formation region, and a nitride film or an oxynitride film on said tunnel insulating film. 11. The gate insulating film according to claim 9, wherein said gate insulating film includes a tunnel insulating film on said channel forming region, and small-diameter conductors formed on said tunnel insulating film and insulated from each other as said charge storage means. 10. The nonvolatile semiconductor memory device according to claim 1. 12. The nonvolatile semiconductor memory device according to claim 11, wherein said small-diameter conductor has a particle size of 10 nanometers or less. 13. A source region and a drain region formed on a surface portion of a semiconductor with a channel forming region interposed therebetween, a gate insulating film provided on the channel forming region and including charge storage means therein, and the gate insulating film. And an impurity concentration profile of the channel forming region, the source region and / or the drain region, which suppresses a decrease in the threshold value of the memory transistor, which occurs when the gate length is reduced, to a predetermined ratio. A writing method for a nonvolatile semiconductor memory device having a memory transistor in which a junction withstand voltage of the source region and / or the drain region is changed from an optimum impurity concentration profile in a direction to increase the junction withstand voltage. The region is reverse biased with respect to the channel forming region, and
A writing method for a nonvolatile semiconductor memory device, wherein a write inhibit voltage lower than the junction withstand voltage is applied to at least one of a source region and a drain region. 14. The nonvolatile semiconductor memory device according to claim 14,
A plurality of the memory transistors are arranged in a word direction and a bit direction, a plurality of gate electrodes of the memory transistor are connected to each of the plurality of word lines, and the source region or the drain region is electrically insulated from the word lines. 14. The writing method for a nonvolatile semiconductor memory device according to claim 13, wherein the write inhibit voltage is applied via the common line, wherein the write inhibit voltage is applied through the common line in the bit direction that intersects in a crossed state. 15. The write inhibit voltage is applied via a source line commonly connecting the source regions in the bit direction and / or a bit line commonly connecting the drain regions in the bit direction. 15. The writing method of the nonvolatile semiconductor memory device according to item 14. 16. The non-volatile memory according to claim 13, wherein the impurity concentration profile of the memory transistor is set so that the threshold value is at least 15% lower than the threshold value of a memory transistor having a sufficiently long gate length. A writing method of a semiconductor memory device. 17. The method according to claim 13, wherein an impurity peak concentration of a channel formation region of the memory transistor is higher than 4 × 10 ¹⁷ cm ⁻³ . 18. The gate length of the memory transistor is
14. The method according to claim 13, wherein the thickness is 0.13 [mu] m or less. 19. A source line for commonly connecting the source regions in the bit direction, a bit line for commonly connecting the drain regions in the bit direction, and a word line for commonly connecting the gate electrodes in the word direction. 14. The writing method of the nonvolatile semiconductor memory device according to claim 13, comprising: 20. The source line is composed of a sub-source line commonly connecting the source regions in the bit direction, and a main source line commonly connecting the sub-source lines in the bit direction. 20. The nonvolatile semiconductor memory device according to claim 19, further comprising: a sub-bit line commonly connecting the drain regions in the bit direction; and a main bit line commonly connecting the sub-bit lines in the bit direction. Writing method. 21. The method according to claim 13, wherein said charge storage means is discretely planarized at least in a plane facing said channel formation region. 22. The charge accumulating means does not have conductivity as a whole surface facing the channel forming region when there is no transfer of electric charge between at least the outside and the outside.
3. The writing method for the nonvolatile semiconductor memory device according to item 3. 23. The nonvolatile semiconductor memory device according to claim 22, wherein said gate insulating film includes a tunnel insulating film on said channel formation region, and a nitride film or an oxynitride film on said tunnel insulating film. Method. 24. The gate insulating film according to claim 22, wherein the gate insulating film includes a tunnel insulating film on the channel forming region, and small-diameter conductors formed on the tunnel insulating film and insulated from each other as the charge storage means. The writing method of the nonvolatile semiconductor memory device described in the above. 25. The writing method for a nonvolatile semiconductor memory device according to claim 24, wherein the small-diameter conductor has a particle size of 10 nanometers or less.