JP2004158614A - Nonvolatile semiconductor memory device and data writing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that the reduction of cell area of a NAND type memory cell array is insufficient. <P>SOLUTION: The nonvolatile semiconductor memory device includes a plurality of transistor columns respectively including the first and the second select transistors S1, S2 and a plurality of memory transistors M1 to Mn cascade connected between such transistors S1, S2, charge accumulating film consisting of a plurality of dielectric material films stacked on a semiconductor 2 within the transistor columns, a plurality of word lines WL1 to WLn formed on the charge accumulating film to electrically connect the memory transistors M1 to Mn in adjacent different transistor columns in the row direction, the first upper wirings BSL1a, BSL2a to supply a first voltage V1 to the memory transistor via the first select transistor S1, and a second upper wiring BSL2b to supply a second voltage V2 to the memory transistor via the second select transistor S2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a so-called NAND string (transistor array) and capable of electrically writing data to a selected memory transistor, and a data writing method thereof.
[0002]
[Prior art]
At present, many types of memory cell schemes have been proposed for a batch erasing nonvolatile semiconductor memory (flash memory) having a floating gate. Among them, a cell scheme having a small cell size and capable of increasing the capacity has been proposed. , NAND type are known.
A NAND flash memory has a memory block called a NAND string in which a plurality of memory transistors are cascaded between two select transistors. For example, by sharing one bit contact and one source line between two NAND strings adjacent in the column direction, an effective cell area per bit can be reduced. The source line is usually formed of an impurity diffusion layer that is long in the row direction, and is shared by a plurality of NAND strings in the row direction (for example, see Patent Document 1).
[0003]
In a general NAND flash memory, at the time of an erase operation, 0 V is applied to all word lines of a selected NAND string, and a high voltage (for example, 20 V) is applied to all word lines of a non-selected NAND string and a substrate.
As a result, only the memory transistor of the selected NAND string has electrons extracted from the floating gate to the substrate by FN tunneling, and the threshold voltage of the memory transistor shifts in the negative direction to, for example, about -3V.
[0004]
On the other hand, the data programming (writing) operation is performed in units of a so-called page for the memory transistors connected to the selected word line at a time, and a high voltage (for example, 18 V) is applied to the selected word line by the program (“1”). A voltage of 0 V is applied to a bit line to which a memory transistor to store (data) is connected, and an intermediate potential (for example, 9 V) is applied to a bit line to which a memory transistor to inhibit program (retain "0" data) is connected.
As a result, electrons are injected into the floating gate by FN tunneling only in the selected memory transistor to be programmed, and the threshold voltage of the selected memory transistor shifts in the positive direction to, for example, about 2V.
[0005]
In the NAND flash memory, contacts and impurity diffusion layer wirings are shared by a large number of memory cells such as 64, for example, and NAND strings, and the area occupied by these cells is small. Suitable for memory applications.
[0006]
[Patent Document 1]
Japanese Patent No. 2732601, page 5, right column, line 45 to line 49, FIG. 9 (a).
[0007]
[Problems to be solved by the invention]
In a NAND flash memory, both writing and erasing of data are performed by FN (Fowler Nordheim) tunnel current, and data that can be stored in one memory transistor is usually one binary data, that is, 1-bit data. In order to further increase the capacity, in addition to miniaturization of elements, a multi-value technology capable of storing a plurality of bits in one memory transistor is important.
However, in the multi-valued operation generally performed in the memory transistor having the FG structure, since the region into which the charge is injected is a conductor (a floating gate of polysilicon), local charge injection cannot be performed. Therefore, multi-valued storage of a plurality of bits is performed on a memory transistor having an FG structure by finely dividing a threshold voltage in a storage state. However, in this multilevel technology, control of peripheral circuits is complicated, and errors due to fluctuations in threshold voltage are likely to occur.
[0008]
A first object of the present invention is to provide a NAND-type nonvolatile semiconductor memory device having a wiring structure capable of multi-leveling by writing data by local charge injection.
A second object of the present invention is to provide a data writing method for a nonvolatile semiconductor memory device that can independently write two data in a memory transistor connected in a NAND type.
[0009]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention achieves the first object, and includes first and second select transistors whose on and off are independently controlled, and a cascade between the select transistors. A plurality of transistor rows each including a plurality of connected memory transistors, and a plurality of dielectric films stacked on a semiconductor in the transistor rows, and a charge is stored in the stacked dielectric films. And electrically connecting gates of the memory transistors in different transistor rows formed on the charge storage film and adjacent in a direction intersecting a direction of cascade connection of the plurality of memory transistors. And a first word line for supplying a first voltage to the memory transistor via the plurality of word lines and the first select transistor. Having an upper interconnection, and the second upper wiring for supplying the second voltage to the memory transistor via the second select transistor.
[0010]
A method of writing data in a nonvolatile semiconductor memory device according to the present invention achieves the second object described above, and includes first and second select transistors whose on and off are independently controlled, Applying a pass voltage for turning on the non-selected memory transistor to a gate of the non-selected memory transistor for a transistor row including a plurality of memory transistors connected in cascade between the transistors; Applying a write voltage to the gates of the first and second select transistors; supplying a first voltage to the transistor row from one side of the first and second select transistors in an on state; 2 from the other side of the select transistor. Supplying the pass voltage, the write voltage, the first voltage, and the second voltage to each other. The first data and the second data are independently written into the selected memory transistor by repeatedly switching the side to which the second voltage is applied.
[0011]
According to the data write method of the present invention, at the time of writing the first data, the pass voltage and the write voltage are respectively applied as described above, the first voltage is applied from one end of the transistor row, and the second voltage is applied. Is applied from the other side of the transistor row. The first and second voltages are transmitted to the unselected memory transistors in the ON state, respectively, and reach the source and drain of the selected memory transistor. At this time, by controlling the values of the first or second voltage transmitted to the source, the first or second voltage transmitted to the drain, and the write voltage applied to the gate, the local voltage from the drain side is controlled. Charge injection is possible. Electric charges locally injected from the drain side are locally injected in a dielectric laminated film (charge storage film) composed of a plurality of dielectric films and having extremely low conductivity in the direction of the plane and thickness of the film. It is held at a local position centered on the region that was set.
At the time of writing the second data, the first voltage and the second voltage applied from both ends of the transistor array are applied interchangeably with each other at the time of writing the first data. As a result, the source and drain of the memory transistor are switched, and charge is injected into the charge storage film from the side of the drain which was the source in the first data write. Since the conductivity is extremely low as described above, the charge injected at the time of writing the second data does not mix with the charge already injected and corresponding to the first data.
[0012]
In the nonvolatile semiconductor memory device according to the present invention, the charge storage film is a laminated film of a plurality of dielectric films, and a wiring for supplying the first voltage and the second voltage is divided, and each of the wirings is provided above the transistor. It is composed of wiring layers (first upper wiring, second upper wiring). For this reason, the wiring structure is suitable for applying the above-described data writing method which requires voltage replacement. Further, since these wirings are formed of an upper wiring layer, they have a lower resistivity than the impurity diffusion layer, and the first and second voltages are transmitted to the end of the transistor column without much lowering.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit diagram showing a basic configuration of a memory cell array of a nonvolatile semiconductor memory device (hereinafter, nonvolatile memory) according to the present embodiment.
In FIG. 1, NAND strings are repeatedly arranged as a basic configuration of the memory cell array 1. FIG. 1 shows three NAND strings.
Each NAND string includes a first select transistor S1 and a second select transistor S2, and n (for example, n = 64, 128) memory transistors M1 to Mn cascaded therebetween.
[0014]
The first select transistor S1 of another NAND string adjacent in the column (COLUMN) direction is connected to the first select transistor S1. A node between the two first select transistors is connected to an upper wiring layer (hereinafter, a first upper wiring) BSL1a, BSL2a, BSL3a,... Via a first contact C1.
Similarly, the second select transistor S2 of another NAND string adjacent in the column (COLUMN) direction is connected to the second select transistor S2. A node between the two second select transistors is connected to an upper wiring layer (hereinafter, a second upper wiring) BSL1b, BSL2b, BSL3b,... Via a second contact C2.
The first upper wires BSL1a, BSL2a, BSL3a,... And the second upper wires BSL1b, BSL2b, BSL3b,.
[0015]
In a plurality of NAND strings arranged in a row (ROW) direction, the first select transistor S1 is controlled by a first select gate line SG1, and the select transistor S2 is controlled by a second select gate line SG2.
In a plurality of NAND strings arranged in a row (ROW) direction, a plurality of memory transistors M1, M2, M3,..., Mn are controlled by word lines WL1, WL2, WL3,. .
[0016]
In the memory cell array shown in FIG. 1, a plurality of NAND strings are arranged in a matrix. Among them, the first contact C1 is shared between two NAND strings in the column direction, and the two NAND strings are connected to the first upper wirings BSL1a, BSL2a, BSL3a,... Via the first contact C1. Similarly, the second contact C2 is shared between two NAND strings in the column direction, and the two NAND strings are connected to the second upper wirings BSL1b, BSL2b, BSL3b,... Via the second contact C2. . These connection relations are repeated in other strings in the column direction.
[0017]
FIG. 2 is a plan view of the memory cell array mainly showing the NAND strings in the second column shown in FIG. FIG. 3 is a cross-sectional view of a portion indicated by line AA in FIG. FIG. 4 is a cross-sectional view of a portion indicated by line BB in FIG.
As shown in the cross-sectional view of FIG. 3, for example, a P-type well (P-well) 2 is formed on the surface side in an N-type semiconductor substrate 1, and a transistor row is arranged on the surface side of the P-well 2. ing. Further, as shown in the cross-sectional view of FIG. 4, the surface portion of the semiconductor substrate 1 is electrically separated by the element isolation insulating layer 10.
[0018]
Each of the memory transistors M1 to Mn has a charge storage film 3 formed by stacking a plurality of dielectric films on a P well 2. The word lines WL1 to WLn are stacked on the charge storage film 3. The word lines WL1 to WLn are generally made of doped polycrystalline silicon into which P-type or N-type impurities are introduced at a high concentration, or a laminated film of doped polycrystalline silicon and refractory metal silicide.
[0019]
Source / drain impurity regions 5 are formed by introducing N-type impurities into the surface portion of P well 2 below between word lines.
The source / drain impurity region 5 is a region having a high conductivity formed by introducing an impurity of the opposite conductivity type into the P well 2 at a high concentration, and has various modes. Although not shown in the figure, low-concentration impurity regions called extension regions may be provided at both ends in the column direction of the source / drain impurity regions 5.
[0020]
The first and second select transistors S1 and S2 are formed of normal MOSFETs. Therefore, the gate insulating film 4 is constituted by a single layer film made of, for example, silicon dioxide. The gate electrode layers of the first and second select transistors S1 and S2 form a first select gate line SG1 and a second select gate line SG2, respectively.
[0021]
On these select transistors and memory transistors, an interlayer insulating film 8 made of, for example, silicon dioxide is deposited thickly. The interlayer insulating film 8 is composed of a plurality of films.
A first shared region in which an N-type impurity is added at a high concentration is provided on a surface portion of P well 2 between first select gate line SG1 and first select gate line SG1 of another NAND string adjacent in the column direction. Impurity region 6 is formed. First contact C1 is formed on first shared impurity region 6. A second common gate in which an N-type impurity is added at a high concentration is provided on the surface of P well 2 between second select gate line SG2 and second select gate line SG2 of another NAND string adjacent in the column direction. Impurity region 7 is formed. Second contact C2 is formed on second shared impurity region 7.
The first and second contacts C1 and C2 are formed by filling a contact hole formed in the interlayer insulating film 8 with a metal plug such as W through an adhesion layer such as Ti / TiN. I have.
A first upper wiring BSL2a that is in contact with the first contact C1 is formed between the plurality of films of the interlayer insulating film 8. On the interlayer insulating film 8, a second upper wiring BSL2b that is in contact with the second contact C2 is formed. The second upper wiring BSL2b is formed above the first upper wiring BSL2a. The first and second upper wirings BSL2a and BSL2b can have a three-layer structure in which the upper and lower main wiring layers of, for example, Al are sandwiched between an antireflection layer (or a protection layer) and a barrier metal.
[0022]
As a nonvolatile memory transistor having electric charge storage means in this embodiment and capable of storing electrical data, a non-volatile memory transistor between a gate electrode (word line) and a semiconductor region (P well 2) in which a channel is formed. The MONOS type in which the electric charge accumulation film 3 is formed of an ONO (Oxide-Nitride-Oxide) film is used.
Here, the "charge storage means" means a charge storage medium that is formed in the charge storage film 3 and exchanges charges with the substrate side in accordance with a voltage applied to a gate electrode above the charge storage film 3 to hold the charges. Say. The charge storage means in the MONOS cell refers to a carrier trap of a nitride film bulk of an ONO film or a deep carrier trap formed near an interface between an oxide film and a nitride film.
[0023]
The charge storage film 3 in the present embodiment is composed of a first oxide film 31, a nitride film 32, and a second oxide film 33 in order from the lower layer.
The first oxide film 31 is made of, for example, silicon dioxide (SiO 2) formed by thermal oxidation. The thickness of the first oxide film 31 can be determined within the range of 2.5 nm to 6.0 nm according to the intended use, and is set to 3.5 nm here. Note that a thin nitrided oxide layer may be formed on at least the surface of the first oxide film 31 by thermal nitridation.
The nitride film 32 is made of, for example, 8.0 nm silicon nitride (Si _x N _y (0 <x <1, 0 <y <1)). The nitride film 32 is formed, for example, by low pressure CVD (LP-CVD).
The second oxide film 33 needs to form deep carrier traps at a high density near the interface with the nitride film 32. For this reason, the second oxide film 33 is formed by, for example, thermally oxidizing a nitride film or the like after film formation. Further, the second oxide film 33 is formed by an HTO (High Temperature chemical vapor deposited Oxide) method. ₂ It may be a film. When the second oxide film 33 is formed by CVD, this trap is formed by heat treatment. The thickness of the second oxide film 33 is at least 3.0 nm, preferably 3 nm, in order to effectively prevent holes from being injected from the gate electrode (word line) and to prevent a reduction in the number of times data can be rewritten. 0.5 nm or more is required.
[0024]
In the manufacture of this NAND string, first, after the element isolation insulating layer 10 and the P well 2 are formed in the prepared semiconductor substrate 1, ion implantation for adjusting the gate threshold voltage of the memory transistor is performed as necessary. Do it.
[0025]
Next, the charge storage film 3 is formed on the P well 2 by the following procedure, for example.
A heat treatment at 1000 ° C. for 10 seconds is performed by a short-time high-temperature heat treatment method (RTO method) to form a silicon dioxide film (first oxide film 31).
Next, a silicon nitride film (nitride film 32) is deposited on the first oxide film 31 by LP-CVD so as to have a final thickness of 8 nm. This CVD is performed at a substrate temperature of 650 ° C. using, for example, a gas obtained by mixing dichlorosilane (DCS) and ammonia.
The surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form, for example, a 3.5 nm-thick silicon oxide film (second oxide film 33). This thermal oxidation is, for example, H ₂ This is performed for about 40 minutes while maintaining the temperature in the furnace in an O atmosphere at 950 ° C. As a result, a deep carrier trap having a trap level (energy difference from the conduction band of the silicon nitride film) of about 2.0 eV or less can be formed in about 1-2 × 10 5 ^Thirteen / Cm ² Formed at a density of The thermal silicon oxide film (the second oxide film 33) is formed to 1.6 nm with respect to the silicon nitride film constituting the nitride film 32 at 1 nm. Has a final thickness of 8 nm.
[0026]
If necessary, the charge storage film 3 having a three-layer structure is removed from a portion other than the memory transistor row, and a silicon oxide film serving as the gate insulating film 4 of the select transistors S1 and S2 is formed by thermal oxidation to a thickness of several nm. In this case, in order to protect the charge storage film 3, it is desirable to form a film of a material that can be selectively removed later on the charge storage film 3. Note that since a high electric field is not applied to the select transistors S1 and S2 so that charge injection occurs, the gate insulating film 4 of the select transistor can have the same structure as the charge storage film 3. In this case, the step of removing the charge storage film 3 is unnecessary.
[0027]
A conductive film serving as a word line is stacked. Then, the conductive film and the charge storage film 3 (and the gate insulating film 4) thereunder are collectively patterned. Thereby, the word lines WL1, WL2, WL3,... WLn, the first select gate line SG1, and the second select gate line SG2 are formed simultaneously.
[0028]
In the state where the parallel stripe-shaped wirings long in the row direction are formed, N-type impurities are ion-implanted into the well surface between the wirings, and annealing is performed. As a result, source / drain impurity regions 5 are formed between the word lines and between the word lines and the gates of the select transistors. Further, the first shared impurity region 6 or the second shared impurity region 5 is provided between the gates of the select transistors. Region 7 is formed.
Through the above steps, for example, 128 to 256 NAND strings including 16 to 64 memory transistors are formed in the row direction. One rewrite unit (page) is constituted by the number of cells equal to the product of the number of cells connected to one word line and the number of word lines in the NAND string. Normally, one page is composed of, for example, 4K (= 256 × 16) cells.
[0029]
By embedding the memory transistor and the select transistor, the lower layer film of the interlayer insulating film 8 made of, for example, silicon dioxide is subjected to CVD, and an opening for the first contact C1 is formed in the interlayer insulating film 8. This opening is formed on the first shared impurity region 6. A plug material, for example, tungsten is deposited so as to completely fill the opening, and this is etched back on the entire surface to separate the plug material on the lower layer film of the interlayer insulating film 8. As a result, the first contact C1 composed of a plug connected to the first shared impurity region 6 is formed by being buried in the lower layer film of the interlayer insulating film 8. A first upper wiring BSL2a connected to the first contact C1 is formed.
Further, the upper layer film of the interlayer insulating film 8 is subjected to CVD. Thereafter, similarly, an opening for the second contact C2 is formed in the upper layer film and the lower layer film of the interlayer insulating film 8, and this is buried with a plug material. A second upper wiring BSL2b connected to the contact C2 is formed.
After that, if necessary, another interlayer insulating film and an upper layer wiring are formed, and finally, the non-volatile memory cell array is completed through an overcoat film formation and a pad opening step.
[0030]
In the memory cell array thus formed, the minimum width of the wiring width and distance between the first select gate line SG1, the word lines WL1 to WLn, and the second first select gate line SG2 (minimum process and design) If the rule is F, the pitch in the column direction is 2F.
The pitch of the first upper wirings BSL1a, BSL2a,... Is the sum of the first upper wiring width F0, the first contact diameter F1, and the minimum proximity distance F2 between the first upper wirings. Here, when all of F0 to F2 are defined as the minimum rule F of the process and the design, the pitch of the first upper wiring is 3F. In FIG. 2, the overlapping dimension of the first contact C1 and the first upper wiring BSL2a in the row direction is set to zero. However, assuming that a displacement occurs between the two, a reference numeral Cex in FIG. By previously expanding the first contact to the vicinity of the center of the width of the first upper wiring as shown by, a sufficient contact area between the first contact and the first upper wiring can be secured.
Since the pitch of the second upper wirings BSL1a, BSL2a,... Is limited to the pitch of the first upper wirings described above, they are the same 3F.
[0031]
Although not shown, the peripheral circuits of the memory cell array include a row decoder (including a word line driving circuit), a column decoder, a row and column buffer, a data latch circuit group for temporarily storing write data and read data, and a column selection circuit. , A read circuit (sense amplifier), a power supply circuit, a well bias circuit, and the like.
FIG. 1 shows a first voltage supply means 20 connected to the first upper wiring and the second upper wiring, a first select gate line and a second select gate line, and a word line. And the second voltage supply means 30 connected to the power supply.
The first voltage supply means 20 supplies the first voltage to the selected first upper wirings BSL1a, BSL2a, BSL3a,. Are supplied with the second voltage, and the voltage applied to the first upper wiring and the voltage supplied to the second upper wiring are switched as necessary.
The second voltage supply means 30 controls the first and second select gate lines SG1 and SG2, and applies a write voltage or a pass voltage to the word lines WL1, WL2, WL3,..., WLn.
[0032]
Hereinafter, the operation of the memory cell executed under the control of the first and second voltage supply means 20, 30 (and the well bias circuit) will be described. In the following description, the operation of the selected cell Ssel shown in FIG. 1 will be described, and prevention of malfunction of the unselected cell Cus1 in the same row as the selected cell and the unselected cell Cus2 in a row different from the selected cell will also be described.
[0033]
FIG. 5A is an enlarged cross-sectional view showing a part of the memory transistor M2, and FIG. 5B is an explanatory diagram of a write operation. FIGS. 6A to 6J are timing charts of the write operation.
During the data writing period, as shown in FIG. 6G, a second voltage V2, for example, a ground voltage of 0 V is applied to the second upper wiring BSL1b connected to the NAND string including the selected cell. 6 (H) and 6 (I), unselected first upper wirings BSL2a, BSL3a,... And unselected second upper wirings BSL2b, BSL3b,. Is also held at the ground voltage of 0V.
[0034]
In writing the first data, as shown in FIGS. 6A and 6E, for example, a voltage of 6 V to 8 V is applied to the first and second select gate lines SG1 and SG2, and the first data is written. And set the ON state of the second select transistors S1 and S2. At the same time, a pass voltage Vpass that is sufficiently lower than the write voltage Vw but turns on the memory transistor M1 and transmits the first voltage V1 is applied to the unselected word line WL1 within a range of, for example, 6 V to 8 V. . In addition, a pass voltage Vpass that is sufficiently lower than the write voltage Vw but turns on the memory transistors M3 to Mn and transmits the second voltage V2 (0 V) is applied to the other unselected word lines WL3 to WLn, for example. The voltage is applied within the range of 6V to 8V.
Next, as shown in FIG. 6C, a predetermined write voltage Vw of, for example, 6 V to 10 V is applied to the word line WL2 to which the selected cell Csel (memory transistor M2) is connected, preferably at a slightly delayed timing. Apply within the range. The write voltage Vw is higher than the threshold voltage of the memory transistor M2 and higher than the drain voltage (first voltage V1). Further, as shown in FIG. 6F, the first voltage V1 is applied to the first upper wiring BSL1a within a range of, for example, 4V to 6V, preferably at a slightly later timing.
[0035]
As a result, a channel is formed in the channel formation region CH of the memory transistor M2, and electrons are supplied into the channel from the source / drain impurity region 5 (source S) to which the second voltage (0 V) is applied. At this time, electrons in the channel are accelerated by an electric field between the source / drain impurity region 5 (drain D) to which the first voltage V1 is applied and the pinch-off point of the channel formation region CH. The accelerated electrons obtain high energy near the drain end and become hot carriers, are attracted to the vertical electric field, are injected into the region of the charge storage film 3 near the drain end, and are captured by the charge trap.
At this time, the voltage applied to the P well 2 may be the ground voltage 0V, but as shown in FIG. 6 (J), for example, a negative voltage of about -3V at the maximum may be applied.
[0036]
At the time of writing the data, in the unselected memory cell Cus1 connected to the word line WL2 and applied with the write voltage Vw to the gate, the source and the drain (and the P well) are held at 0V, so the write voltage Vw Is higher, electrons are injected from the entire surface of the channel by the Fowler-Nordheim (FN) tunnel mechanism. In this example, however, the write voltage Vw is sufficiently lower than the FG type write voltage, and such electron injection does not occur. . In the memory cells Cus2 in the other non-selected rows, the pass voltage Vpass is sufficiently low as described above, so that the injection of electrons is similarly effectively prevented.
The relationship between the threshold voltages of the select transistors S1 and S2 and the gate applied voltage is controlled to cut off the select transistors of the non-selected NAND strings at the time of writing data, and the potential of the channel is automatically boosted by a so-called self booth. Thus, the writing of the non-selected columns can be effectively prevented.
[0037]
In the writing of the second data, the upper wiring to which the first voltage V1 and the second voltage V2 are applied is switched. That is, the first voltage V1 (positive voltage) shown in FIG. 6F is applied to the second upper wiring BSL1b, and the second voltage V2 (0 V) shown in FIG. The voltage is applied to the wiring BSL1a. Accordingly, if necessary, the applied voltage of the select gate line and the applied voltage Vpass of the unselected word line are also switched. As a result, the source S and the drain D are switched in FIG. 5A, and hot electrons are locally injected into the charge storage film 3 from the side serving as the source at the time of the first data writing.
The holding region for the electrons injected by the second data writing and the holding region for the electrons injected by the first data writing are separated from each other in position, and the two electron holding regions do not overlap. .
[0038]
FIGS. 7A to 7J are timing charts of the erase operation.
At the time of erasing, for example, block erasing is performed using hot hole injection generated due to band-to-band tunneling. Hereinafter, this erasing method is referred to as BTBT (Band to Band Tunneling) -HH (Hot Hole) implantation erasing.
During the data erasing period, as shown in FIGS. 7G to 7I, the second upper wiring BSL1b connected to the NAND string including the selected cell and the unselected first upper wiring BSL2a , BSL3a,... And unselected second upper wirings BSL2b, BSL3b,.
[0039]
As shown in FIGS. 7A and 7E, a voltage of, for example, 6 V to 8 V is applied to the first and second select gate lines SG1 and SG2, and the first and second select transistors S1 and SG2 are applied. The on state is set in S2. At the same time, a pass voltage Vpass that does not erase data but turns on the memory transistor M1 and transmits the erase drain voltage Vde is applied within a range of, for example, 6 V to 8 V to the unselected word line WL1. Similarly, a pass voltage Vpass sufficient to turn on the memory transistors M3 to Mn and transmit the ground voltage 0V is applied to other unselected word lines WL3 to WLn, for example, in a range of 6V to 8V.
Next, as shown in FIG. 7C, the erase gate voltage Ve is applied to the word line WL2 connected to the cell to be erased Csel, preferably within a range of 0 to -5 V, for example, at a slightly delayed timing. . Further, as shown in FIG. 7F, the erase drain voltage Vde is applied to the first upper wiring BSL1a within a range of, for example, 4V to 6V, preferably at a slightly later timing.
[0040]
As a result, in the selected NAND string, the erase drain voltage Vde applied to the first upper wiring BSL2a changes the selected cell Csel (memory transistor) via the ON-state select transistor S1 and the unselected memory transistor M1. M2) is transmitted to one of the source / drain impurity regions 5 (drain D). Therefore, an erase voltage (= | Ve | + Vde) exceeding 10 V is applied as a third voltage between the source / drain impurity region 5 and the gate electrode (selected word line WL2). As a result, in the source / drain impurity region 5, the surface is in a deep depletion state, the energy band is bent, and electrons tunnel from the valence band to the conduction band due to an interband tunneling phenomenon. At this time, an electron and a hole pair are generated, and the electron flows into the N-type source / drain impurity region and is absorbed. On the other hand, the generated holes are accelerated by the high electric field applied near the junction, become hot holes, and drift toward the center of the channel formation region. Some of the hot holes are locally injected into charge traps in the charge storage film 3.
For this reason, in a writing state in which electrons are injected into the memory transistor M2, and when the threshold voltage is high, the accumulated electrons are offset by the injected hot holes, and the threshold voltage of the memory transistor M2 is erased. The state drops to a lower level.
[0041]
In this erasing method, erasing can be performed from both the source and the drain, but erasing may be performed on only one side as described above. Alternatively, the select transistor S2 on the side on which erasing is not performed may be cut off, and the other source / drain impurity region may be floated.
Of course, depending on the definition of the write state and the erase state, channel hot electron (CHE) injection can be used for erasure and hot hole injection caused by an interband tunnel current can be used for write.
[0042]
The data read operation includes a normal read (hereinafter, referred to as a forward read method) in which a current flows from the drain D to the source S when writing data, and a bias between the drain D and the source S when reading data. The writing is performed in the reverse direction, and the reading is performed in one of the reverse directions in which a current flows from the source S to the drain D during writing (hereinafter, referred to as a reverse reading method). The case of the reverse read method will be described below.
[0043]
FIGS. 8A to 8J are timing charts of the reverse read operation.
During the data reading period, as shown in FIGS. 8F and 8H to 8J, the first upper wiring BSL1a connected to the NAND string including the selected cell, The first upper wirings BSL2a, BSL3a,..., Unselected second upper wirings BSL2b, BSL3b,.
[0044]
As shown in FIGS. 8A and 8E, a voltage of, for example, 3 V to 5 V is applied to the first and second select gate lines SG1 and SG2, and the first and second select transistors S1, The on state is set in S2. At the same time, a pass voltage Vpass, which is lower than the read gate voltage Vgr but is low enough to turn on the memory transistor M1 and transmit the read drain voltage Vdr, is applied to the unselected word line WL1, for example, in the range of 3V to 5V. In addition, a pass voltage Vpass lower than the read gate voltage Vgr but turning on the memory transistors M3 to Mn and transmitting the ground voltage 0V is applied to the other unselected word lines WL3 to WLn, for example, in the range of 3V to 5V. Apply within.
[0045]
Next, as shown in FIG. 8C, a predetermined read gate voltage Vgr is applied to the word line WL2 to which the selected cell Csel (memory transistor M2) is connected, preferably at a slightly delayed timing, for example, from 3 V to 5 V. Apply within the range. The read gate voltage Vgr is lower than the threshold voltage of the memory transistor M2 in the write state, higher than the threshold voltage in the erase state, and a voltage at which the memory transistor M2 operates in the saturation region.
Further, as shown in FIG. 8F, a read drain voltage Vdr is applied to the first upper wiring BSL1a, for example, in a range of 1 V to 2 V, preferably at a slightly later timing. In the reverse read method, data on the source side (second data) is read. For this reason, by optimizing the read drain voltage Vdr, the depletion layer on the drain side is sufficiently extended to the source side, and the accumulated charge corresponding to the first data on the drain side does not significantly affect the read electric field.
Thus, the current or voltage of the first or second upper wiring SBL1a or SBL1b changes according to the data storage state of the memory transistor M. This change is amplified and read by a sense amplifier in the peripheral circuit.
[0046]
To read the first data by the reverse read, the upper wiring to which the read drain voltage Vdr and the ground voltage 0V are applied is switched. That is, the read drain voltage Vdr shown in FIG. 8G is applied to the first upper wiring BSL1a, and the ground voltage 0V shown in FIG. 8F is applied to the second upper wiring BSL1b. Accordingly, if necessary, the applied voltage of the select gate line and the applied voltage Vpass of the unselected word line are also switched. As a result, similarly to the second data reading, the current or voltage of the first or second upper wiring SBL1a or SBL1b changes, and this change is amplified and read by the sense amplifier in the peripheral circuit.
Note that data may be read in units of pages, that is, cells connected to one word line.
[0047]
Other methods for erasing are also possible.
In the first modification of the erasing method, the charges accumulated in the charge storage film 3 are stored in the channel formation region CH by using FN tunneling from the charge storage film 3 of the memory transistor M2 to be erased to the channel formation region CH. Pull out. In this case, a potential having the same polarity as the accumulated charge is applied to the word line WL2 to which the memory transistor M2 to be erased is connected.
In the modified example of the second erasing method, the charge stored in the charge storage film 3 is stored in the word line WL2 by using FN tunneling from the charge storage film 3 of the memory transistor M2 to be erased to the gate electrode (word line WL2). Pull out the charge. In this case, a potential having a polarity opposite to that of the accumulated charge is applied to the word line WL2.
[0048]
Further, the following changes can be made to the transistor structure.
The structure of the charge storage film of the transistor is not limited to the MONOS type, but may be, for example, an MNOS type. Further, the film that mainly accumulates electric charges is not limited to the nitride film 32. ₂ O ₅ Or Ta ₂ O ₃ For example, a high dielectric film having charges and wraps discretely may be used.
The semiconductor on which the memory transistor is formed is not limited to a well such as a P well or a bulk silicon substrate, but may be, for example, an SOI semiconductor layer in an SOI substrate or a thin-film polysilicon in a laminated structure of the substrate. Is also good.
[0049]
In the present embodiment, the following various advantages can be obtained.
First, wiring for supplying a first voltage V1 (positive voltage) and a second voltage V2 (for example, a ground voltage of 0 V) at the time of data writing are separated, and each wiring is a wiring layer (a second wiring layer) above a transistor. One upper wiring SBL1a and a second upper wiring SBL1b). These wirings are connected to the first voltage supply means 20, and the first voltage supply means 20 supplies the first and second voltages V1 and V2. Since the first voltage supply means 20 has a configuration in which the above-mentioned two voltages can be exchanged, it is easy to write two bits into one cell. Further, since the first upper wiring SBL1a and the second upper wiring SBL1b are provided separately, random writing for each bit is possible. Since these upper wirings are composed of upper wiring layers, they have a lower resistivity than the impurity diffusion layers, and the first and second voltages V1 and V2 are transmitted to the ends of the NAND strings without much voltage drop.
Further, high-speed erasing using the interband tunnel current can be performed for each bit. Since high-speed erasing using the interband tunnel current is performed without forming a channel, current consumption can be reduced.
[0050]
Second, since the charge storage film of the transistor has a so-called MONOS structure in which a plurality of dielectric films are stacked, the voltage at the time of writing and erasing can be set lower than that of the FG type.
In addition, the problem of disturb of unselected cells at the time of writing and erasing is improved.
Since CHE injection is used for writing data, the first oxide film can be determined within a range from 2.5 nm to 6.0 nm depending on the intended use. At the time of reading, a pass voltage is applied to a non-selected word line. However, since the first oxide film is relatively thick, FN injection of charges into the charge storage film does not occur. That is, weak erroneous writing to a cell connected to an unselected word line at the time of reading, which has been a problem in the conventional MONOS type using a thin first oxide film of about 2 nm, can be prevented.
[0051]
Third, cell operation is stable.
Since this is a multi-valued technology that stores 2-bit data at a local position, the operation margin is larger than that of multi-valued data obtained by dividing the threshold voltage into smaller values, and the operation is stable.
Further, capacitive coupling between surrounding cells is reduced.
In the conventional FG type NAND memory cell array, when the cell is miniaturized, the coupling capacitance between the floating gates or between the floating gate and an adjacent word line increases, causing a fluctuation in the floating gate potential and a decrease in operation stability due to the fluctuation. Malfunctions are a problem.
On the other hand, in the present embodiment, a discrete charge storage means is provided, which is different from a conventional floating gate formed of a single conductive layer, and is different from the charge storage means and word line of other neighboring cells. Does not capacitively couple with Therefore, this memory cell has high operation stability and is unlikely to malfunction.
[0052]
Fourth, since the first upper wiring BSL1a and the like and the second upper wiring BSL1b and the like are formed in different wiring layers, the cell area is relatively small even if the wiring is divided. In the case of 2-bit storage, the cell area per bit is smaller than that of a conventional FG type NAND array cell.
That is, as described above, in the cell array according to the present embodiment, since the wiring pitch in the column direction is 2F and the wiring pitch in the row direction is 3F, the cell area is about 6F. ² It becomes. Assuming that the area occupied by the first and second contacts C1 and C2 is 3F × 3F = 9F, respectively. ² However, since these are shared by two NAND strings adjacent in the column direction, even if the number of cells in one string is estimated to be, for example, 16 as a minimum, the contact area is 0.28F per cell. ² And extremely small. Therefore, for 2-bit storage, the effective cell area per bit is up to about 3.14F ² / Bit. This is the normal FG type cell area 4F ² / Bit.
[0053]
【The invention's effect】
According to the data writing method for a nonvolatile semiconductor memory device according to the present invention, in a so-called NAND memory cell array in which a contact is shared by a large number of cells, the effective cell area is small. And the effective cell area per bit can be further reduced. In addition, since the threshold voltage is not multi-valued with fine division, the operation margin is large and the operation is stable.
According to the nonvolatile semiconductor memory device of the present invention, it is possible to provide a nonvolatile semiconductor memory device having a configuration capable of suitably executing the above-described data writing.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a basic configuration of a nonvolatile memory cell array according to an embodiment of the present invention.
FIG. 2 is a plan view of a memory cell array mainly showing a NAND string in a second column shown in FIG. 1;
FIG. 3 is a cross-sectional view of a part indicated by line AA in FIG.
FIG. 4 is a cross-sectional view of a portion indicated by line BB in FIG.
FIG. 5A is a cross-sectional view showing a part of a memory transistor in an enlarged manner, and FIG. 5B is an explanatory diagram of a write operation.
FIGS. 6A to 6J are timing charts of a write operation.
FIGS. 7A to 7J are timing charts of an erasing operation.
FIGS. 8A to 8J are timing charts of a reverse read operation.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... P well, 3 ... Charge storage film, 4 ... Gate insulating film, 5 ... Source / drain impurity region, 6 ... First shared impurity region, 7 ... Second supply impurity region, 8 ... Interlayer insulating film, 10 element isolation insulating layer, 20 first voltage supply means, 30 second voltage supply means, 31 first oxide film, 32 nitride film, 33 second oxide film, CH: channel formation region, BSL1a, etc .: first upper wiring, BSL1b, etc .: second upper wiring, M1, etc .: memory transistor, S1, etc. select transistor, SG11, etc. select gate line, WL1, etc. word line.

Claims (9)

First and second select transistors whose on and off are independently controlled, a plurality of transistor rows each including a plurality of memory transistors cascaded between the select transistors;
A charge storage film comprising a plurality of dielectric films stacked on a semiconductor in the transistor array, and storing charge in the plurality of stacked dielectric films;
A plurality of word lines formed on the charge storage film and electrically connecting the gates of the memory transistors in different transistor rows adjacent to each other in a direction crossing the direction of the cascade connection of the plurality of memory transistors;
A first upper wiring for supplying a first voltage to the memory transistor via the first select transistor;
A second upper wiring for supplying a second voltage to the memory transistor via the second select transistor;
A nonvolatile semiconductor memory device having: 2. The nonvolatile semiconductor memory device according to claim 1, wherein said second upper wiring is formed on a layer above said first upper wiring. By supplying the first voltage to the first upper wiring and supplying the second voltage to the second upper wiring, the first data is supplied to the memory transistor selected in the transistor row. The wiring for applying the first voltage and the second voltage is switched between the first upper wiring and the second upper wiring to store the first voltage and the second voltage. Supply means for storing second data in the selected memory transistor independently of the first data,
A write voltage is applied to a word line to which the selected memory transistor is connected, and a non-selected memory transistor is connected between the selected memory transistor and the first or second select transistor. Second voltage supply means for applying a pass voltage to turn on the unselected memory transistor to the word line;
The nonvolatile semiconductor memory device according to claim 1, further comprising: The first voltage supply means and the second voltage supply means control the first voltage, the second voltage, and the write voltage, form a channel in the selected memory transistor, and The first data is written by injecting the charge accelerating into the charge storage film from the vicinity of one channel end, and the charge is applied from the vicinity of the channel end on the opposite side to the time when the first data is written by switching the voltage. 4. The non-volatile semiconductor memory device according to claim 3, wherein said second data is written by injecting data. The first voltage supply means and the second voltage supply means may include a memory transistor selected on at least one of a side on which the first data is written and a side on which the second data is written. A third voltage is applied between the gate and the source or drain of the semiconductor device, and a charge having a polarity opposite to that of the write operation is applied to at least one of the first data storage area and the second data storage area. 5. The nonvolatile semiconductor memory device according to claim 4, wherein stored data is erased by injecting the data from the side of the nonvolatile semiconductor memory. The first voltage supply means and the second voltage supply means, when writing the first data or the second data, use the gates of the first and second selector transistors, the non-selected memory transistor After applying a voltage to each of the gate of the selected memory transistor and the gate of the selected memory transistor, at least one of the first voltage and the second voltage is applied to the first upper wiring or the second upper wiring. The nonvolatile semiconductor memory device according to claim 4, wherein: First and second select transistors whose on and off are independently controlled, and a transistor row including a plurality of memory transistors cascaded between the select transistors, respectively.
Applying a pass voltage to turn on the unselected memory transistor to the gate of the unselected memory transistor;
Applying a write voltage to the gate of the selected memory transistor;
Supplying a first voltage to the transistor array from one side of the first and second select transistors in an on state;
Supplying a second voltage to the transistor array from the other side of the first and second select transistors in an on state;
Has,
The steps of applying the pass voltage, the write voltage, the first voltage, and the second voltage are performed while switching between the side to which the first voltage is applied and the side to which the second voltage is applied. A data writing method for a non-volatile semiconductor memory device in which first data and second data are repeatedly written into the selected memory transistor independently. In the writing of the first data and the writing of the second data, at least one of the steps of supplying the first and second voltages includes the step of applying the pass voltage and the step of applying the write voltage. 8. The data writing method for a nonvolatile semiconductor memory device according to claim 7, which is performed later. The memory transistor is
A charge storage film comprising a plurality of dielectric films stacked on the semiconductor and storing charge in the plurality of stacked dielectric films,
A gate electrode formed on the charge storage film;
8. The data writing method for a nonvolatile semiconductor memory device according to claim 7, comprising:

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