JP2007157289A - Nonvolatile semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which noise is reduced and reliability is high. <P>SOLUTION: The nonvolatile semiconductor memory device has a memory cell array having a plurality of memory cells connected in series in a form of sharing source and drain regions, a plurality of word lines connected to each of a plurality of memory cells connected in series, and a peripheral circuit part performing control of the memory cell array, and it is characterized in that timing at which selection voltage is applied is different from timing at which readout voltage is applied in readout operation. In this device, timing at which selection voltage is applied is made later than timing at which readout voltage is applied. Also in a period between timing at which readout voltage is applied and timing at which selection voltage is applied, a gate in the memory cell to which the selection voltage is applied is in a floating state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor device.

  In recent years, so-called nonvolatile semiconductor memory devices that hold stored data in a nonvolatile manner have become widespread among semiconductor memory devices. Some of such semiconductor memory devices have a memory cell array structure called a NAND type.

  A semiconductor memory device having a memory cell array structure called a NAND type has a plurality of memory cells connected in series with a common source / drain region, and is connected at the drain side end of the plurality of memory cells connected in series. Connected to the source-side select transistor, the source-side select transistor connected at the source-side end opposite to this end, and the source-drain region on the side not connected to the memory cell of the drain-side select transistor And a plurality of memory cell units having bit lines. Further, the semiconductor memory device includes a drain side selection gate line connected in common to the gates of the drain side selection transistors in each unit, a source side selection gate line connected in common to the gates of the source side selection transistors, The memory cell unit has a plurality of word lines connected in common to the gates of the memory cells at the same electrical connection position. Note that this semiconductor memory device can perform a read operation and a write operation by applying a voltage to each wiring such as a word line, a gate line, and a bit line from a circuit outside the memory cell. Note that Patent Documents 1 and 2 below describe conventional techniques for controlling voltage application to a wiring in a read operation or the like.

JP-A-8-55488 JP 2000-173300 A

  An object of the present invention is to provide a highly reliable non-volatile semiconductor memory device in which noise is further reduced.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of memory cells connected in series with a common source / drain region, and a plurality of memory cells connected to each of the plurality of memory cells connected in series. A nonvolatile semiconductor memory device having a memory cell array having a word line and a peripheral circuit unit for controlling the memory cell array, wherein a timing for applying a selection voltage and a timing for applying a read voltage in a read operation It is characterized by being different.

  According to the present invention, a highly reliable nonvolatile semiconductor device in which noise is further reduced can be provided.

  The inventors of the present invention have examined the read operation in the nonvolatile semiconductor device and found that two coupling noises are mainly generated. Specifically, the first noise is that when a voltage is applied to the selected word line connected to the gate line of the selected memory cell, a charge flows to the voltage generation circuit side connected to the outside, and the voltage This is undershoot, and another noise is an overshoot that occurs when an unselected word line is boosted to the read voltage. These not only affect reliability as noise, but also lead to an increase in read operation and write time.

  The inventors of the present invention have made extensive studies in view of the above problems, and in the read operation of the nonvolatile semiconductor memory device, the timing at which the selection voltage is applied and the timing at which the read voltage is applied are different from each other. The present invention has been completed with the idea that the timing of two coupling noises can be made different and the coupling noises can be offset.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes and is not limited to the embodiments shown below. Note that in this specification, portions having the same or similar functions are denoted by the same reference numerals, and repeated description thereof is omitted.

(Embodiment)
FIG. 1 is a schematic block diagram of a nonvolatile memory device (hereinafter referred to as “the present nonvolatile memory device”) according to the present embodiment. The nonvolatile memory device 1 shown in FIG. 1 includes a plurality of gate lines, a plurality of word lines arranged along the plurality of gate lines, a plurality of word lines, and a plurality of gate lines arranged to cross the plurality of gate lines. Bit line, a memory cell array 2 having a plurality of memory cells, a bit line control circuit 3 for controlling the bit lines in the memory cell array 2, a word line control circuit 4 for controlling the word lines in the memory cell array 2, and a memory cell array 2, a gate control circuit 5 that controls the gate lines, a control signal generation circuit 6 that generates control signals in the word line control circuit 3, the bit line control circuit 4, the gate line control circuit 5, and the like, and the control signal generation circuit 6 has a signal input terminal 7 for inputting a signal as a basis thereof. The nonvolatile memory device 1 also includes a data input / output buffer 8 connected to the bit line control circuit 3 and a data input / output terminal 9 connected to the data input / output buffer 8 (note that In this specification, a circuit including various circuits such as the bit line control circuit, the word line control circuit, the gate line control circuit, and the control signal generation circuit is referred to as a “peripheral circuit portion”.)

  Here, FIG. 2 shows a configuration of the memory cell array 2. The memory cell array 2 shown in FIG. 2 is configured by arranging a plurality of memory cell units MU0, MU1,... MUj in parallel, and each memory cell unit is arranged in series with a common source / drain region. A plurality of memory cells MC0, MC1,..., MCi, a source side select transistor S1 connected to one end (source region side) of these connections, and a drain side select transistor connected to the other end (drain region side) S2. Note that the gates of the memory cells MC0, MC1,..., MCi are floating gates, and these memory cells are connected to the floating gate and word of the memory cells in the same electrical connection position in other memory cell units. They are connected in common via lines (WL0, WL1,..., WLi). Further, the gate of the source side select transistor S1 in each memory cell unit is connected to the source side select gate line SGS common to the memory cell array. Similarly, the gate of the drain side select transistor S2 is also connected to the drain common to the memory cell array. It is connected to the side selection gate line SGD. Further, the drain region of the drain side select transistor S2 in each memory block is connected to bit lines BL0, BL1,..., BLi provided corresponding to each memory block, and the source side select transistor S1 in each memory block is connected. The source region is commonly connected to a cell source line CELSRC common to the memory cell array 2.

  FIG. 3 shows detailed functional blocks of the word line control circuit 4 and the control signal generation circuit 6 in the nonvolatile semiconductor memory device shown in FIG. The control signal generator 6 includes at least a read voltage generator 61 that generates a read voltage Vread and a selection voltage generator 62 that generates a selection voltage Vcgrv. On the other hand, the word line control circuit 4 has a plurality of voltage transfer transistors 41 connected to each word line in the memory cell array 2 and a plurality of CG drivers 42 connected to each of these voltage transfer transistors. Each CG driver 42 is connected to the read generation device 61 and the selection voltage generation device 62, and selects either the read voltage Vread or the selection voltage Vcgrv depending on whether the connected memory cell is selected or not selected. To do. The plurality of voltage transfer transistors 41 have their gates connected to a common gate line. When a voltage of a predetermined value or higher is applied, the gates of the voltage transfer transistors 41 are turned on at one time. A selected voltage can be applied to each word line. In this nonvolatile semiconductor device, a selection voltage transfer circuit 63 is provided between the selection voltage generation circuit 62 in the control signal generation device 6 and the CG driver 42 of the word line control circuit 4 to apply the selection voltage. In this case, the application voltage is controlled by the selection voltage transfer circuit 63 (more specific operation will be described later). The selection voltage transfer circuit 63 can perform an operation of transferring a necessary voltage to the CG driver 42 not only in the read operation but also in the write operation.

  Next, a data read operation of the nonvolatile semiconductor device will be described with reference to FIG. FIG. 4 shows a timing chart when reading the memory cell MC0 adjacent to the source side select transistor in the memory cell unit MU0 in FIG. In the nonvolatile semiconductor memory device, first, at time t1, the voltage Vsg is applied to the source side selection gate line. Next, at time t2, the voltage Vbl is applied to the bit line BL0. At time t3, a word line (hereinafter referred to as non-selected memory) connected to memory cells (hereinafter referred to as “non-selected memory cells”) MC1 to MC1 other than memory cells (hereinafter referred to as “selected memory cells”) MC0 to be read. A word line connected to the cell is referred to as a “non-selected word line.”) A read voltage Vread is applied to WL1 to WLi. Thereafter, at time t4, the selection voltage applied to the word line (hereinafter referred to as “selected word line”) connected to the selected memory cell MC0 is boosted to Vcgrv. Then, at time t5, the voltage Vsg is applied to the drain side selection gate SGD, and the gate of the drain side selection transistor is turned ON. That is, by such an operation, the drain-side selection transistor, the source-side selection transistor, and the gate of the non-selected memory cell are turned on, and “0” data is stored in the selected memory cell or “1” data is stored. The voltage change of the bit line occurs depending on whether it is stored, and data can be read by determining the change of the voltage on the bit line BL0 at time t5. Although an example in which the memory cell MC0 adjacent to the source side selection transistor is selected is described here, in the present embodiment, coupling noise with an adjacent non-selected word line is taken into consideration as will be described later. Therefore, the position of the selected memory cell is not particularly limited.

  One feature of the nonvolatile semiconductor memory device is that the boosting timings of the selected word line WL0 and the unselected word lines WL1 to WLi are different. More specifically, the boost timing of the selected word line is later than the boost timing of the non-selected word line. This is because the memory cell adjacent to the selected memory cell is an unselected memory cell, and when the selected word line and the unselected word line are boosted almost simultaneously, coupling noise occurs between them, and the voltage of the selected word line This is to avoid this because it may overshoot. More specifically, when the selected word line and the non-selected word line are boosted almost simultaneously, two noises are generated. The first noise is generated at the moment when the selected word line and the selected voltage generation circuit are connected via the CG driver. This is because the burden on the selection voltage generating circuit increases at the moment when the selected word line is connected. As a result, charge flows through the load and the potential of the selected word line undershoots. After that, the selection voltage generation circuit charges the load of the selected word line again and converges it to a desired voltage Vcgrv (for example, about 2V). On the other hand, the second noise is generated when the unselected word line is boosted to the read voltage Vread. Since the selected word line is always adjacent to the non-selected word line, it is generated when the potential of the selected word line is overshooted by the coupling noise of the non-selected word line. If the selected word line voltage exceeds the allowable range and undershoots or overshoots, the selected voltage will not converge to the desired voltage, and this coupling noise will have to wait until the coupling noise has converged. It takes time for reading, which leads to an increase in writing time. On the other hand, in the nonvolatile semiconductor memory device, as described above, by first boosting the unselected word line, the timing at which the potential of the selected word line undershoots can be delayed. As a result, the coupling noise peak received from the unselected word line and overshooting can be brought closer to the timing at which the potential of the selected word line undershoots, and the coupling noise can be reduced. Note that the delay time in the nonvolatile semiconductor memory device can be appropriately adjusted according to the voltage, the wiring interval, and the like, and is not particularly limited as long as the above effects can be obtained, but may be larger than zero. At least necessary. On the other hand, the upper limit of the delay time can be adjusted as appropriate as described above. However, the voltage of the selected word line becomes Vcgrv before the selection gate line to be boosted later (drain side selection gate line SGD in the example of FIG. 4) is boosted. The upper limit corresponds to the time until the selection gate line is turned on. Specific numerical values are, for example, larger than 0 μsec and not longer than 5 μsec, 0.5 μsec to 5 μsec, 1.0 μsec to 5 μsec, or 1.5 μsec to 5 μsec depending on the embodiment. The following is desirable. Further, it is more preferable that the gate of the selected memory cell in this period is in a floating state, and the previous voltage may be held during the period t3 to t4 (the delay time).

  The effect of noise reduction in this nonvolatile semiconductor memory device was confirmed by conducting a specific simulation. The results are shown in FIGS. FIG. 5 shows a case where the timing for boosting the selected word line is delayed by 1 μsec from the timing for boosting the unselected word line, and FIG. 6 shows a case where the timing is delayed by 1.5 μsec. According to the result of FIG. 5, it can be confirmed that the voltage overshooting from the potential of the selection voltage Vcgrv (here, 2 V, see the dotted circle in the figure) can be reduced by delaying the boosting timing of the selected word line by 1 μsec. (Note that FIG. 7 shows the simulation result when the timing for boosting the selected word line and the timing for boosting the non-selected word line are set substantially the same). Further, FIG. 6 shows an example in which the delay time is 1.5 μs, but according to this, it can be further reduced, and it has been confirmed that the noise is almost zero. As a result, it can be confirmed that the setup time of the selected word line can be shortened, and in particular, the write time and the like are shortened. In this simulation, the unselected word line is charged to Vdd and then boosted to the read voltage Vread. However, the same result can be obtained when the unselected word line is boosted from Vss to the read voltage Vread. It is considered possible.

  Here, an example of a circuit configuration for realizing the above operation will be described with reference to FIG. FIG. 8 is a diagram illustrating the inside of the selection voltage transfer circuit 63 of the control signal generation circuit 6 shown in FIG. The selection voltage transfer circuit 63 shown in FIG. 8 can apply a selection voltage when the voltage transfer transistor 41 is turned on at t4, or can set the gate of the memory cell to a floating state. It is comprised. That is, according to the above configuration, the nonvolatile semiconductor memory device can enter the selected word line in a floating state at time t4, and can switch to the selected voltage and apply the selected voltage to the selected word line at time t5. . FIG. 9 shows values of the voltages CGSVCGRV-V and CGSFLO-V (in the vicinity of times t3 to t5) in the selection voltage selection circuit 63. Prior to time t3 in FIG. 9, CGSVCGRV-V and CGSFLO-V are both Vss. At this time, since the LVNE transistor in FIG. 8 is turned on, the selected WL voltage also becomes Vss. Next, between time t3 and time t4, Vdd is applied only to CGSFLO-V. At this time, the LVNE transistor that transfers Vss is turned off, and the HVNE transistor that transfers the selection voltage is also turned off, so that the selection WL can be in a floating state. Finally, at time t4, Vdd is applied to CGSVCGRV-V and Vss is applied to CGSFLO-V. At this time, the LVNE transistor that transfers VSS is kept off, and the HVNE transistor that transfers the selection voltage is turned on, so that the selection voltage can be transferred to the selected word line.

  Here, FIG. 10 shows a partial cross-sectional view of the nonvolatile semiconductor memory device. This figure shows a case where one memory cell unit is cut by a cross section passing through both the source side select transistor and the drain side select transistor. As described above, the nonvolatile semiconductor memory device is arranged in correspondence with the substrate and the plurality of memory cells, the drain side selection transistor, the source side selection transistor, and the floating gates of the plurality of memory cells arranged on the substrate. A word line, a bit line connected to the drain region of the drain side select transistor, and a cell source line connected to the source region of the source side select transistor. In FIG. 10, the substrate, the floating gate, the word line, A cross section of a bit line or the like is shown. In the nonvolatile semiconductor device, a source-side selection transistor shunt line (SGS shunt line) connected to the source-side selection transistor, and a drain-side selection transistor shunt line (SGD) connected to the drain-side selection transistor. Shunt line).

  As described above, the nonvolatile semiconductor memory device according to this embodiment can provide a highly reliable nonvolatile semiconductor memory device in which noise is further reduced.

  In addition, the nonvolatile semiconductor memory device according to this embodiment can be mounted on a memory card. In this case, it can be realized by providing a controller for controlling the nonvolatile semiconductor memory device, a pad portion, and the like. This figure is shown in FIG.

FIG. 3 is a functional block diagram of the nonvolatile semiconductor memory device according to the embodiment. 1 is a diagram showing a configuration of a memory cell array of a nonvolatile semiconductor memory device according to an embodiment. FIG. 3 is a diagram illustrating functional blocks of a memory cell, a word line control circuit, and a control signal generation circuit in the nonvolatile semiconductor memory device according to the embodiment. FIG. 6 is a view showing a timing chart in a read operation of the nonvolatile semiconductor device according to the embodiment. The figure which shows the simulation result about the non-volatile semiconductor device which concerns on embodiment. The result when the boost of the selected word line is sent for 1 μs compared to the boost of the non-selected word line is shown. The figure which shows the simulation result about the non-volatile semiconductor device which concerns on embodiment. The result when the boost of the selected word line is sent for 1.5 μs compared to the boost of the non-selected word line is shown. The figure which shows the simulation result about a non-volatile semiconductor device. The figure which shows the result at the time of boosting the selected word line and boosting the non-selected word line simultaneously. The figure explaining the inside of the control signal generation circuit selection voltage transfer circuit 63 concerning this embodiment The figure which shows the timing chart (t3-t5 vicinity) regarding the selection voltage transfer circuit 63 shown in FIG. 1 is a partial cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment. The figure which shows the structure of the memory card carrying the non-volatile semiconductor device concerning this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device 2 ... Memory cell array 3 ... Bit line control circuit 4 ... Word line control circuit 5 ... Gate line control circuit 6 ... Control signal generation circuit 7 ... Signal input terminal 8 ... Data input / output buffer 9 ... Data input Output terminals MC0-i ... Memory cell S1 ... Source side select transistor S2 ... Drain side select transistor WL0-i ... Word line SGD ... Drain side select gate line SGS ... Source side select gate line MB0-j ... Memory cell units BL0-j ... Bit line 41 ... Voltage transfer transistor 61 ... Read voltage generation circuit 62 ... Selection voltage generation circuit 63 ... Selection voltage transfer circuit

Claims (5)

A memory cell array having a plurality of memory cells connected in series with a common source / drain region, and a plurality of word lines connected to each of the plurality of memory cells connected in series;
A non-volatile semiconductor memory device having a peripheral circuit section for controlling the memory cell array,
A nonvolatile semiconductor memory device, wherein a timing for applying a selection voltage and a timing for applying a read voltage are different in a read operation.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the timing for applying the selection voltage is later than the timing for applying the read voltage.   3. The nonvolatile memory according to claim 2, wherein a gate of the memory cell to which the selection voltage is applied is in a floating state during a period between the timing of applying the read voltage and the timing of applying the selection voltage. Semiconductor device.   The nonvolatile semiconductor device according to claim 1, wherein the timing for applying the selection voltage is later than 0.5 μsec by the timing for applying the read voltage. The nonvolatile semiconductor device according to claim 1, wherein the timing for applying the selection voltage is 1 μs or more later than the timing for applying the read voltage.