JP2875109B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to improvement in performance and reliability by making the thickness of a gate insulating film substantially uniform in a portion where writing / erasing is performed. The present invention relates to a nonvolatile semiconductor memory device capable of performing the following.

[0002]

2. Description of the Related Art An EEPROM is known as a memory device having a structure in which data can be freely programmed and which can be electrically written and erased. Hereinafter, a flash memory will be described as an example of a conventional EEPROM with reference to FIGS.

FIG. 30 is a block diagram showing a general configuration of a conventional flash memory. Referring to FIG.
The flash memory includes a memory cell array 100 arranged in a matrix, an X address decoder 200, a Y gate / sense amplifier 300, and a Y address decoder 400.
, Address buffer 500 and input / output buffer 600
And control logic 700.

[0004] The memory cell array 100 has memory transistors arranged therein in a matrix. In order to select a row and a column of the memory cell array 100,
The X address decoder 200 is connected to the Y gate and the sense amplifier 300. Y gate, sense amplifier 3
00 is a Y address decoder 4 for providing column selection information.
00 is connected. X address decoder 200 and Y
The address decoder 400 is connected to an address buffer 500 for temporarily storing address information.

An input / output buffer 600 for temporarily storing input / output data is connected to the Y gate and the sense amplifier 300. Address buffer 500 and input / output buffer 6
00 is connected to control logic 700 for controlling the operation of the flash memory. The control logic 700 performs control based on a chip enable signal, an output enable signal, and a program signal.

Next, with reference to FIG.
The internal structure of the array 100 will be described in more detail.
You. FIG. 31 is a schematic diagram of the memory cell array 100 described above.
It is an equivalent circuit diagram showing composition. Referring to FIG.
Word lines WL extending to ₁, WL_Two, ... WL
_iAnd a plurality of bit lines BL extending in the column direction₁, B
L_Two, ... BL_iAre arranged so as to be orthogonal to each other.
Make up the tricks. Each word line and each bit line
Each intersection has a floating gate electrode
Memory transistor Q₁₁, Q₁₂, ... Q_iiIs arranged
You.

[0007] The drain region of each memory transistor is connected to each bit line, and the control gate electrode of the memory transistor is connected to each word line. The source region of the memory transistor is connected to each source line S
₁ , S ₂ ,... The source regions of the memory transistors belonging to the same row are connected to each other as shown in FIG. 31, and the source lines S ₁ , S
Connected to _two .

Next, a sectional structure of the memory cell array 100 will be described with reference to FIG. FIG.
FIG. 3 is a partial cross-sectional view of the memory cell array 100. FIG. 33 is an enlarged sectional view of one memory transistor.

Referring to FIGS. 32 and 33, a source diffusion region 106 and a drain diffusion region 107 are formed on the main surface of p-type semiconductor substrate 101 at intervals.
On a region between source diffusion region 106 and drain diffusion region 107, gate insulating film 102 having a thickness of about 100 ° is formed. On this gate insulating film 102, a floating gate electrode 103 made of a polycrystalline silicon film or the like is formed. On this floating gate electrode 103, an interlayer insulating film 104 made of an ONO film or the like is formed.

On the interlayer insulating film 104, a control gate electrode 105 made of a polycrystalline silicon film or the like is formed. Oxide film 10 is formed so as to cover control gate electrode 105 and floating gate electrode 103.
8 is formed, and a smooth coat film 109 is formed on the oxide film 108. A contact hole 112 is formed at a predetermined position of the smooth coat film 109, and a bit line 111 is formed on the inner surface of the contact hole 112 and on the smooth coat film 109.

Referring to FIG. 33, the structure of the memory transistor will be described in more detail by focusing on one of the plurality of memory transistors shown in FIG. Referring to FIG. 33, a gate bird's beak 110 generated at the time of forming the smooth coat film 109 and the like is formed at the ends of the floating gate electrode 103 and the control gate electrode 105. In this specification, a portion where the thickness of the oxide film near the floating gate electrode 103 and the control gate electrode 105 is increased due to oxidation at the time of the oxidation process is referred to as a “gate bird's beak”. And Then, the source diffusion region 106 and the drain diffusion region 10 have an end near the lower portion of the gate bird's beak 110 below the floating gate electrode 103.
7 are formed.

Next, the operation of the flash memory having the above structure will be described. First, the write operation will be described. When writing, the drain diffusion region 107
And a voltage (Vg) of about 13 V is applied to the control gate electrode 105.
Thereby, the drain diffusion region 107 and the gate insulating film 1
In the vicinity of 02, electrons having high energy are generated due to the avalanche breakdown phenomenon. Some of the electrons are attracted to the floating gate electrode 103 by the electric field generated by the application of Vg. As a result, electrons are stored in the floating gate electrode 103.

As described above, the floating gate electrode 1
When electrons are stored in the transistor 03, the threshold voltage of the transistor increases. The state in which the threshold voltage is increased in this manner becomes the written state “0”. And
As shown in FIG. 33, floating gate electrode 1
03 is covered with an oxide film 108,
The electrons once injected into the floating gate electrode 103 remain in the floating gate electrode 103 unless high energy is obtained from the outside, and the stored state does not change forever.

Next, the erasing operation will be described. At the time of erasing, a voltage of about 12 V (V
s), the control gate electrode 105 is grounded, and the drain diffusion region 107 is set in a floating state. Then, the voltage V applied to the source diffusion region 106
s, the floating gate electrode 104
The electrons inside the gate insulating film 102 cause FN (Fowler Nordh
eim) Pass by tunnel phenomenon. As a result, electrons are extracted from the floating gate electrode 103. Thus, the floating gate electrode 10
By extracting electrons from 3, the threshold voltage of the memory transistor decreases. This state in which the threshold voltage is lowered is called an erased state "1".

Next, the read operation will be described. At the time of reading, the source diffusion region 106 is held at the ground state, a voltage of about 1 V is applied to the drain diffusion region 107, and a voltage of about 5 V is applied to the control gate electrode 105.
At this time, the above described “0” or “1” is determined depending on whether a current flows in the channel region of the memory transistor.

Next, a method of manufacturing a conventional flash memory having the above-described structure will be described with reference to FIGS. 34 to 44 are cross-sectional views showing first to eleventh steps in a conventional flash memory manufacturing process.

Referring to FIG. 34, a p-type semiconductor substrate 101 on which a desired well or a field oxide film has been formed is prepared. Then, as shown in FIG. 35, a gate insulating film 102 having a thickness of about 100 ° is formed on the surface of the p-type semiconductor substrate 101 by performing a thermal oxidation process. Next, as shown in FIG. 36, a CVD (Chemical Vapor Depos) is formed on the gate insulating film 102.
The polycrystalline silicon film 103 having a thickness of about 2000 ° is formed by using the ition method) or the like. This polycrystalline silicon film 103 becomes the floating gate electrode 103. On this polycrystalline silicon film 103, as shown in FIG. 37, an interlayer insulating film 104 made of an ONO film or the like is formed by using a CVD method or the like. This interlayer insulating film 104
Has a thickness of about 300 °.

Next, as shown in FIG. 38, a polycrystalline silicon film 105 having a thickness of about 3000 ° is formed on the interlayer insulating film 104 by using the CVD method. The polycrystalline silicon film 105 serves as a control gate electrode 105
Becomes Thereafter, as shown in FIG. 39, the gate insulating film 102, the polycrystalline silicon films 103 and 105, and the interlayer insulating film 104 are patterned into desired shapes by using a photolithography technique and an etching technique. Thereby, floating gate electrode 103 and control gate electrode 105 are formed.

Next, referring to FIG. 40, arsenic (As) ions are self-aligned to 3 × 10 5 in a predetermined region on the main surface of p-type semiconductor substrate 101 using control gate electrode 105 or the like as a mask. Inject about ¹⁵ (cm ^-2 ). And by performing the thermal diffusion process,
The arsenic (As) ions are diffused and the source diffusion region 10 is diffused.
6 and the drain diffusion region 107 are formed.

Referring to FIG. 41, an oxide film 108 is formed by performing a thermal oxidation process. Further, as shown in FIG. 42, a smooth coat film 109 is formed on oxide film 108 by using a CVD method or the like. Then, as shown in FIG. 43, the smooth coat film 109 is formed.
Is performed at a temperature of about 900 ° C. in order to improve the flatness of the surface. At this time, as shown in FIG. 43, oxidation also proceeds at the ends of the floating gate electrode 103 and the control gate electrode 105. Thus, gate bird's beaks 110 are formed at the ends of control gate electrode 103 and floating gate electrode 104.

After that, as shown in FIG. 44, the smooth coat film 109 is
An aluminum (Al) film having a thickness of about 0000 ° is formed. Then, the bit line 111 is formed by patterning this aluminum (Al) film into a predetermined shape using a photolithography technique and an etching technique.

[0022]

As described above, in the conventional flash memory, a portion near the lower portion of the gate bird's beak 110 under the floating gate electrode 103 is provided.
The ends of the source diffusion region 106 and the drain diffusion region 107 were located. For this reason, the following problem has occurred. The problem will be described with reference to FIG. FIG. 45 is an explanatory diagram for explaining the write and erase operations of the above-mentioned conventional flash memory.

Referring to FIG. 45, in the flash memory, writing and erasing are performed by generating a high electric field at the lower end of floating gate electrode 103 during writing or erasing, as described above. As shown in FIG. 45, electrons move during writing (1) or erasing (2) between the end of the drain diffusion region 107 and the vicinity of the lower end of the floating gate electrode 103 and the end of the source diffusion region 106 and the floating gate. It occurs between the vicinity of the lower end of the electrode 103. That is, the movement of electrons during writing and erasing is performed in the vicinity of the region where gate bird's beak 110 is formed. For this reason, in the conventional flash memory, the film quality such as the film thickness and the withstand voltage of the gate bird's beak portion 110 has a great influence on the performance and reliability of the memory transistor.

Here, the dependence of the writing and erasing characteristics on the film thickness will be described. For the write operation, the gate insulating film 1
The thicker the film thickness of 02, the better the writing characteristics. on the other hand,
The erasing operation is performed using the FN tunnel phenomenon. Then, J = exp (a
E ^-1 ) (In this equation, J indicates a current value, and a
Is a constant, and E indicates the electric field strength), and is strongly affected by the electric field. Therefore, the electric field is increased by reducing the thickness of the gate insulating film, so that a tunnel current easily flows. That is, erasing characteristics are improved by reducing the thickness of the gate insulating film.

As described above, it can be said that the change in the thickness of the gate insulating film 102 in the portion where writing and erasing are performed affects writing and erasing characteristics.
However, in the conventional flash memory, the source diffusion region 106 or the drain diffusion region 107 is located near the lower portion of the portion where the gate bird's beak 110 is formed.
In the vicinity of the channel region. Thus, it can be said that the thickness of the gate insulating film 102 in a portion where writing or erasing is performed varies for each memory transistor. Therefore, there is a problem that the performance or reliability of the flash memory is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a high-performance and highly reliable flash memory capable of performing a stable writing or erasing operation and a method of manufacturing the same. The purpose is to:

[0027]

A nonvolatile semiconductor memory device according to the present invention is formed so as to define a first conductivity type semiconductor substrate having a main surface and a channel region on the main surface of the semiconductor substrate. A pair of impurity regions of the second conductivity type and an end located at a predetermined distance from the channel region and formed so as to extend in a direction away from the channel region and serve as a diffusion source for forming the impurity region. A pair of impurity-introduced layers, a gate insulating film formed on the channel region and the impurity-introduced layer, and a gate insulating film formed on the channel region such that both ends of the gate insulating film rise over the impurity-doped layer. A floating gate electrode formed via a film, and a control gate electrode formed on the floating gate electrode via an interlayer insulating film are provided.

According to the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, first, an impurity in which a second conductivity type impurity is introduced at a predetermined interval on a first conductivity type semiconductor substrate having a main surface. An introduction layer is formed. Then, a pair of second conductivity type impurity regions is formed so as to define a channel region by thermally diffusing the second conductivity type impurity introduced into the impurity introduction layer into the semiconductor substrate. Then, a gate insulating film is formed over the channel region and the impurity-doped layer, and a floating gate electrode is formed over the channel region so as to ride on the impurity-doped layer. A control gate electrode is formed on the floating gate electrode via an interlayer insulating film.

[0029]

In the nonvolatile semiconductor memory device according to the present invention, a gate bird's beak is formed in a region between an impurity introduction layer and a part of a floating gate electrode formed so as to ride on the impurity introduction layer. Will be. The ends of the pair of second conductivity type impurity regions serving as the source / drain regions are located closer to the channel region than the ends of the impurity introduction layers. Thereby,
The thickness of the gate insulating film located on the end of the impurity region in the vicinity of the surface of the semiconductor substrate becomes substantially uniform. That is, the thickness of the gate insulating film in the portion where the writing and erasing operations are performed becomes substantially uniform. Thus, the writing and erasing operations can be performed stably.

According to the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a pair of impurity regions is formed by thermally diffusing a second conductivity type impurity introduced into an impurity introduction layer into a semiconductor substrate. ing. Therefore, the impurity region can be formed such that the end portion of the impurity region is located below a portion of the gate insulating film having a substantially uniform thickness. This makes it possible to more reliably improve the performance of the nonvolatile semiconductor memory device.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view showing a flash memory according to a first embodiment of the present invention. FIG. 2 is a partial cross-sectional view of the memory cell array of the flash memory according to the present embodiment, and is a cross-sectional view corresponding to FIG. 32 shown in the conventional example. FIG. 3 is an enlarged cross-sectional view illustrating a memory transistor according to the present embodiment.

First, referring to FIG. 2, a plurality of memory transistors are formed in a memory cell array. p
Source diffusion region 6 and drain diffusion region 7 are formed on the main surface of mold semiconductor substrate 1 at intervals so as to define a channel region. On the surface of p-type semiconductor substrate 1, impurity introduction layers 21 are formed at intervals. In this embodiment, the material of the impurity introduction layer 21 is polycrystalline silicon. This impurity introduction layer 21
Are located farther from the channel region than the ends of the source diffusion region 6 and the drain diffusion region 7.

On the channel region, a floating gate electrode 3 is formed with a gate insulating film 2 interposed. At this time, the end of the floating gate electrode 3 is formed so as to ride on a part of the impurity introduction layer 21. ONO on the floating gate electrode 3
An interlayer insulating film 4 made of a film or the like is formed. On this interlayer insulating film 4, a control gate electrode 5 is formed.

An oxide film 8 is formed to cover control gate electrode 5 and floating gate electrode 3. A smooth coat film 9 is formed on oxide film 8, and contact hole 12 is formed at a predetermined position in smooth coat film 9. At this time, the impurity introduction layer 21 located under the contact hole 12 has been removed. The bit line 11 is formed on the inner surface of the contact hole 12 and on the smooth coat film 9.

Next, the structure of the memory transistor in this embodiment will be described in more detail with reference to FIGS. First, referring to FIG.
The end of the drain diffusion region 7 in the vicinity of the surface of the p-type semiconductor substrate 101 is formed such that the gate insulating film 2 under the floating gate electrode 3 has a substantially uniform thickness. Thus, the writing operation and the erasing operation of the memory transistor are performed stably.

At this time, both ends of the floating gate electrode 3 are formed so as to ride on the impurity introduction layer 21. As shown in FIG. 1, a gate bird's beak 1 is located near the end of the floating gate electrode 3.
0 is formed. The width of the floating gate electrode 3 riding on the impurity introduction layer 21 is adjusted to be larger than the width of the gate bird's beak 10. Therefore, even if the gate bird's beak 10 is formed, the gate bird's beak 10 exists only between the vicinity of the end of the floating gate electrode 3 and the impurity introduction layer 21, and the gate bird's beak 1 is located further inside.
No zero is formed. Therefore,
The thickness of the gate insulating film 2 located on the end of the source diffusion region 6 and the drain diffusion region 7 near the surface of the p-type semiconductor substrate becomes substantially uniform.

Next, referring to FIG. 3, the channel region width W1 of the memory transistor in this embodiment is 0.5 μm.
m, and the distance W2 between the impurity-doped layers 21 is
It is a value larger by a predetermined amount than W1. This value is determined in consideration of the thermal diffusion conditions of the source diffusion region 6 and the drain diffusion region 7, and the like. The width W4 at which both end portions of the floating gate electrode 3 ride on the impurity introduction layer 21 is about 0.2 μm. Thus, in this case, the width W3 of the floating gate electrode 3 has a value of about 0.9 μm.

The value of the raised width W4 of the floating gate electrode 3 on the impurity introduction layer 21 is determined so as to be greater than the width of the gate bird's beak 10 in the flash memory forming process. Therefore, the value of W4 is not limited to the above value. In addition,
Each of the above dimension values shows an example, and is not limited to each of the above dimensions.

The memory transistor according to the present invention has the above-described structure, so that electrons are injected during writing (indicated by (1) in the figure) and electrons are extracted during erasing ((2) in FIG. 2). (Indicated by (1)), the vicinity of the end of the drain diffusion region 7 and the vicinity of the end of the source diffusion region 6 and the gate bird's beak 10 are separated from each other. As a result, the injection and extraction of electrons are performed only in portions where the thickness of the gate insulating film 2 (in this case, about 100 °) is substantially uniform. Therefore,
The erase characteristics do not depend on the state of the gate bird's beak 10, and a memory transistor having stable write / erase characteristics can be obtained.

Further, since floating gate electrode 3 is formed so as to ride on impurity introduction layer 21, floating gate electrode 3 and control gate electrode 5
Step occurs on the surface of Therefore, the capacitance of the capacitor having the floating gate electrode 3 and the control gate electrode 5 as electrodes is increased, and the writing characteristics of the memory transistor can be improved. This will be described with reference to FIG. FIG. 4 is a conceptual diagram schematically showing virtual capacitors C1 and C2 formed in the memory transistor.

Referring to FIG. 4, during a write operation to a memory transistor, voltage Vg applied to control gate electrode 5 is controlled by a capacitor formed of control gate electrode 5, interlayer insulating film 4, and floating gate electrode 3. The capacitance is divided by C1 and a capacitor C2 including the floating gate electrode 3, the gate insulating film 2, and the p-type semiconductor substrate 1. As a result, the voltage Vg applied to the control gate electrode 4 is reduced by the above-described capacitor C1
And the capacitor C2 at a ratio of V1 and V2, respectively. It is the voltage V2 distributed to the capacitor C2 that determines the write efficiency during the write operation. That is, as the voltage V2 increases, electrons generated in the vicinity of the drain diffusion region 7 and the gate insulating film 2 due to the avalanche breakdown are more easily injected into the floating gate electrode 3. V2 at this time is given by the following equation.

[0042]

(Equation 1)

In the above formula 1, Vg indicates the voltage applied to the control gate electrode 5, and c1 and c2 indicate the capacitances of the capacitors, respectively. From the above formula 1, the capacitor C formed by the control gate electrode 5, the interlayer insulating film 4, and the floating gate electrode 3
The larger the capacity c1 of one is, the larger V2 can be obtained. Thereby, it is possible to improve the writing characteristics.

Next, a method of manufacturing a flash memory according to this embodiment will be described with reference to FIGS.
5 to 12 are sectional views showing first to eighth steps of the manufacturing process of the flash memory according to the present embodiment.

First, referring to FIG. 5, a polycrystalline silicon film having a thickness of about 100 ° is formed on p-type semiconductor substrate 1 by using a CVD (Chemical Vapor Deposition) method. Then, impurities such as arsenic (As) are introduced into the polycrystalline silicon film by an ion implantation method. At this time, the amount of impurity introduced into the polycrystalline silicon film is preferably about 1 to 10 × 10 ¹⁵ (cm ⁻² ). At this time, when introducing impurities into the polycrystalline silicon film, the acceleration voltage at the time of ion implantation is suppressed to about 50 KeV so that the impurities do not reach the p-type semiconductor substrate 1 through the polycrystalline silicon film. Thereby, impurity introduction layer 21 is formed.

Next, referring to FIG.
A resist 41 is applied thereon, and the resist 41 is patterned into a desired shape. Then, by performing dry etching using the resist 41 as a mask,
The impurity introduction layer 21 is patterned into a desired shape. The etching conditions at this time are set such that the etching of the p-type semiconductor substrate 1 by the etching of the impurity introduction layer 21 can be prevented as much as possible.

Next, as shown in FIG. 7, after removing the above-mentioned resist 41, at a temperature of about 1100.degree.
A heat treatment is performed for about 60 minutes to diffuse the impurities in the impurity introduction layer 21 into the p-type semiconductor substrate 1. At this time, the source diffusion region 6 and the drain diffusion region 7 are formed. At this time, the positions of the ends of the source diffusion region 6 and the drain diffusion region 7 can be arbitrarily set according to the heat treatment conditions. Thereby, the degree of freedom for forming source diffusion region 6 and drain diffusion region 7 is increased.

As another method of forming the source diffusion region 6 and the drain diffusion region 7 so as to have an end portion below the floating gate electrode 3, an oblique rotation ion implantation method performed after the formation of the electrode can be considered. However, when this oblique rotation ion implantation method is used, there are restrictions due to the implantation depth of impurities, restrictions due to the shadow effect due to the stacked structure of the floating gate electrode 3 and the control gate electrode 5, and the like. Thus, it can be said that there is a restriction on the position control of the ends of the source diffusion region 6 and the drain diffusion region 7. In a nonvolatile semiconductor device such as an EPROM and a flash memory, it is important to control the electric field distribution generated in the vicinity of the drain diffusion region 7 and the floating gate electrode 3 by controlling the profile of the impurity diffusion layer for controlling the writing characteristics. I can say. Therefore, it can be said that increasing the degree of freedom in forming the drain diffusion region 7 and the like as in the present embodiment is effective in improving the performance of the nonvolatile semiconductor device.

After the source diffusion region 6 and the drain diffusion region 7 are formed through the above steps, as shown in FIG.
A gate insulating film 2 having a thickness of about 0 ° is formed by performing a thermal oxidation process. At this time, since the impurity is introduced into the impurity introduction layer 21, oxidation is promoted thereon. Therefore, an oxide film having a thickness of about 300 ° is formed on impurity introduction layer 21. The thickness of the oxide film at this time varies depending on the concentration of the impurity introduced into the impurity introduction layer 21 or the condition of thermal oxidation.

Next, referring to FIG. 9, a polycrystalline silicon film 3 having a thickness of about 2000.degree. To become floating gate electrode 3 is formed on gate insulating film 2 by using a CVD method or the like. Then, a film thickness of about 300 ° is formed on the polycrystalline silicon film 3 by using a CVD method or the like.
An interlayer insulating film 4 made of an ONO film or the like is formed. On this interlayer insulating film 4, a polycrystalline silicon film 5 having a thickness of about 3000.degree. Serving as a control gate electrode 5 is formed by a CVD method or the like.

Thereafter, as shown in FIG. 10, a resist 42 is applied on the polysilicon film 5, and the resist 4
2 is patterned into a desired shape. Then, the gate insulating film 2, the floating gate electrode 3, the interlayer insulating film 4, and the control gate electrode 5 are patterned into desired shapes by performing dry etching using the resist 42 as a mask. Thereby, a memory transistor is formed.

Next, as shown in FIG. 11, after the resist 42 is released, the memory transistor is covered with an oxide film 8 by performing a thermal oxidation process. Then, as shown in FIG. 12, a smooth coat film 9 is formed by using a CVD method or the like so as to cover oxide film 8. Thereafter, in order to improve the flatness of the surface of the smooth coat film 9, an oxidation treatment is performed at a temperature of about 900.degree. At this time, oxidation progresses also at the end of the floating gate electrode 3 and the end of the control gate electrode 5, and a gate bird's beak 10 is formed.

However, at this time, in this embodiment,
The width of the floating gate electrode 3 riding on the impurity introduction layer 21 is set so as to be larger than the formation width of the gate bird's beak 10. Therefore, even if the gate bird's beak 10 is formed, only the gate bird's beak 10 exists within a range in which the floating gate electrode 3 rises on the impurity-doped layer 21. Therefore, it can be said that the gate bird's beak 10 does not affect the thickness of the gate insulating film 2 on the end portions of the source diffusion region 6 and the drain diffusion region 7 near the p-type semiconductor substrate surface.

Thus, the end portions of the source diffusion region 6 and the drain diffusion region 7 are located under the gate insulating film 2 having a substantially uniform thickness. for that reason,
Writing and erasing operations can be performed stably. As described above, after the smooth coat film 9 is formed, the smooth coat film 9 is formed on the smooth coat film 9 by sputtering or the like.
An aluminum film having a thickness of about 00 ° is formed.
Then, using photomechanical technology and etching technology,
The bit line 11 is formed by patterning this aluminum film into a desired shape.

In the above embodiment, the source diffusion region 6 and the drain diffusion region 7 are formed to have the same structure. However, in a flash memory, writing is performed by channel hot electron injection from the drain diffusion region 7 side, and erasing uses a phenomenon different from extracting electrons by an FN tunnel current. Therefore, in order to optimize the respective phenomena, it may be required to separately form the drain diffusion region 7 and the source diffusion region 6 into different structures (for example, by changing the impurity concentration). In such a case, by separately forming the drain diffusion region 7 and the source diffusion region 6, different structures can be obtained. An embodiment in which the source diffusion region 6 and the drain diffusion region 7 are separately formed will be described below.

First, a second embodiment according to the present invention for independently controlling the impurity concentrations of the source diffusion region 6 and the drain diffusion region 7 will be described with reference to FIGS. 13 to 16 are sectional views showing first to fourth steps of the manufacturing process of the flash memory according to the present embodiment.

First, referring to FIG. 13, an impurity introduction layer 21 serving as a diffusion source is formed on p-type semiconductor substrate 1 through the same steps as in the above embodiment. Then, the impurity introduction layer 21 is patterned into a desired shape using the resist 41 patterned into a predetermined shape as a mask. After that, the resist 41 is removed.

Thereafter, as shown in FIG. 14, a resist 43 is applied on the entire surface of the p-type semiconductor substrate 1, and the impurity introduction layer 2 located on the region where the drain diffusion region 7 is formed is formed.
Then, patterning is performed so as to expose 1. Then, using this patterned resist 43 as a mask, for example, arsenic (As) ions are deposited at 6 × 10 ¹⁵ cm ⁻² ,
The injection is performed under the condition of 50 KeV. Then, the resist 43 is removed.

Next, referring to FIG. 15, a resist 44 is formed so as to expose impurity introduction layer 21 located on the source diffusion region 6 formation region. Using this resist 44 as a mask, arsenic (As) ions are
It is implanted into the impurity introduction layer 21 under the conditions of 10 ¹⁵ cm ⁻² and 50 KeV. After that, the resist 44 is removed.

Next, as shown in FIG.
By performing a heat treatment at a temperature of about several degrees C. for several hours, the impurities introduced into the impurity introduction layer 21 are diffused into the p-type semiconductor substrate 1. As a result, a source diffusion region 6 and a drain diffusion region 7 are formed. At this time, since the impurity concentrations introduced into the impurity introduction layers 21 located on the source diffusion region 6 and the drain diffusion region 7 are different, the impurity concentrations of the source diffusion region 6 and the drain diffusion region 7 are also different. Thus, a flash memory having an impurity concentration suitable for operations such as writing and erasing can be formed. That is, a high-performance flash memory can be formed.

After the source diffusion region 6 and the drain diffusion region 7 are formed in this way, a flash memory is formed through the same steps as in the first embodiment.

Next, a third embodiment according to the present invention will be described with reference to FIGS. This embodiment is an embodiment in which the impurity diffusion depths of the source diffusion region 6 and the drain diffusion region 7 are independently controlled. In the same manner as the method described in the second embodiment, an impurity is first introduced into the impurity introduction layer 21 on the source diffusion region 6 side, and a first heat treatment is performed.

Thereafter, in the same manner as in the second embodiment described above, impurities are introduced into the impurity introduction layer 21 on the drain diffusion region 7 side, and a second heat treatment is performed. Thereby, the impurity on the source diffusion region 6 side is driven deep by the two heat treatments, and the impurity on the drain diffusion region 7 side is driven by only one heat treatment, so that the impurity is driven shallower than the source diffusion region 6 side. Thus, it becomes possible to form the source diffusion region 6 and the drain diffusion region 7 having different depths. Thereby, it is possible to obtain an optimum impurity profile of the source diffusion region 6 and the drain diffusion region 7 so as to improve the performance of the memory transistor.

After the source diffusion region 6 and the drain diffusion region 7 are formed through the above steps, a flash memory is formed through the same steps as in the first embodiment.

Next, a fourth embodiment according to the present invention will be described with reference to FIGS. 19 to 24
FIG. 14 is a sectional view showing first to sixth steps of a method for manufacturing a flash memory according to a fourth embodiment of the present invention.

Referring to FIG. 19, after the impurity introduction layer 21 is formed through the same steps as in the second embodiment, a resist 45 is formed on the impurity introduction layer 21 located on the drain diffusion region 7 side. I do. Then, the impurity introduction layer 21 is patterned using the resist 45 as a mask.
Thereafter, as shown in FIG. 20, a resist 46 is formed so as to expose the impurity introduction layer 21. Using the resist 46 as a mask, arsenic (As) ions are implanted into the impurity-doped layer 21 under the conditions of 6 × 10 ¹⁵ cm ⁻² and 50 KeV.

Thereafter, as shown in FIG.
A heat treatment of about several hours at 0 ° C.
Is diffused into the p-type semiconductor substrate 1. Thus, a drain diffusion region 7 is formed. Next, as shown in FIG.
A gate insulating film 2 having a thickness of about 0 ° is formed. Then, a polycrystalline silicon film 3 serving as a floating gate electrode 3, an interlayer insulating film 4, and a polycrystalline silicon film 5 serving as a control gate electrode 5 are formed on the gate insulating film 2 in the same manner as in the first embodiment. Form sequentially. And
As shown in FIG. 23, patterning into a desired shape is performed using a photolithography technique and a dry etching technique.

Thereafter, as shown in FIG. 24, a resist 47 is formed so as to cover drain diffusion region 7, and arsenic (As) ions are implanted at 4 × 10 ¹⁵ cm ⁻² using resist 47 as a mask. , 50 KeV. Then, the resist 47 is removed.
Activate by performing heat treatment for about 0 minutes. Thereby, source diffusion region 6 is formed. After the memory transistor is formed as described above, a flash memory is formed through the same steps as in the first embodiment.

In this embodiment, only one of the source diffusion region 6 and the drain diffusion region 7 is formed by thermal diffusion, and the other is formed by ion implantation.
When both the source diffusion region 6 and the drain diffusion region 7 are formed by thermal diffusion, it is not inconceivable that the effective channel length becomes short. Therefore, such a problem that the effective channel length is shortened by forming one by ion implantation as in the present embodiment is avoided.

Next, a fifth embodiment according to the present invention will be described with reference to FIGS. In this embodiment, an LDD (Lightly Doped Drain) structure is used as the structure of the source diffusion region 6 and the drain diffusion region 7. 25 to 29 are cross-sectional views showing first to fifth steps of the manufacturing process of the flash memory according to the present embodiment.

First, referring to FIG. 25, p-type semiconductor substrate 1
An impurity introduction layer 21 is formed thereon by using a CVD method or the like. Then, phosphorus (P) ions were added to 1 × 10 ¹⁴ cm ^−2,3
The impurity is introduced into the impurity introduction layer 21 under the condition of 0 KeV. Thereafter, as shown in FIG. 26, a resist 48 patterned into a predetermined shape is formed on the impurity introduction layer 21 and the impurity introduction layer 21 is formed using the resist 48 as a mask.
Is patterned into a predetermined shape. And resist 48
Is removed, heat treatment is performed at 1100.degree. C. for about 2 hours to form regions serving as low concentration impurity regions of the source diffusion region 6 and the drain diffusion region 7. Next, as shown in FIG. Thereafter, a gate insulating film 2, a floating gate electrode 3, an interlayer insulating film 4, and a control gate electrode 5 are formed in the same manner as in the first embodiment. Then, by patterning them into a predetermined shape, the shape shown in FIG. 28 is obtained. At this time, the impurity introduction layer 21 is simultaneously patterned.

Thereafter, as shown in FIG. 29, arsenic (A) is formed using control gate electrode 5 as a mask.
s) is implanted under the conditions of 50 KeV and 4 × 10 ¹⁵ cm ⁻² . Thus, high-concentration impurity regions of source diffusion region 6 and drain diffusion region 7 are formed.

As described above, the LDD is formed in the source diffusion region 6 and the drain diffusion region 7 in the memory transistor.
By using the structure, the withstand voltage between the source and the drain of the memory transistor can be improved. In this embodiment, when forming the memory transistor, the impurity introduction layer 21 serving as an impurity diffusion source is also removed by etching at the same time. However, the source diffusion region 6 and the drain diffusion region 7 may be formed by performing ion implantation through the impurity introduction layer 21 while leaving the impurity introduction layer 21.

As described above, in each of the above embodiments, the polycrystalline silicon film was used as the impurity diffusion source. However, instead of this polysilicon film, PSG
(Phospho Silicate Glass) or another insulating material containing impurities may be used.

[0075]

As described above, according to the present invention,
During the oxidation process after the formation of the floating gate electrode and the control gate electrode, the position of the gate bird's beak generated at the ends of the floating gate electrode and the control gate electrode and the location where electrons move during the write / erase operation are located. It becomes possible to separate. Thus, the writing and erasing operations are performed through the gate insulating film having a substantially uniform film thickness. as a result,
A nonvolatile semiconductor memory device capable of performing a stable writing / erasing operation can be obtained. In addition, since the floating gate electrode is formed so as to rise on the impurity introduction layer, the surface area of the floating gate electrode can be increased. Thereby, the capacitance between the floating gate electrode and the control gate electrode can be increased. As a result, the writing characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a flash memory according to a first embodiment of the present invention.

FIG. 2 is a partial sectional view of a memory cell array in the flash memory according to the first embodiment of the present invention.

FIG. 3 is an enlarged sectional view of a memory transistor in the flash memory according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a case where voltages applied to a control gate electrode in a memory transistor are virtual capacitors C1 and C
FIG. 4 is a conceptual diagram showing a state where the image is divided into two.

FIG. 5 is a sectional view showing a first step in a manufacturing process of the first embodiment according to the present invention.

FIG. 6 is a sectional view showing a second step of the manufacturing process of the first embodiment according to the present invention.

FIG. 7 is a sectional view showing a third step of the manufacturing process of the first embodiment based on the present invention.

FIG. 8 is a sectional view showing a fourth step in the manufacturing process of the first embodiment according to the present invention.

FIG. 9 is a sectional view showing a fifth step of the manufacturing process of the first embodiment according to the present invention.

FIG. 10 is a sectional view showing a sixth step in the manufacturing process of the first embodiment according to the present invention.

FIG. 11 is a sectional view showing a seventh step of the manufacturing process of the first embodiment according to the present invention.

FIG. 12 is a sectional view showing an eighth step of the manufacturing process of the first embodiment according to the present invention.

FIG. 13 is a cross-sectional view showing a first step in the manufacturing process of the flash memory according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a second step in the manufacturing process of the flash memory in the second embodiment according to the present invention.

FIG. 15 is a sectional view showing a third step of the manufacturing process of the flash memory in the second embodiment according to the present invention;

FIG. 16 is a sectional view showing a fourth step in the manufacturing process of the flash memory according to the second embodiment of the present invention;

FIG. 17 is a sectional view showing a third step of the manufacturing process of the flash memory in the third embodiment according to the present invention;

FIG. 18 is a sectional view showing a fifth step of the manufacturing process of the flash memory in the third embodiment according to the present invention.

FIG. 19 is a sectional view showing a first step of a flash memory according to a fourth embodiment of the present invention.

FIG. 20 is a sectional view showing a second step of the flash memory in the fourth embodiment according to the present invention.

FIG. 21 is a sectional view showing a third step of the flash memory according to the fourth embodiment of the present invention.

FIG. 22 is a sectional view showing a fourth step of the flash memory in the fourth embodiment according to the present invention.

FIG. 23 is a sectional view showing a fifth step of the flash memory according to the fourth embodiment of the present invention.

FIG. 24 is a sectional view showing a sixth step of the flash memory in the fourth embodiment according to the present invention;

FIG. 25 is a cross-sectional view showing a first step of the manufacturing process of the flash memory in the fifth embodiment according to the present invention.

FIG. 26 is a sectional view showing a second step in the manufacturing process of the flash memory in the fifth embodiment according to the present invention.

FIG. 27 is a sectional view showing a third step of the manufacturing process of the flash memory in the fifth embodiment according to the present invention;

FIG. 28 is a sectional view showing a fourth step in the manufacturing process of the flash memory in the fifth embodiment according to the present invention;

FIG. 29 is a sectional view showing a fifth step of the manufacturing process of the flash memory in the fifth embodiment according to the present invention;

FIG. 30 is a block diagram showing a schematic configuration of a conventional flash memory.

FIG. 31 is an equivalent circuit diagram showing a schematic configuration of the memory cell array shown in FIG. 30;

FIG. 32 is a partial cross-sectional view of a memory cell array in a conventional flash memory.

FIG. 33 is an enlarged cross-sectional view of one memory transistor in a memory cell array.

FIG. 34 is a cross-sectional view showing a first step of a conventional flash memory manufacturing process.

FIG. 35 is a cross-sectional view showing a second step of the conventional flash memory manufacturing process.

FIG. 36 is a cross-sectional view showing a third step of the conventional flash memory manufacturing process.

FIG. 37 is a cross-sectional view showing a fourth step in the process of manufacturing the conventional flash memory.

FIG. 38 is a cross-sectional view showing a fifth step of the conventional flash memory manufacturing process.

FIG. 39 is a cross-sectional view showing a sixth step of the conventional flash memory manufacturing process.

FIG. 40 is a cross-sectional view showing a seventh step of the conventional flash memory manufacturing process.

FIG. 41 is a cross-sectional view showing an eighth step of the conventional flash memory manufacturing process.

FIG. 42 is a cross-sectional view showing a ninth step of the conventional flash memory manufacturing process.

FIG. 43 is a tenth step of a conventional flash memory manufacturing process.
It is sectional drawing which shows a process.

FIG. 44 shows an eleventh manufacturing process of a conventional flash memory.
It is sectional drawing which shows a process.

FIG. 45 is an explanatory diagram for describing a write and erase operation of a memory transistor in a conventional flash memory.

[Explanation of symbols]

 1,101 p-type semiconductor substrate 2,102 gate insulating film 3,103 floating gate electrode 4,104 interlayer insulating film 5,105 control gate electrode 6,106 source diffusion region 7,107 drain diffusion region 8,108 oxide film 9, 109 Smooth coat film 11, 111 Bit line 12, 112 Contact hole 21 Impurity introduction layer 110 Gate bird's beak

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788

Claims (2)

(57) [Claims] A semiconductor substrate of a first conductivity type having a main surface; a pair of impurity regions of a second conductivity type formed on the main surface of the semiconductor substrate so as to define a channel region; A pair of impurity introduction layers serving as diffusion sources for forming the impurity region, having an end portion at a position separated from the channel region and extending in a direction away from the channel region; A gate insulating film formed on the impurity-introducing layer and above the impurity-introducing layer; A nonvolatile semiconductor memory device comprising: a formed floating gate electrode; and a control gate electrode formed on the floating gate electrode via an interlayer insulating film. A step of forming, at a predetermined interval, an impurity-doped layer into which a second-conductivity-type impurity is introduced, on the first-conductivity-type semiconductor substrate having a main surface; Forming a pair of second conductivity type impurity regions to define a channel region by thermally diffusing a second conductivity type impurity into the semiconductor substrate; and forming a pair of second conductivity type impurity regions on the channel region and the impurity introduction layer. Forming a gate insulating film thereon; forming a floating gate electrode on the channel region so as to ride on the impurity-doped layer; and controlling the control gate electrode on the floating gate electrode via an interlayer insulating film. Forming a non-volatile semiconductor storage device.