JPH07202046A - Nonvolatile semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device and its manufacturing method wherein deterioration of memory cell characteristics can be restrained to be small. CONSTITUTION:A lamination structure of a floating gate 6, an insulating layer 7, and a control gate 8 is formed in a specified position on the main surface of a P-type semiconductor substrate 1. An insulating layer of about 100Angstrom in thickness is formed on the whole part of the main surface of the P-type semiconductor substrate 1, so as to cover the lamination structure. A resist pattern 17 which covers the forming region of the drain region of a memory transistor and exposes the forming region of the source region is formed on the insulating layer. By using the resist pattern 17 as a mask, the insulating layer, a gate insulating layer 5, and an element isolation dielectric layer are etched. Thereby a side wall insulating layer 9a is formed. In this state, N-type impurities are implanted in the main surface of the P-type semiconductor substrate 1, and the source region is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically writing and erasing, and a method of manufacturing the same, and more particularly, to a structure of a flash memory and improvement of a method of manufacturing the same. is there.

[0002]

2. Description of the Related Art A flash memory capable of freely writing data and electrically erasing written information charges has been known. FIG. 10 is a block diagram showing a general configuration of a flash memory. First, the schematic configuration of the flash memory will be described with reference to FIG.

Referring to FIG. 10, the flash memory is
A memory cell matrix 100 in which memory transistors arranged in rows and columns are formed, and an X address decoder 2
00, Y gate 300, and Y address decoder 400
An address buffer 500, a write circuit 600, a sense amplifier 700, an input / output buffer 800, and a control logic 900.

The memory cell matrix 100 has a plurality of memory transistors arranged in a matrix therein. An X address decoder 200 and a Y gate 300 are connected to the memory cell matrix 100 to select a row and a column of the memory cell matrix 100.

The Y gate 300 is connected to a Y address decoder 400 for providing column selection information. The X address decoder 200 and the Y address decoder 400 include
An address buffer 500 for temporarily storing address information is connected to each.

A write circuit 600 for performing a write operation at the time of data input and a sense amplifier 700 for determining "0" or "1" from the value of the current flowing at the time of data output are connected to Y gate 300. There is. An input / output buffer 800 for temporarily storing input / output data is connected to each of the writing circuit 600 and the sense amplifier 700.

A control logic 900 for controlling the operation of the flash memory is connected to the address buffer 500 and the input / output buffer 800. The control logic 900 performs control based on a chip enable signal, an output enable signal and a program signal.

FIG. 11 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG.
The internal structure of the memory cell matrix 100 will be described with reference to FIG.

With reference to FIG. 11, a plurality of word lines WL ₁ , WL ₂ , ..., WL _i extending in the row direction and a plurality of bit lines BL ₁ , BL ₂ , ..., BL _j extending in the column direction. And are arranged so as to be orthogonal to each other. At the intersections of the word lines and the bit lines, memory transistors Q11, Q12 ..., Qij each having a floating gate.
Are arranged.

The drain region of each memory transistor is
It is connected to each bit line. The source region of the memory transistor is connected to each source line S ₁ , S ₂ , ... The source regions of the memory transistors belonging to the same row are connected to each other as shown in FIG.

Next, the structure and operation of the conventional flash memory described above will be described in more detail with reference to FIGS. FIG. 12 is a partial plan view of a memory cell matrix of a flash memory. 13 is the same as FIG.
It is sectional drawing which follows the XIII-XIII line in. FIG. 14 is a cross-sectional view showing one memory transistor forming the flash memory.

First, referring to FIG. 12, a plurality of floating gates (charge storage electrodes) 106 (m × n) are arranged in a matrix of m rows and n columns. An element isolation region (field oxide film) 120 is formed between the adjacent columns of the floating gate 106. In addition, m control gates (word lines) are provided for each row on the floating gate 106.
108 is formed. On the control gate 108, n bit lines 116 formed for each column are formed. The bit line 116 and the drain region of each memory transistor are electrically connected via the plug electrode 115.

Next, referring to FIG. 13, memory transistors 104 are formed on the main surface of p-type semiconductor substrate 101 at predetermined intervals. Memory transistor 104 has an n-type source region 103 and a drain region 102 formed on the main surface of p-type semiconductor substrate 101.

The memory transistor 104 has a floating gate 106 formed on a region sandwiched between the source region 103 and the drain region 102 with a gate insulating layer 105 interposed, and the floating gate 106.
And a control gate 108 provided on the insulating layer 107. In this case, the insulating layer 107 includes the silicon oxide film 107a and the silicon nitride film 10a.
7b and a silicon oxide film 107c have a laminated structure.

An insulating layer 112 is formed so as to cover the side wall of each memory transistor 104. This insulating layer 11
An interlayer insulating layer 113 is formed so as to cover 2. The interlayer insulating layer 113 is provided with a contact hole 114 reaching the surface of the drain region 102.

A plug electrode 115 is formed in this contact hole 114. Bit line 116 is formed on plug electrode 115 and interlayer insulating layer 113. The bit line 116 is electrically connected to the drain region 102 of the memory transistor 104 via the plug electrode 115.

Next, the operation of the flash memory having the above structure will be described with reference to FIG.

Referring to FIG. 14, in the writing operation,
A voltage V _{D of} about 6 to 8 V is applied to the n-type drain region 102, and a voltage V _{G of} about 10 to 15 V is applied to the control gate 108. At this time, the n-type source region 1
03 and the p-type semiconductor substrate 101 are kept at the ground potential.

As a result, a current of several hundred μA flows in the channel region of the memory transistor. At this time, electrons flow from the source region 103 toward the drain region 102, and among the electrons, the electrons accelerated in the vicinity of the drain region 102 become channel hot electrons.

Some of these electrons are part of the control gate 1.
08 by the electric field due to the voltage V _G applied to
It is injected into the floating gate 106, as indicated by the arrow at. In this way, electrons are accumulated in the floating gate 106. This increases the threshold voltage V _th of the memory transistor. Thus, the threshold voltage V _th of the memory transistor is
Is written when the value is higher than the specified value,
It is called "0".

Next, the erase operation will be described. In the erase operation, a voltage V _{S of} about 10 to 12 V is applied to the source region 103, and the control gate 108 and the p-type semiconductor substrate 101 are kept at the ground potential. At this time,
The drain region 102 is opened.

By applying the voltage as described above to the source region 103, the electrons accumulated in the floating gate 106 pass through the thin gate insulating layer 105 by the tunnel phenomenon as shown by the arrow in FIG. To do.

As a result, the floating gate 106
The electrons inside are pulled out. As a result, the threshold voltage V _th of the memory transistor becomes low. A state in which the threshold voltage V _th of the memory transistor is lower than a predetermined value in this way is called an erased state, “1”. Since the source regions 103 of the respective memory transistors are connected to each other as shown in FIG. 11, all the memory cells can be collectively erased by this erase operation.

Next, the read operation will be described. At the time of reading, a voltage V _G ′ of about 5 V is applied to the control gate 108 and a voltage V _D ′ of about 1 to 2 V is applied to the drain region 10. At this time, the determination of "1" or "0" is made depending on whether or not a current flows in the channel region of the memory transistor, that is, whether the memory transistor is on or off.

As described above, the floating gate (charge storage electrode) 106 is surrounded by the insulating layer, and the electrons stored in the floating gate 106 are stored in the floating gate 106 for a long time unless a write or erase operation is performed. Retained. More specifically, 1
It is desired that electrons be retained in the floating gate 106 for a period of 0 years or more.

Next, a method of manufacturing the conventional flash memory having the above structure will be described with reference to FIGS. FIG. 15 is a plan view showing a first step in a conventional flash memory manufacturing process. FIG. 16 shows FIG.
6 is a cross-sectional view taken along line XVI-XVI in FIG. FIG. 17
FIG. 16 is a sectional view taken along line XVII-XVII in FIG. 15.

18 to 24 are cross-sectional views showing second to eighth steps of a conventional flash memory manufacturing process. 18 to 24, a cross section corresponding to FIG. 17 is shown.

First, referring to FIGS. 15 to 17, an element isolation insulating layer (field oxide film) 120 is formed on each of the columns on the main surface of p type silicon substrate 101. Next, an oxide film (gate insulating layer) 105 having a thickness of about 100 Å is formed on the active region on the main surface of p-type silicon substrate 101. A polycrystalline silicon layer 106 is deposited on the gate insulating layer 105 and the element isolation insulating layer 120. Then, a resist pattern 121 patterned into a predetermined shape is formed on the polycrystalline silicon layer 106.

By using this resist pattern 121 as a mask, anisotropic etching is performed to pattern polycrystalline silicon layer 106 into a predetermined shape. Then, the resist pattern 121 is removed.

Next, referring to FIG. 18, insulating layer 107 is formed on polycrystalline silicon layer 106. This insulating layer 1
07 has a three-layer structure. That is, the insulating layer 107
Is an oxide film 107a having a thickness of about 100Å, a nitride film 107b having a thickness of about 100Å formed on the oxide film 107a, and an oxide film 107c having a thickness of about 100Å formed on the nitride film 107b. Have.

The oxide films 107a and 107c are CV
It is formed by the D method or the thermal oxidation method. The nitride film 107b is formed by the CVD method or the like.

A polycrystalline silicon layer 1 having a thickness of about 2500 Å is formed on the oxide film 107c by using the CVD method or the like.
08 is formed. An insulating layer 111 is formed on the polycrystalline silicon layer 108. A resist pattern 122 patterned into a predetermined shape is formed on the insulating layer 111.

Then, using the resist pattern 122 as a mask, the insulating layer 111, the polycrystalline silicon layer 108, the insulating layer 107 and the polycrystalline silicon layer 106 are anisotropically etched. As a result, as shown in FIG. 19, the control gate 108 and the insulating layer 10 are formed.
7 and the floating gate 106 are formed. Then, the resist pattern 122 is removed.

Next, referring to FIG. 20, a p-type semiconductor substrate 101 in which the drain region of the memory transistor is formed.
A resist pattern 123 is formed so as to cover the region of the main surface of. Then, using this resist pattern 123 as a mask, anisotropic etching is applied to the gate insulating layer 105 and the element isolation insulating layer (not shown) located on the region where the source region of the memory transistor is formed.

Next, using the resist pattern 123 as a mask, the main surface of the p-type semiconductor substrate 101 is
An n-type impurity such as arsenic (As) is implanted. The condition is 3
It is 5 KeV and 1 × 10 ¹⁶ / cm ² . Then, by performing a diffusion process, an n-type impurity region (source region) 10 having a concentration of 1 × 10 ²¹ / cm ³ and a sheet resistance of 50Ω / □ is formed.
3 is formed.

Then, referring to FIG. 21, after removing the resist pattern 123, the source region 103 is covered and the drain region of the memory transistor is formed.
A resist pattern 124 exposing a region of the main surface of mold semiconductor substrate 101 is formed. This resist pattern 1
Using 24 as a mask, an n-type impurity such as arsenic (As) is implanted into the main surface of p-type semiconductor substrate 101. The conditions are 35 KeV and 5 × 10 ¹⁴ / cm ² . And
A concentration of 5 × 10 ¹⁹ / c is obtained by applying diffusion treatment.
An n-type impurity region (drain region) 102 having m ³ and a sheet resistance of 80Ω / □ is formed. Then, the resist pattern 124 is removed.

Then, referring to FIG. 22, an oxide film 112 is formed on the entire main surface of p type semiconductor substrate 101. Thereafter, this oxide film 112 is subjected to anisotropic etching treatment.
As a result, as shown in FIG. 23, the insulating layer 112 that covers the sidewall of the memory transistor is formed.

Then, referring to FIG. 24, an interlayer insulating layer 113 made of a TEOS layer or the like is formed on the entire main surface of the p-type semiconductor substrate 101. Then, after performing a wet reflow process at about 900 ° C. for about 30 minutes, an etch back process is performed. Then, as shown in FIG. 24, a resist pattern 126 patterned into a predetermined shape is formed on the interlayer insulating layer 113. This resist pattern 1
26 as a mask, the interlayer insulating layer 113, the insulating layer 1
12 is etched. As a result, the contact hole 114 is formed.

Thereafter, a plug electrode 115 made of a refractory metal such as tungsten (W) is formed in the contact hole 114. And the interlayer insulating layer 1
A bit line 116 is formed on 13 and on the plug electrode 115. Through the above steps, the conventional flash memory shown in FIG. 13 is formed.

Next, a modification of the structure of the conventional flash memory will be described with reference to FIG. In the conventional flash memory shown in FIG. 13, the bit line 11
6 and the drain region 102 were electrically connected via the plug electrode 115. However, as shown in FIG. 25, the bit line 1 is directly connected without using the plug electrode 115.
27 and the drain region 102 may be connected.

In order to obtain the structure shown in FIG. 25, an insulating layer 112 is deposited on the entire main surface of p type semiconductor substrate 101 as in the above case, and this insulating layer 112 is anisotropically etched. By doing so, a part of the surface of the drain region 102 is exposed. Then, a polycrystalline silicon layer (bit line) 127 is deposited on the entire main surface of p-type semiconductor substrate 101 and patterned into a predetermined shape. Thereby, the structure shown in FIG. 25 is obtained.

[0042]

However, the above-mentioned conventional flash memory has the following problems. The problem will be described with reference to FIG. FIG. 26 is a perspective view showing a state where the gate insulating layer 105 and the element isolation insulating layer 120 are removed on the region where the source region of the memory transistor is formed, using the resist pattern 123 as a mask.

When forming the source region 103, as described above, the thin gate insulating layer 105 and the thick element isolation insulating layer 1 located on the region where the source region 103 is formed.
20 and 20 were simultaneously subjected to anisotropic etching treatment. Thereby, as shown in FIG. 26, the p-type semiconductor substrate 1
On the main surface of 01, the element isolation insulating layer 120 formed on the formation region of the source region 103 is removed by etching to form the recess 118.

At this time, since the thickness of the element isolation insulating layer 120 is large, the above etching process is performed for a relatively long time. As a result, at the time of this etching, the floating gate 106, the insulating layer 107 between the floating gate 106 and the control gate 108, the gate insulating layer 105 between the floating gate 106 and the p-type semiconductor substrate 101, and the vicinity of the region for tunneling electrons P-type semiconductor substrate 101 located at
Etching damage enters each of the.

Further, at the time of implanting arsenic (As) for forming the source region 103 after the above-mentioned etching treatment, a problem that impurities or the like are implanted into a portion where etching damage has occurred and contaminated, or implanted ions The problem arises that the seed creates defects in each of the above insulating layers. There is a problem that the characteristics of the memory cell are deteriorated when the memory cell is completed due to the occurrence of the above phenomenon during the manufacturing process.

The present invention has been made to solve the above problems. An object of the present invention is to provide a non-volatile semiconductor memory device capable of effectively preventing deterioration of memory cell characteristics and a manufacturing method thereof.

[0047]

A nonvolatile semiconductor memory device according to the present invention includes a first conductivity type semiconductor substrate and a second conductivity type semiconductor substrate.
A conductive type source region and drain region, a floating gate, a control gate, and a sidewall insulating layer are provided. The source and drain regions are
The main surface of the semiconductor substrate is formed at intervals so as to define a channel region. The floating gate is formed on the channel region with the first insulating layer interposed. The control gate is formed on the floating gate with a second insulating layer interposed. The sidewall insulating layer covers at least the bottom of the side wall of the floating gate located on the source region side, and the height of the upper end of the sidewall insulating layer from the main surface of the semiconductor substrate is lower than the height of the upper surface of the control gate from the main surface of the semiconductor substrate. There is.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, first, element isolation is performed so as to define an active region in a predetermined region of the main surface of the first conductivity type semiconductor substrate in which a memory transistor is formed. An insulating layer is formed. Then, a first insulating layer is formed on the active region on the main surface of the semiconductor substrate. The floating gate of the memory transistor and the second gate of the memory transistor are formed on the insulating layer.
The insulating layer and the control gate of the memory transistor are sequentially formed. Then, a third insulating layer is formed on the entire main surface of the semiconductor substrate so as to cover the floating gate, the second insulating layer and the control gate. Then, a third region which covers the first region of the main surface of the semiconductor substrate in which the drain region of the memory transistor is formed and is located on the second region of the main surface of the semiconductor substrate in which the source region of the memory transistor is formed is formed. A mask layer exposing the surface of the insulating layer is formed. By using this mask layer as a mask, anisotropic etching is performed on the third insulating layer, the element isolation insulating layer located on the second region, and the first insulating layer, whereby the main surface of the semiconductor substrate is exposed. The area of 2 is exposed. Then, a source region and a drain region of the memory transistor are formed by introducing impurities of the second conductivity type into the first and second regions on the main surface of the semiconductor substrate.

[0049]

According to the nonvolatile semiconductor memory device of the present invention, the side wall insulating layer is formed to cover at least the side wall bottom of the floating gate on the source region side. This sidewall insulating layer is formed before forming the source region. As a result, when the second conductivity type impurity is injected into the main surface of the semiconductor substrate for forming the source region, the sidewall insulating layer protects the gate insulating layer of the memory transistor. As a result, it is possible to suppress the damage due to the implantation of impurities for forming the source region.

According to the method for manufacturing a nonvolatile semiconductor memory device in accordance with the present invention, in forming the source region, the element isolation insulating layer located on the second region of the main surface of the semiconductor substrate on which the source region is formed, When anisotropic etching is performed on the first insulating layer and the third insulating layer, the third insulating layer causes the control gate, the floating gate and the second insulating layer to move.
Covers the laminated structure with the insulating layer. As a result, even when the above anisotropic etching is performed, the time during which the etching gas directly contacts the second insulating layer or the floating gate, and further the first insulating layer located between the floating gate and the source region is suppressed to be short. It becomes possible. As a result, it becomes possible to suppress etching damage to a smaller level than in the past.

[0051]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view showing a sectional structure of a flash memory according to an embodiment of the present invention. First, the structure of the flash memory according to the present invention will be described with reference to FIG.

Referring to FIG. 1, the main difference between the structure of the flash memory according to the present invention and the structure of the conventional flash memory is that the side wall insulation of the memory transistor 4 located on the source region 3 side is provided. The point is that the layer 9a is formed and the insulating layer 9b is formed so as to cover the sidewall of the memory transistor 4 located on the drain region side. The sidewall insulating layer 9a and the insulating layer 9b described above
The material is preferably a silicon oxide film (SiO ₂ ),
It is a silicon nitride film (Si ₃ N ₄ ) or the like.

By providing the side wall insulating layer 9a as described above, the gate insulating layer 5 and the like located between the p-type semiconductor substrate 1 and the floating gate 6 are implanted at the time of impurity implantation for forming the source region 3. It is possible to effectively prevent damage.

Other than that, the structure is almost the same as the conventional example. That is, the memory transistor 4 is formed on the main surface of the p-type semiconductor substrate 1. The memory transistor 4 has an n-type source region 3 and an n-type drain region 2
A gate insulating layer 5 made of a silicon oxide film or the like, a floating gate 6 made of polycrystalline silicon or the like,
An insulating layer 7 and a control gate 8 made of polycrystalline silicon or the like are provided. The insulating layer 7 is composed of a silicon oxide film 7a, a silicon nitride film 7b, and a silicon oxide film 7c.
It has a three-layer structure consisting of

Then, the insulating layer 12 made of a silicon oxide film or the like is formed so as to cover the entire sidewall of the memory transistor. Then, an interlayer insulating layer 13 made of TEOS or the like is formed so as to cover the insulating layer 12. A contact hole 14 is provided in the interlayer insulating layer 13 at a portion located on the drain region 2. A plug electrode 15 made of tungsten (W) or the like is formed in the contact hole 14. On the plug electrode 15 and the interlayer insulating layer 13
A bit line 16 made of polycrystalline silicon or the like is formed on the top.

Next, a method of manufacturing the flash memory according to the present invention shown in FIG. 1 will be described with reference to FIGS. 2 to 5 are cross-sectional views showing first to fourth steps of the manufacturing process of the flash memory according to the present invention. FIG. 6 is a view showing a cross section different from the cross section shown in FIG. 5 in the fourth step. 7 and 8 are sectional views showing a fifth step and a sixth step of the flash memory according to the present invention. FIG. 9 is a cross-sectional view showing a characteristic process of a modification of the manufacturing process shown in FIGS. In addition,
2 to 9, for convenience, there are some components for which reference numerals are omitted.

First, referring to FIG. 2, the gate insulating layer 5, the floating gate 6, and the insulating layers 7 (7a, 7a, 7a, 7) are formed on the main surface of the p-type semiconductor substrate 1 through the same steps as in the conventional example.
b, 7c), the control gate 8 and the insulating layer 11 are laminated.

Next, referring to FIG. 3, p-type semiconductor substrate 1
An insulating layer 9 is formed on the entire main surface of the substrate by the CVD method or the thermal oxidation method. The thickness of the insulating layer 9 is preferably about 100Å. The material of the insulating layer 9 may be a silicon oxide film (SiO ₂ ), a silicon oxide film (Si ₃ N ₄ ) or a composite film thereof. The silicon nitride film is preferably formed by CVD.

Next, referring to FIG. 4, a resist pattern that covers the region where the drain region of the memory transistor is formed and exposes the surface of the insulating layer 9 located on the region where the source region of the memory transistor is formed. 17, p
It is formed on the main surface of the type semiconductor substrate 1.

Next, referring to FIG. 5, anisotropic etching is performed using the resist pattern 17 as a mask. As a result, the insulating layer 9, the gate insulating layer 5 located on the region where the source region is formed, and the element isolation insulating layer (not shown) made of a silicon oxide film located on the region where the source region is formed (not shown). ) And are simultaneously etched.

As a result, the sidewall insulating layer 9a is formed and, as shown in FIG. 6, the recess 18 is formed in the main surface of the p-type semiconductor substrate 1 where the element isolation insulating layer was formed. It will be.

At this time, since a predetermined portion of the element isolation insulating layer is also removed by etching, a relatively long anisotropic etching process is performed. As a result, the sidewall insulating layer 9a is also etched in the height direction, and the height h of the upper end of the sidewall insulating layer 9a from the main surface of the p-type semiconductor substrate 1 is higher than that of the upper surface of the control gate 8 from the main surface of the p-type semiconductor substrate 1. Height h1
Will be lower than.

However, since the insulating layer 9 is provided during the above anisotropic etching, the etching gas is formed on the main surface of the p-type semiconductor substrate at least in the region for tunneling electrons (tunnel region) and in the vicinity of the region. Can be prevented from touching directly. Further, the time for the side walls of the control gate 8, the insulating layer 7, and the floating gate 6 to directly contact the etching gas can be shortened as compared with the conventional example. As a result, it becomes possible to effectively prevent the deterioration of the characteristics of the memory cell as in the conventional case.

The thickness W of the sidewall insulating layer 9a is
Is about 100Å. Further, in FIG. 5, the upper end portion of the sidewall insulating layer 9a is located below the insulating layer 7, but it is preferable to leave the sidewall 9a so as to cover the insulating layer 7 and the control gate 8. As a result, more parts can be protected, and etching damage can be further suppressed.

Further, the material of the element isolation insulating layer and the insulating layer 9
When the material of the element isolation insulating layer is SiO ₂ and the material of the insulating layer 9 is Si ₃ N ₄ , the etching conditions are appropriately selected to make the insulating layer 9 The position of the upper end of the sidewall insulating layer 9a can be made higher than in the case where SiO ₂ is selected as the material. As a result, etching damage can be further suppressed.

Next, referring to FIG. 7, using resist pattern 17 as a mask again, n-type impurities such as arsenic (As) and phosphorus (P) are applied to the main surface of p-type semiconductor substrate 1. inject. The implantation conditions are the same as in the conventional example. Then, the source region 3 is formed by performing the same diffusion process as in the conventional example. As a result, the impurity concentration is 1 × 10
^The n-type source region 3 of ²¹ / cm ³ and sheet resistance of 50Ω / □ is formed. At this time, the insulating layer 9
By setting the thickness to 100 Å as described above, the width of the sidewall insulating layer 9a protruding to the source region 3 side can be suppressed to be small, and the formation region of the source region 3 can be secured.

At this time, the sidewall insulating layer 9
By forming a, it is possible to suppress damage to the tunnel region due to the implantation of the n-type impurity. Thereby, it is possible to effectively prevent the adverse effect on the memory transistor due to the impurity implantation for forming the source region 3. Then, the resist pattern 17
To remove.

Next, referring to FIG. 8, the source region 3 is covered.
Of the insulating layer 9 located on the drain region forming region.
The resist pattern 19 exposing the surface is formed by a p-type semiconductor.
It is formed on the main surface of the substrate 1. And this resist pattern
Turn 19 is used as a mask to remove arsenic (As)
N-type impurities are implanted into the main surface of p-type semiconductor substrate 1. This
In this case, the injection conditions are the same as in the conventional example. By that
Impurity concentration 5 × 10 ¹⁹/ Cm³, Sheet resistance 80Ω
An n-type drain region 2 made of / □ is formed. That
After that, the resist pattern 19 is removed.

After that, the insulating layer 12, the interlayer insulating layer 13, the contact hole 14, the plug electrode 15 and the bit line 16 are formed through the same steps as in the conventional example.
As a result, the flash memory shown in FIG. 1 is formed.

Next, a modification of the method of forming the source / drain regions 3 and 2 will be described with reference to FIG. In the above manufacturing method, the source region 3 and the drain region 2 are formed in separate steps. Therefore, the drain region 2 and the source region 3 could be formed so as to have the optimum concentration required. However, since they are formed in separate steps, there is a problem that the manufacturing process becomes complicated. This modification is devised to solve the problem that the manufacturing process becomes complicated. Note that this modification should be applied to a flash memory in which the source / drain regions 3 and 2 may have the same concentration.

Referring to FIG. 5, resist pattern 17 is removed after the above anisotropic etching treatment is performed at this stage. Thereby, the structure shown in FIG. 9 is obtained. Then, as shown in FIG. 9, an n-type impurity such as arsenic (As) is implanted into the main surface of p-type semiconductor substrate 1.
The implantation conditions are 30 keV and 4 × 10 ¹⁵ / cm ² .

Then, the source region 3 and the drain region 2 are formed in the same step by performing a predetermined diffusion process. Thereby, the manufacturing process can be simplified as compared with the case of the above manufacturing method. The present invention is also applicable to the structure shown in FIG.

[0073]

As described above, according to the present invention, by having the third insulating layer, the element isolation insulating layer located on the source region forming region is removed by etching when the source region is formed. In this case, etching damage to the memory transistor can be suppressed to be small. In addition, by including the sidewall insulating layer, damage to the memory transistor due to the implantation of impurities for forming the source region can be suppressed to be small. As a result, it becomes possible to stably form a memory cell having good characteristics.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a flash memory in an embodiment according to the present invention.

FIG. 2 is a sectional view showing a first step of manufacturing steps of the flash memory according to the embodiment of the present invention.

FIG. 3 is a sectional view showing a second step of manufacturing the flash memory in one embodiment according to the present invention.

FIG. 4 is a sectional view showing a third step of manufacturing the flash memory in one embodiment according to the present invention.

FIG. 5 is a cross-sectional view showing a fourth step of manufacturing the flash memory in one embodiment according to the present invention.

FIG. 6 is a cross-sectional view showing a cross-section different from the cross-section shown in FIG. 5 in the fourth step of the manufacturing steps of the flash memory according to the embodiment of the present invention.

FIG. 7 is a cross sectional view showing a fifth step of manufacturing the flash memory in one embodiment according to the present invention.

FIG. 8 is a sectional view showing a sixth step of manufacturing the flash memory in one embodiment based on the present invention.

FIG. 9 is a cross-sectional view showing a modified example of the method for forming the source / drain regions.

FIG. 10 is a block diagram showing a schematic configuration of a conventional flash memory.

FIG. 11 is an equivalent circuit diagram showing a schematic configuration of a memory cell matrix in a conventional flash memory.

FIG. 12 is a partial plan view of a conventional flash memory.

13 is a sectional view taken along line XIII-XIII in FIG.

FIG. 14 is a cross-sectional view showing one memory transistor.

FIG. 15 is a plan view showing a first step of manufacturing steps of the conventional flash memory.

16 is a cross-sectional view taken along line XVI-XVI in FIG.

17 is a sectional view taken along line XVII-XVII in FIG.

FIG. 18 is a sectional view showing a second step of the conventional manufacturing steps of the flash memory.

FIG. 19 is a cross-sectional view showing a third step of the conventional flash memory manufacturing steps.

FIG. 20 is a cross-sectional view showing a fourth step of the conventional flash memory manufacturing steps.

FIG. 21 is a cross-sectional view showing a fifth step of the conventional flash memory manufacturing steps.

FIG. 22 is a cross-sectional view showing a sixth step of the conventional flash memory manufacturing steps.

FIG. 23 is a cross-sectional view showing a seventh step of the conventional flash memory manufacturing steps.

FIG. 24 is a cross-sectional view showing an eighth step of the manufacturing process of the conventional flash memory.

FIG. 25 is a cross-sectional view showing another structural example of the conventional flash memory.

FIG. 26 is a perspective view for explaining a problem in a conventional flash memory.

[Explanation of symbols]

1, 101 p-type semiconductor substrate 2, 102 drain region 3, 103 source region 4, 104 memory transistor 5, 105 gate insulating layer 6, 106 floating gate 7, 107 insulating layer 8, 108 control gate 9 insulating layer 9a sidewall insulating Layer 9b Insulating layer 11,12,111,112 Insulating layer 13,113 Interlayer insulating layer 14,114 Contact hole 15,115 Plug electrode 16,116 Bit line 17,19,121,122,123,124,126
Resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (10)

[Claims] 1. A first-conductivity-type semiconductor substrate having a main surface, and a second-conductivity-type source region and drain region formed on the main surface of the semiconductor substrate at intervals so as to define a channel region. A floating gate formed on the channel region with a first insulating layer interposed therebetween, a control gate formed on the floating gate with a second insulating layer interposed, and located on the source region side. A sidewall insulating layer that covers at least the bottom of the side wall of the floating gate, and the height of the upper end of the floating gate from the main surface of the semiconductor substrate is lower than the height of the upper surface of the control gate from the main surface of the semiconductor substrate. Non-volatile semiconductor memory device. 2. A second sidewall insulation layer is formed so as to cover the sidewall insulation layer, both side walls of the control gate and both side walls of the floating gate, and to cover the second side wall insulation layer. An interlayer insulating layer is formed on the drain region, and a contact hole penetrating the interlayer insulating layer and the second sidewall insulating layer to reach the drain region surface is provided in the interlayer insulating layer and the second sidewall insulating layer. The nonvolatile semiconductor memory device according to claim 1, wherein a bit line electrically connected to the drain region through the contact hole is formed on the insulating layer. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a width of a bottom surface of the sidewall insulating layer in a direction orthogonal to a direction in which the floating gate extends is about 100 Å. 4. A step of forming an element isolation insulating layer so as to define an active region in a predetermined region of a main surface of a first-conductivity-type semiconductor substrate having a memory transistor formed on the main surface, and the main substrate of the semiconductor substrate. First on the active area at the surface
Forming an insulating layer of the memory transistor, forming a floating gate, a second insulating layer and a control gate of the memory transistor on the first insulating layer in sequence, the floating gate and the second insulating layer And a step of forming a third insulating layer over the entire main surface of the semiconductor substrate so as to cover the control gate, and a first region of the main surface of the semiconductor substrate in which a drain region of the memory transistor is formed. Forming a mask layer covering and exposing a surface of the third insulating layer located on a second region of the main surface of the semiconductor substrate where the source region of the memory transistor is formed; and masking the mask layer. Used as the third insulating layer,
Exposing the second region of the main surface of the semiconductor substrate by subjecting the element isolation insulating layer and the first insulating layer located on the second region to anisotropic etching. A second surface is formed on the main surface of the semiconductor substrate in the first and second regions.
A step of forming a source region and a drain region of the memory transistor by introducing a conductivity type impurity, and a method of manufacturing a nonvolatile semiconductor memory device. 5. The step of forming the source region and the drain region forms the source region by introducing impurities of a second conductivity type into the exposed second region using the mask layer as a mask. A step of removing the mask layer, a step of forming a second mask layer covering the second region and exposing the surface of the third insulating layer located on the first region, Forming a drain region by introducing an impurity of a second conductivity type into a first region of the main surface of the semiconductor substrate using the second mask layer as a mask. Non-volatile semiconductor memory device manufacturing method. 6. The step of forming the source region and the drain region, the step of removing the mask layer, and the second conductivity type impurity are simultaneously introduced into the first and second regions on the main surface of the semiconductor substrate. Forming a source region and a drain region by
The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, comprising: 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the thickness of the third insulating layer is about 100Å. 8. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the third insulating layer is an insulating layer including at least one of a silicon oxide film and a silicon nitride film. 9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the material of the element isolation insulating layer and the material of the third insulating layer are the same. 10. The material of the element isolation insulating layer and the third
The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the material of the insulating layer is different from that of the insulating layer.