JPH07161850A - Nonvolatile semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To manufacture a memory cell which is a layer-built gate type nonvolatile memory cell and which can be written at low voltage (<=5V), having a high drain disturb resistance. CONSTITUTION:A layer-built structure comprising a first gate insulating film 3, a floating gate electrode 4b, a second gate insulating film 5, and a control gate electrode 6a is formed on a p type silicon substrate 1, and a source region 10s is formed away from this layer-built gate. A drain region 10d is formed with this layer-built gate in a self-aligning manner, and this drain region forms a double structure of an n<+> diffusion layer 10d and an n<-> diffusion layer 1. A high electric field generates in an offset part on the source side to make write enable at low voltage. Through the double step concentration distribution on the drain side, the electric field strength on the drain side is relaxed with an improvement of a disturb resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a nonvolatile memory semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As a writable / erasable nonvolatile memory element, a floating gate is provided on a channel formed between a source and a drain on a surface of a semiconductor substrate via a first gate insulating film, Further, there is known a field effect transistor (EPROM) in which a control gate is formed on the floating gate through a second gate insulating film to make a capacitive junction. In this memory element, the difference in the threshold voltage due to the difference in the charge storage state of the floating gate causes the difference in data "0", "1".
Memorize as.

When writing information to this storage element,
The control gate is set to a positive high potential to form a channel on the substrate surface, and a positive voltage is applied to the drain. At this time, the electrons traveling in the channel receive energy due to the high electric field generated on the channel, and are injected into the floating gate beyond the potential barrier of the insulating film. A state in which electrons are injected into the floating gate in this way is called a write state. In this write operation, it is extremely important to reduce the write voltage. For example, in the market of a flash memory that electrically writes and electrically erases all bits collectively, there is a strong demand for a transition from the current 12V / 5V dual power supply to 5V single power supply or 3V single power supply. However, for that purpose, it is necessary to lower the voltage in the write operation.

Conventionally, a floating gate field effect transistor having an offset region in a source and a gate has been proposed as a semiconductor memory device for realizing such low voltage writing (for example, IEDM Tech. Di).
g. , Pp. 584-587, 1986, IEEE E
electron Device Letters, vo
l. EDL-7, p. 540-542, IEDM Te
ch. Dig. pp. 315-318, 1991, IE
EE Electron Device Letter
s, vol. 13, pp. 456-467,199
2). The operation of this element causes Source-Sid
e Injection EPROM (hereinafter referred to as SIEP
It is called ROM).

FIG. 9 shows a sectional view of the structure of the SIEPROM. In FIG. 9, the floating gate electrode 4b is formed on the channel region A formed on the surface of the semiconductor substrate 1 between the n ⁺ drain region 10d and the n ⁺ source region 10s with the first gate insulating film 3 interposed therebetween. A control gate electrode 6a is formed at a position overlapping with 10d and having an offset region B with respect to the source region 10s, and on the floating gate electrode 4b via a second gate insulating film 5. In this element, since the offset region B has high resistance, strong electric field concentration occurs on the channel on the source side even if the voltage applied to the control gate electrode 6a and the drain region 10d is relatively low, and this high electric field causes energy. The obtained hot electrons can be injected into the floating gate electrode 4b.

Specifically, for example, a first gate oxide film having a film thickness of 10 nm and a film thickness of 200 nm are formed on the surface of a P-type silicon substrate.
Floating gate electrode, a second gate oxide film having a thickness of 20 nm,
After forming a control gate electrode having a film thickness of 250 nm, an offset length (hereinafter referred to as L _OFF ) of 0.15 μm is provided on the drain side in a self-aligned manner with the gate electrode and on the source side between the gate electrode and the source electrode. A source and drain are simultaneously ion-implanted with accelerating voltage of 70 keV and implantation density of 3 × 10 ¹⁵ cm ² and thermally diffused at 900 ° C. for 30 minutes to form a SIEPROM structure. In FIG. 10, the gate length (hereinafter abbreviated as L) formed in this way is 0.6 μm,
Gate width (hereinafter abbreviated as W) 0.8 μm, L _OFF = 0.
The writing characteristics of a 2 μm SIEPROM are
Shown in comparison with ROM (L _OFF = 0). Write voltage V
_CG = 12V, the V _D = 3V, to the normal of which is impossible to perform writing in EPROM, SIEP
In ROM, write time (hereinafter abbreviated as t _W ) 10 μs
Has been realized.

The memory array having the SEEPROM cells as a basic unit may be arranged so that the cells can be selected by arranging the cells in a matrix and selecting both the signal lines of the word line and the bit line. For example, a memory array can be configured as shown in FIG. 11 (in the following example, the source lines S ₁ and S ₂ , S ₃ are used to reduce the chip size.
And S ₄ , ... Can be common.) Here, to select and read the cell 22, the selected word line W ₂
By 5 V, selected bit B ₂ by 1 V, and other unselected word lines W ₁ , W ₃ , W ₄ , ... And unselected bit lines B ₁ , B ₃ , B ₄ ,. You can do it. That is, since the non-selected cell transistor is off, for the selected cell, 1) a current flows through the bit line B ₂ in an erase state (V _T <2V) where there is no electrons in the floating gate, and 2) electrons are present in the floating gate. In the accumulated write state (V _T > 6 V), no current flows in the bit line B ₂ , so that it is possible to determine data “0” and “1”, respectively. To select the cell 22 for writing, the selected word line W ₂ is boosted to 12 V and the selected bit line B ₂ is boosted to 5 V, and the other unselected word lines W ₁ , W ₃ , W are selected.
_4, ..., and the unselected bit lines _{B 1, B 3, B 4} , ·
.. Can be done by grounding.

[0008]

[Problems to be Solved by the Invention] However, the conventional SIE
When the memory cell array is configured by the PROM and the write operation is performed, the following problems occur. That is, the write voltage V _D (= 5 V) is applied as stress to the drains of the non-selected bit cells on the selected bit line during writing. Due to this voltage stress, 1) electrons accumulated in the floating gate are Fowler-
It is emitted to the drain as a Nordheim tunneling current, 2) Hot holes are generated near the drain and injected into the floating gate, and 3) Electrons and holes are generated by band-to-band tunneling near the drain, and these holes are injected into the floating gate. The above phenomenon occurs, and as a result, the electrons accumulated in the floating gate decrease. In other words, there occurs a phenomenon that the data “1” of the non-selected bit on the selected bit line is erroneously erased to “0” at the time of writing (hereinafter, this phenomenon is referred to as write drain disturb). When this drain disturb occurs, there arises a problem that the number of cells and the number of data rewrites that can be arranged on the same bit line are limited. In particular, considering the application as a flash memory, the sector configuration in the word line direction results in 1) a small erase block configuration.
Or, 2) complicated circuit design such as introduction of a sub-bit line provided with a selection transistor and an increase in processes are required, resulting in a problem that the cost of the device is increased.

An object of the present invention is to provide a non-volatile semiconductor memory device capable of low voltage writing and having high drain disturb resistance.

[0010]

According to the present invention, there are provided a semiconductor substrate having a P-type main surface, an N-type drain region / source region formed on the main surface, and the drain region / source region. In a nonvolatile semiconductor memory device having a channel region formed between them, a floating gate of a first insulating film and a control gate of a second insulating film which are sequentially formed on the channel region, the source region is floating. The drain region is formed in a channel region with an interval (offset) so as not to overlap with the gate or the control gate, the drain region is formed in a self-aligned manner with respect to the floating gate or the control gate, and the drain region is , n ⁺ impurity regions, the adjacent channel region side and lower concentration than the n ⁺ impurity concentration of the n ⁺ impurity region n ^- this being formed from an impurity region The features.

According to the present invention, the low concentration n ^- impurity region adjacent to the channel region side of the drain region is LDD.
(Lightly Doped Drain) structure can be used.

According to the present invention, the low concentration n ⁻ impurity region adjacent to the channel region side of the drain region is D.
DD (Double Diffused Drain)
It can be a structure.

The method for manufacturing a non-volatile semiconductor memory device according to the present invention includes the step of forming an element isolation structure on a semiconductor substrate having a P-type region on the surface to partition the element formation region, and the element formation region. Forming a first gate insulating film on the surface of the semiconductor substrate and depositing a first conductor film on the first gate insulating film;
Patterning a conductor film for the floating gate by leaving a conductor film on the element formation region and its vicinity to form a second gate insulating film by covering the conductor film for the floating gate; And then patterning the second conductive film, the second gate insulating film, and the floating gate conductive film to form a stacked gate structure crossing the central portion of the device forming region, and the stacked gate structure. In a drain region, which is one of the element forming regions where no n is provided, to form an n ⁻ impurity region, and in the source region side and the drain region side of the stacked gate structure. Spacer is formed, ion implantation is performed, and N
And a step of forming an n ⁺ impurity source region and an n ⁺ impurity drain region of the type.

[0014]

According to the above-described means, even when the write voltage V _D is applied as stress to the non-selected bit line on the selected bit line, that is, the drain during the write operation of the memory array, the N-type impurity on the drain side is also applied. By optimizing the concentration distribution, the potential gradient in the vicinity of the drain end can be made gentle, and as a result, it is possible to suppress the occurrence of drain disturb that reduces the electrons accumulated in the floating gate. As a result, a large-capacity flash memory can be configured without making complicated design in circuit design.

Further, the method of manufacturing a semiconductor memory device according to the present invention is highly compatible with the prior art in the manufacturing process, and LDD is provided on the drain side without adding a new mask step.
It is possible to stably manufacture the structure in which the structure is formed and the offset region is formed on the source side.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

1A and 1B are views showing an embodiment of a nonvolatile semiconductor memory device of the present invention, FIG. 1A is a partial plan view, and FIG.
Is a sectional view. In this example, the boron concentration is 2 × 10 ^15.
A cm ⁻³ P-type silicon substrate 1 (or an N ⁻ -type silicon substrate having a P well formed therein, in which case P
The surface of the P-type silicon substrate 1 sandwiched between the N-type drain region 10d and the source region 10s selectively formed on the surface of the well having a concentration of 2 × 10 ¹⁵ cm ⁻³ The second gate insulating film 5 (20 n thick) is formed on the surface of the floating gate electrode 4b and the floating gate electrode 4b which are selectively covered with the gate insulating film 3 (10 nm thick silicon oxide film).
control gate electrode 6a deposited via a silicon oxide film of m), the source region 10s and the floating gate electrode 4b.
In the nonvolatile semiconductor memory device in which the offset region is provided between the drain region 10d and the portion immediately below, the drain region 10d formed of the shallow n ⁺ diffusion layer is doubled with the n ⁻ diffusion layer 7 formed so as to surround it. It has a structure. Note that, for example, L _OFF = 0.15 μm, the n ⁻ diffusion layer 7 is formed by ion diffusion of phosphorus at an acceleration voltage of 70 keV and an implantation density of 5 × 10 ¹⁴ cm ⁻² , and then thermal diffusion at 980 ° C. for 45 minutes. Subsequently, the source region 10s and the n ⁺ diffusion layer 10 in the drain region 10
d is an acceleration voltage of 50 keV and an implantation density of 5 × 10 ¹⁵ cm ^-2
After ion implantation of arsenic at 850 ° C., it was formed by thermal diffusion at 850 ° C. for 30 minutes. In FIG. 1, 11 is an interlayer insulating film, 1
Reference numeral 2 is a contact hole, and 13 is an extraction electrode.

FIG. 2 is a graph showing the write drain disturb of the SIEPROM according to this embodiment. L =
The threshold voltage V of the memory cell in the write state when the stress of V _CG = V _S = 0V; V _D = 5V is applied to the element of 0.6 μm, W = 0.8 μm, L _OFF = 0.15 μm The actual measured value of the change in _TM is shown. While the conventional SIEPROM having a simple single drain structure causes a threshold change of 1 V (V _TM = 6 V → 5 V) in 100 ms, the SIEPROM of this embodiment has a drain disturb resistance of 10 ⁵ s or more. There is. When designing a flash memory array in which sectors are arranged in the word line direction and t _w = 10 μs and the number of data rewrites is 10 ⁶ or more, the number of cells that can be formed on the same bit line should be 10 ^4. It is possible. As described above, in the cell of this embodiment, the gate disturb resistance is remarkably improved, and the degree of freedom of the array configuration can be increased.

Next, an embodiment of a method for manufacturing a nonvolatile semiconductor memory device of the present invention will be described with reference to the drawings. First, as shown in FIG. 3, P with an impurity concentration of 2 × 10 ¹⁵ cm ⁻³ is used.
A type silicon substrate 1 (or a P ⁻ type silicon substrate on which a P well may be formed) is prepared, and a trench or a field oxide film 2 is formed as an element isolation structure to partition an element forming region. A first gate insulating film 3 and a first conductor film 4 are sequentially grown on it. For example, the first gate insulating film 3 can be a silicon nitride oxide film with a thickness of 10 nm, and the first conductor film 4 can be a polysilicon film with a thickness of 200 nm doped with impurities.

Next, as shown in FIG. 4, after patterning the first conductor film 4 to form a floating gate conductor film 4a covering the element formation region and its vicinity, a second gate insulating film 5 is grown. Then, the second conductor film 6 is grown. Where the second
The gate insulating film 5 is, for example, ON with a thickness of 20 nm.
An O three-layer film (silicon oxide film / silicon nitride film / silicon oxide film) is used, and the second conductor film 6 has a thickness of 250 n.
m tungsten polycide film (tungsten silicide film / polysilicon film) can be used.

Next, as shown in FIG. 5, the second conductor film 6,
By patterning the second gate insulating film 5 and the floating gate conductor film 4a sequentially by anisotropic dry etching, a stacked gate structure including the floating gate electrode 4b, the second gate insulating film 5, and the control gate electrode 6a is obtained. Form. This laminated gate structure generally crosses the central portion of the element formation region, and the control gate electrode 6a is usually processed into a form connected to the control gate electrode wiring. Then, a photosensitive resist film C is applied to the entire surface of the substrate, and then a hole is formed on the drain region by photolithography to remove arsenic ions (As).
⁺ ) With an acceleration energy of 50 keV and a density of 5 × 10 ¹³ cm
^At 850 after peeling off the photosensitive resist film C by injecting at ^-2
The n ⁻ impurity region 8 is formed by thermal diffusion at 30 ° C. for 30 minutes.

Next, as shown in FIG. 6, a silicon oxide film 9 is grown. The silicon oxide film 9 can be formed by, for example, a chemical vapor deposition method (CVD) having good step coverage.

Next, as shown in FIG. 7, the silicon oxide film 9 formed on the surface of the semiconductor substrate 1 is entirely etched by anisotropic dry etching, whereby the floating gate electrode 4b, the second gate insulating film 5, and the like. A sidewall 9a of polysilicon is formed on the sidewall of the control gate electrode 6a.

Finally, as shown in FIG. 8, arsenic ions (As ⁺ ) are accelerated at an energy of 70 keV and a density of 5 × 10.
Ion implantation is performed at ¹⁵ cm ^-2 , and then 90 in a nitrogen atmosphere.
A heat treatment is performed at 0 ° C. for 30 minutes to form a source region 10s and a drain region 10d of n ⁺ impurities.

According to this manufacturing method, the LDD structure is formed on the drain side and the offset region is formed on the source side by a process highly compatible with the conventional technique and without adding a new mask step. The semiconductor memory device to be formed can be manufactured stably. Further, since the impurity distribution in the source region and the impurity distribution in the drain side are independently performed in the manufacturing process, the degree of freedom in memory cell design is extremely high.

[0026]

As described above, according to the present invention, in the nonvolatile semiconductor memory element having the floating gate, the source region is formed with an offset in the channel region so as not to overlap the floating gate, and the drain region is formed. The n ^- diffusion layer and the n ⁺ diffusion layer are provided to optimize the impurity concentration distribution, and it is possible to stably manufacture a SIEPROM having a high drain disturbance resistance and a high degree of freedom in design capable of low voltage and high speed writing.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view of an embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a write drain disturb resistance of the nonvolatile semiconductor memory device shown in FIG.

FIG. 3 is a process sectional view of an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a process sectional view of an example of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 5 is a process sectional view of an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a process sectional view of an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a process sectional view of an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 8 is a process sectional view of an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 9 is a diagram showing a conventional semiconductor memory element (SIEPROM).

10 is a diagram showing write characteristics of the semiconductor memory element shown in FIG.

FIG. 11 is a diagram showing a memory array having the semiconductor memory element shown in FIG. 9 as a basic unit.

[Explanation of symbols]

1 semiconductor substrate 2 element isolation structure (field oxide film or trench isolation oxide film) 3 first gate insulating film 4 first conductive film 4a floating gate conductor film 4b floating gate electrode 5 second gate insulating film 6 second conductive film 6a Control gate electrode 7 n ^- Diffusion layer (DDD) 8 n ^- Diffusion layer (LDD) 9 Silicon oxide film 9a Silicon oxide film side wall (spacer) 10d Drain region (n ⁺ diffusion layer) 10s Source region (n ⁺ diffusion layer) 11 interlayer insulating film 12 contact hole 13 extraction electrode A channel region B offset region C photosensitive resist

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[Procedure amendment]

[Submission date] October 14, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010]

According to the present invention, there are provided a semiconductor substrate having a P-type main surface, an N-type drain region / source region formed on the main surface, and the drain region / source region. A channel region formed between the first and second insulating films / floating gates sequentially formed on the channel region
In a non-volatile semiconductor memory device having a second insulating film / control gate , the source region is formed with an interval (offset) provided in the channel region so as not to overlap the floating gate or the control gate, and the drain region is Formed in self-alignment with the floating gate or the control gate, and
It said drain region, and the n ⁺ impurity region, the n ⁺ adjacent to the channel region side of the impurity region and the n ⁺ impurity concentration than the low concentration of the n ^- characterized in that it is formed from the impurity region.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/115

Claims (4)

[Claims] 1. A semiconductor substrate having a P-type main surface, an N-type drain region / source region formed on the main surface, and a channel region formed between the drain region / source region. A nonvolatile semiconductor memory device having a floating gate of a first insulating film and a control gate of a second insulating film sequentially formed on the channel region, wherein the source region does not overlap with the floating gate or the control gate. The drain region is formed with a gap (offset) in the channel region, the drain region is formed in a self-aligned manner with respect to the floating gate or the control gate, and
Said drain region, and the n ⁺ impurity region, the n ⁺ adjacent to the channel region side of the impurity region and the n ⁺ impurity concentration than the low concentration of n ^- non-volatile, characterized in that it is formed from the impurity regions Semiconductor integrated circuit device. 2. The nonvolatile semiconductor integrated circuit device according to claim 1, wherein the low concentration n ⁻ impurity region adjacent to the channel region side of the drain region has an LDD structure. 3. The non-volatile semiconductor integrated circuit device according to claim 1, wherein the low concentration n ⁻ impurity region adjacent to the channel region side of the drain region has a DDD structure. 4. A step of forming an element isolation structure on a semiconductor substrate having a P-type region on its surface to partition the element formation region, and covering the surface of the semiconductor substrate in the element formation region with a first structure.
Forming a gate insulating film, depositing a first conductor film, and patterning leaving the first conductor film on the element forming region and its vicinity to form a conductor film for a floating gate; To form a second gate insulating film, deposit a second conductor film, and then deposit the second conductor film and the second conductor film.
Patterning the gate insulating film and the conductor film for a floating gate to form a stacked gate structure crossing the central portion of the device forming region; and one of the device forming region where the stacked gate structure is not provided. Implanting predetermined ions into a certain drain region to form an n ^- impurity region; forming a spacer on the source region side and the drain region side of the stacked gate structure and performing ion implantation to perform N-type n-type implantation. ^A method of manufacturing a non-volatile semiconductor integrated circuit device, comprising: forming an ⁺ impurity source region and an n ⁺ impurity drain region.