CN102623455A - Nonvolatile memory cell and method for manufacturing same - Google Patents

Nonvolatile memory cell and method for manufacturing same Download PDF

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Publication number
CN102623455A
CN102623455A CN2011100301927A CN201110030192A CN102623455A CN 102623455 A CN102623455 A CN 102623455A CN 2011100301927 A CN2011100301927 A CN 2011100301927A CN 201110030192 A CN201110030192 A CN 201110030192A CN 102623455 A CN102623455 A CN 102623455A
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layer
domain
memory cells
volatile memory
silicon oxide
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刘奎伟
张赛
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GigaDevice Semiconductor Beijing Inc
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GigaDevice Semiconductor Beijing Inc
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Abstract

The invention discloses a nonvolatile memory cell and a method for manufacturing the same. The nonvolatile memory cell comprises: a transistor consists of a drain, a source, a grid and a substrate, wherein the transistor includes: a first heavily doped region, a second heavily doped region, a polycrystalline silicon layer, the substrate, an asymmetrical lightly doped zone, a first sidewall, a second sidewall and a silicon oxide layer; the silicon oxide layer is positioned on the substrate; the polycrystalline silicon layer, the first sidewall and the second sidewall are all located on the silicon oxide layer; the first sidewall and the second sidewall are arranged on the two sides of the polycrystalline silicon layer respectively; the asymmetrical lightly doped zone adjoins the second heavily doped region and the silicon oxide layer. The nonvolatile memory cell and the method for manufacturing the same provided by the invention are completely compatible with the prior logic process, particularly the deep submicron logic process; the memory cell area is able to be reduced with the reduction of the prior logic process.

Description

A kind of non-volatile memory cells and manufacturing approach thereof
Technical field
The present invention relates generally to semiconductor storage unit, relates in particular to a kind of non-volatile memory cells and manufacturing approach thereof.
Background technology
Nonvolatile memory chip is widely used in electronic product, computer, communication device, consumer electronics and other to be needed in the application that the data power down preserves.Nonvolatile memory comprises polytype, and wherein, EPROM, flash memory types such as (Flash Memory) all have programming and erase function.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of non-volatile memory cells and manufacturing approach thereof, itself and existing logic process especially deep-submicron logic process are compatible fully, and the area of memory cell can dwindling and dwindle with technology.
According to an aspect of the present invention, a kind of non-volatile memory cells is provided, has comprised:
The transistor that constitutes by drain electrode, source electrode, grid and substrate;
Transistor comprises:
First heavily doped region, second heavily doped region, polysilicon layer, substrate, asymmetric light doping section, first side wall, second side wall and silicon oxide layer; Wherein,
Silicon oxide layer is positioned on the substrate;
Polysilicon layer, first side wall, second side wall all are positioned on the silicon oxide layer;
First side wall, second side wall lay respectively at the both sides of polysilicon layer;
Asymmetric light doping section is adjacent to second heavily doped region and silicon oxide layer.
According to a characteristic of the present invention,
Said first side wall is used for stored charge.
According to another characteristic of the present invention,
The thickness of said silicon oxide layer equals the thickness of the transistorized silicon oxide layer of thick grid oxygen under the standard semiconductor logic process.
According to another characteristic of the present invention,
Said transistor is a nmos pass transistor.
According to a further aspect in the invention, a kind of nonvolatile memory of making according to said non-volatile memory cells is provided.
According to a further aspect in the invention, a kind of domain of non-volatile memory cells is provided, has comprised:
Active region layer, polysilicon layer, drain-source injection region layer and auxiliary layer, wherein,
Auxiliary layer is used for covering the active region layer of a side that is positioned at the polysilicon layer both sides.
According to another characteristic of the present invention,
The size and dimension of auxiliary layer can be set according to predetermined design rule.
According to a further aspect in the invention, a kind of mask plate patterns that generates according to said domain is provided, has comprised:
Active region layer, polysilicon layer, drain-source injection region layer and asymmetric light dope implanted layer, wherein,
According to the predetermined logic operational formula drain-source injection region layer and auxiliary layer are carried out logical operation, make and in the said active region layer that said auxiliary layer covers, do not carry out the light dope injection, thereby obtain said asymmetric light dope implanted layer.
According to a characteristic of the present invention,
The predetermined logic operational formula is:
S M5＝S L3-S L4-S X5
Wherein, S M5The area of the light dope implanted layer in the expression mask plate patterns,
S L3The area of the drain-source injection region layer in the expression domain,
S L4The area of the auxiliary layer in the expression domain,
S X5Represent predefined when domain is transformed into the mask figure area correction value of light dope implanted layer.
A kind of manufacturing approach of non-volatile memory cells of said mask plate patterns is provided according to a further aspect in the invention.
Non-volatile memory cells of the present invention and manufacturing approach thereof, compatible fully with existing logic process especially deep-submicron logic process, the area of memory cell can dwindling and dwindle with existing logic process.This non-volatile memory cells utilizes the transistorized side wall stored charge of asymmetric light doping section; Through control side wall stored charge the source of how much coming the control store unit, the drain electrode between conducting resistance; With the source that changes memory cell, the conducting electric current between the drain electrode, thereby can confirm the data of storing according to the source of memory cell, conducting electric current between the drain electrode.
Description of drawings
Fig. 1 is as the transistorized circuit diagram of non-volatile memory cells in the embodiment of the invention;
Fig. 2 is the transistorized structure chart of the thick grid oxygen of the standard of logic-based technology;
Fig. 3 is as the transistorized structure chart of non-volatile memory cells in the embodiment of the invention;
Fig. 4 is the transistorized domain of the thick grid oxygen of the standard of logic-based technology;
Fig. 5 is as the transistorized domain of non-volatile memory cells in the embodiment of the invention;
Fig. 6 is the transistorized mask plate patterns of the thick grid oxygen of the standard of logic-based technology;
Fig. 7 is as the transistorized mask plate patterns of non-volatile memory cells in the embodiment of the invention.
Embodiment
Describe specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
Fig. 1 be in the embodiment of the invention as the transistorized circuit diagram of non-volatile memory cells, among Fig. 1, the transistor as non-volatile memory cells in the embodiment of the invention of logic-based technology comprises:
Drain D, source S, grid G and substrate B.
Fig. 2 is the transistorized structure chart of the thick grid oxygen of the standard of logic-based technology, and among Fig. 2, the thick grid oxygen of standard transistor comprises:
First heavily doped region 201, second heavily doped region 202, polysilicon layer 203, substrate 204, first light doping section 205, second light doping section 206, first side wall 207, second side wall 208 and silicon oxide layer 209.
Can know that according to Fig. 2 the thick grid oxygen of standard transistor comprises first light doping section 205, second light doping section 206 of symmetry.Wherein, first heavily doped region 201, second heavily doped region 202 are N type heavily doped region, and substrate 204 is a P type trap.The thick grid oxygen of standard transistor is used to realize imput output circuit in logic process.Under 0.13 micron semiconductor fabrication process, the thickness of the transistorized silicon oxide layer 209 of the thick grid oxygen of standard is generally the 6-8 nanometer.Under different semiconductor fabrication process, the thickness of the transistorized silicon oxide layer 209 of the thick grid oxygen of standard is also different.
Fig. 3 be in the embodiment of the invention as the transistorized structure chart of non-volatile memory cells, among Fig. 3, the transistor as non-volatile memory cells in the embodiment of the invention comprises:
First heavily doped region 301, second heavily doped region 302, polysilicon layer 303, substrate 304, light doping section 305, first side wall 306, second side wall 307 and silicon oxide layer 308.Wherein,
Silicon oxide layer 308 is positioned on the substrate 304;
Polysilicon layer 303, first side wall 306, second side wall 307 all are positioned on the silicon oxide layer 308;
First side wall 306, second side wall 307 lay respectively at the both sides of polysilicon layer 303;
Light doping section 305 is adjacent to second heavily doped region 302 and silicon oxide layer 308.
The thickness of silicon oxide layer 308 equals the thickness of the transistorized silicon oxide layer of thick grid oxide layer under the standard semiconductor logic process.
Can know that according to Fig. 3 the transistor as non-volatile memory cells in the embodiment of the invention only comprises light doping section 305, belong to asymmetric light doping section transistor npn npn.
Transistorized storage area as non-volatile memory cells in the embodiment of the invention is arranged at first side wall, 306 places; Promptly adopt first side wall, 306 stored charges; Control as the conducting resistance between the transistorized source-drain electrode of non-volatile memory cells through controlling first side wall, 306 charge stored numbers; With the conducting size of current between the transistorized source-drain electrode that changes non-volatile memory cells, thereby can confirm the data of storing according to the conducting size of current between the transistorized source-drain electrode of non-volatile memory cells.
Transistor as non-volatile memory cells in the embodiment of the invention passes through to use asymmetric light doping section, has not only reduced program erase voltage, and has improved program erase speed.
Fig. 4 is the transistorized domain of the thick grid oxygen of the standard of logic-based technology, comprises among Fig. 4:
Active region layer L1, polysilicon layer L2 and drain-source injection region layer L3.
Generate the thick grid oxygen of the standard transistor among Fig. 2 according to the domain among Fig. 4.
Fig. 5 be in the embodiment of the invention as the transistorized domain of non-volatile memory cells, comprise among Fig. 5:
Active region layer L1, polysilicon layer L2, drain-source injection region layer L3 and auxiliary layer L4.
According in the embodiment of the invention in the domain shop drawings 3 among Fig. 5 as the transistor of non-volatile memory cells.
Can know that through comparison diagram 4,5 domain among Fig. 5 and the difference of the domain among Fig. 4 are to have increased auxiliary layer L4, auxiliary layer L4 does not influence the figure of other layers such as active region layer L1 in the domain, polysilicon layer L2, drain-source injection region layer L3.
Auxiliary layer L4 can set according to the design rule that wafer factory (IC chip manufactory) provides.Auxiliary layer L4 among Fig. 5 is only as an example; Be not limited to the concrete size and dimension of auxiliary layer L4; Design rule that the designer can provide according to wafer factory and actual needs design the size and dimension of auxiliary layer L4, as long as the active area of the side that is arranged in polysilicon layer L2 both sides in the domain in can coverage diagram 5.
Transistorized manufacturing is to accomplish through transistorized mask figure is copied to silicon chip; And transistorized mask figure is to be converted to by transistorized domain; Wafer factory can provide the conversion Calculation method of domain to the mask figure; Be the predetermined logic operational formula, different wafer factory has different predetermined logic operational formulas.For example, for nmos pass transistor, the P type trap that in domain, generally do not draw, but in the process of making the mask figure, the predetermined logic operational formula that provides according to wafer factory is carried out logical operation to the P type trap layer of NMOS and is obtained.Similar therewith, the present invention utilizes this process to realize the transistorized asymmetric light doping section as non-volatile memory cells just.Particularly, add auxiliary layer in the transistorized domain as non-volatile memory cells in embodiments of the present invention, this auxiliary layer is used for when generating the mask figure, the light doping section layer being carried out logical operation.That is to say,, on the mask figure, realize asymmetrical light doping section through revising the logical calculation method of mask figure.
Fig. 6 is the transistorized mask plate patterns of the thick grid oxygen of the standard of logic-based technology, comprises among Fig. 6: active region layer M1, polysilicon layer M2, drain-source injection region layer M3 and light dope implanted layer M4.
According to the predetermined logic operational formula active region layer L1 among Fig. 4 is carried out logical operation, obtain active region layer M1; Wherein, the predetermined logic operational formula of active region layer M1 can for:
S M1＝S L1-S X1
S M1The area of active region layer M1 in the expression mask plate patterns,
S L1The area of active region layer L1 in the expression domain,
S X1Represent predefined when domain is transformed into the mask figure area correction value of active region layer, this area correction value S X1Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
According to the predetermined logic operational formula polysilicon layer L2 among Fig. 4 is carried out logical operation, obtain polysilicon layer M2; Wherein, the predetermined logic operational formula of polysilicon layer M2 can for:
S M2＝S L2-S X2
S M2The area of polysilicon layer M2 in the expression mask plate patterns,
S L2The area of polysilicon layer L2 in the expression domain,
S X2Represent predefined when domain is transformed into the mask figure area correction value of polysilicon layer, this area correction value S X2Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
According to the predetermined logic operational formula drain-source injection region layer L3 among Fig. 4 carried out logical operation, obtain drain-source injection region layer M3; Wherein, the predetermined logic operational formula of drain-source injection region layer M3 can for:
S M3＝S L3-S X3
S M3The area of drain-source injection region layer M3 in the expression mask plate patterns,
S L3The area of drain-source injection region layer L3 in the expression domain,
S X3Represent predefinedly to be transformed into the area correction value of injection region, mask figure hourglass source layer, this area correction value S from domain X3Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
According to the predetermined logic operational formula drain-source injection region layer L3 among Fig. 4 carried out logical operation, obtain light dope implanted layer M4; Wherein, the predetermined logic operational formula of light dope implanted layer M4 can for:
S M4＝S L3-S X4
S M4The area of light dope implanted layer M4 in the expression mask plate patterns,
S L3The area of drain-source injection region layer L3 in the expression domain,
S X4Represent predefined when domain is transformed into the mask figure area correction value of light dope implanted layer, this area correction value S X4Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
The light doping section that the thick grid oxygen of the standard transistor of realizing through the mask figure among Fig. 6 has symmetry as shown in Figure 2.
Fig. 7 be in the embodiment of the invention as the transistorized mask plate patterns of non-volatile memory cells, comprise among Fig. 7: active region layer M1, polysilicon layer M2, drain-source injection region layer M3 and light dope implanted layer M5.
According to the predetermined logic operational formula active region layer L1 among Fig. 5 is carried out logical operation, obtain active region layer M1; Wherein, the predetermined logic operational formula of active region layer M1 can for:
S M1＝S L1-S X1
S M1The area of active region layer M1 in the expression mask plate patterns,
S L1The area of active region layer L1 in the expression domain,
S X1Represent predefined when domain is transformed into the mask figure area correction value of active region layer, this area correction value S X1Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
According to the predetermined logic operational formula polysilicon layer L2 among Fig. 5 is carried out logical operation, obtain polysilicon layer M2; Wherein, the predetermined logic operational formula of polysilicon layer M2 can for:
S M2＝S L2-S X2
S M2The area of polysilicon layer M2 in the expression mask plate patterns,
S L2The area of polysilicon layer L2 in the expression domain,
S X2Represent predefined when domain is transformed into the mask figure area correction value of polysilicon layer, this area correction value S X2Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
According to the predetermined logic operational formula drain-source injection region layer L3 among Fig. 5 carried out logical operation, obtain drain-source injection region layer M3; Wherein, the predetermined logic operational formula of drain-source injection region layer M3 can for:
S M3＝S L3-S X3
S M3The area of drain-source injection region layer M3 in the expression mask plate patterns,
S L3The area of drain-source injection region layer L3 in the expression domain,
S X3Represent predefinedly to be transformed into the area correction value of injection region, mask figure hourglass source layer, this area correction value S from domain X3Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
According to the predetermined logic operational formula drain-source injection region layer L3 and auxiliary layer L4 among Fig. 5 are carried out logical operation, obtain light dope implanted layer M5; Wherein, the predetermined logic operational formula of light dope implanted layer M5 can for:
S M5＝S L3-S L4-S X5，
S M5The area of light dope implanted layer M5 in the expression mask plate patterns,
S L3The area of drain-source injection region layer L3 in the expression domain,
S L4The area of auxiliary layer L4 in the expression domain,
S X5Represent predefined when domain is transformed into the mask figure area correction value of light dope implanted layer, this area correction value S X5Can be set on the occasion of, negative value or be zero (promptly need not to revise) according to the actual design needs.
Promptly in as the logical calculated of the transistorized mask figure of non-volatile memory cells, remove area portions as the auxiliary layer L4 in the transistorized domain of non-volatile memory cells; To realize the mask figure of asymmetrical light doping section; Thereby make asymmetrical light doping section, only carry out light dope and inject in the zone that light dope implanted layer M5 is arranged.
Has asymmetrical light doping section as shown in Figure 3 through the transistor as non-volatile memory cells in the embodiment of the invention of the realization of the mask plate patterns among Fig. 7.
Being used for calculating logical calculated formula and Fig. 6 of obtaining active region layer M1, polysilicon layer M2, drain-source injection region layer M3 among Fig. 7, to be used to calculate the logical calculated formula of acquisition active region layer M1, polysilicon layer M2, drain-source injection region layer M3 identical.To be used to calculate the logical calculated formula of acquisition light dope implanted layer M4 different and be used for calculating the logical calculated formula that obtains light dope implanted layer M5 and Fig. 6 among Fig. 7.
The above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification, the change that the embodiment of the invention is done, make up, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a non-volatile memory cells is characterized in that, comprising:
The transistor that constitutes by drain electrode, source electrode, grid and substrate;
Said transistor comprises:
First heavily doped region, second heavily doped region, polysilicon layer, substrate, asymmetric light doping section, first side wall, second side wall and silicon oxide layer; Wherein,
Said silicon oxide layer is positioned on the said substrate;
Said polysilicon layer, said first side wall, said second side wall all are positioned on the said silicon oxide layer;
Said first side wall, said second side wall lay respectively at the both sides of said polysilicon layer;
Said asymmetric light doping section is adjacent to said second heavily doped region and said silicon oxide layer.
2. non-volatile memory cells according to claim 1 is characterized in that,
Said first side wall is used for stored charge.
3. non-volatile memory cells according to claim 1 is characterized in that,
The thickness of said silicon oxide layer equals the thickness of the transistorized silicon oxide layer of thick grid oxygen under the standard semiconductor logic process.
4. non-volatile memory cells according to claim 1 is characterized in that,
Said transistor is a nmos pass transistor.
5. nonvolatile memory that non-volatile memory cells according to claim 1 is made.
6. the domain of a non-volatile memory cells is characterized in that, comprising:
Active region layer, polysilicon layer, drain-source injection region layer and auxiliary layer, wherein,
Said auxiliary layer is used for covering the said active region layer of a side that is positioned at said polysilicon layer both sides.
7. domain according to claim 6 is characterized in that,
The size and dimension of said auxiliary layer can be set according to predetermined design rule.
8. the mask plate patterns that domain according to claim 6 generates is characterized in that, comprising:
Active region layer, polysilicon layer, drain-source injection region layer and asymmetric light dope implanted layer, wherein,
According to the predetermined logic operational formula drain-source injection region layer in the said domain and auxiliary layer are carried out logical operation, make and in the said active region layer that said auxiliary layer covers, do not carry out the light dope injection, thereby obtain said asymmetric light dope implanted layer.
9. mask plate patterns according to claim 8 is characterized in that,
Said predetermined logic operational formula is:
S M5＝S L3-S L4-S X5
Wherein, S M5The area of representing the light dope implanted layer in the said mask plate patterns,
S L3The area of representing the drain-source injection region layer in the said domain,
S L4The area of representing the auxiliary layer in the said domain,
S X5Represent predefined when domain is transformed into the mask figure area correction value of light dope implanted layer.
10. the manufacturing approach of the non-volatile memory cells of a mask plate patterns according to claim 8.
CN2011100301927A 2011-01-27 2011-01-27 Nonvolatile memory cell and method for manufacturing same Pending CN102623455A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106610561A (en) * 2015-10-20 2017-05-03 无锡华润上华半导体有限公司 Forming method of mask

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2901473B2 (en) * 1993-12-09 1999-06-07 日本電気株式会社 Nonvolatile semiconductor integrated circuit device
US20010001294A1 (en) * 1998-06-30 2001-05-17 Federico Pio EEPROM memory cell and corresponding manufacturing method
US20050224859A1 (en) * 2002-03-04 2005-10-13 Sharp Kabushiki Kaisha Semiconductor storage device
CN1967871A (en) * 2005-11-17 2007-05-23 力旺电子股份有限公司 Semiconductor device and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2901473B2 (en) * 1993-12-09 1999-06-07 日本電気株式会社 Nonvolatile semiconductor integrated circuit device
US20010001294A1 (en) * 1998-06-30 2001-05-17 Federico Pio EEPROM memory cell and corresponding manufacturing method
US20050224859A1 (en) * 2002-03-04 2005-10-13 Sharp Kabushiki Kaisha Semiconductor storage device
CN1967871A (en) * 2005-11-17 2007-05-23 力旺电子股份有限公司 Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106610561A (en) * 2015-10-20 2017-05-03 无锡华润上华半导体有限公司 Forming method of mask
CN106610561B (en) * 2015-10-20 2020-03-24 无锡华润上华科技有限公司 Method for forming photoetching plate

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Application publication date: 20120801