CN102881691B - P-type OTP (one time programmable) device and preparing method therefore - Google Patents
P-type OTP (one time programmable) device and preparing method therefore Download PDFInfo
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- CN102881691B CN102881691B CN201110195123.1A CN201110195123A CN102881691B CN 102881691 B CN102881691 B CN 102881691B CN 201110195123 A CN201110195123 A CN 201110195123A CN 102881691 B CN102881691 B CN 102881691B
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Abstract
The invention discloses a P-type OTP (one time programmable) device. A channel region of a second PMOS (P-channel metal oxide semiconductor) transistor is provided with one N-type threshold voltage injection region more than a channel region of a first PMOS transistor, and the threshold voltage injection region is used for increasing absolute value of threshold voltage of the second PMOS transistor. The invention also discloses a preparing method for the P-type OTP device. The preparing method comprises the following steps: performing N-type ion implantation on the channel region of the second PMOS transistor by increasing a mask to form the threshold voltage injection region. According to the P-type OTP device and preparing method provided by the invention, threshold voltage of the second PMOS transistor can be increased, programmable performance of the P-type OTP device can be greatly improved, conducted current of the whole device can be improved after programming, distinguishable current range before and after programming can be increased for the device, and area of peripheral circuit for realizing OTP functions can be decreased.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of P type OTP parts, the invention still further relates to the manufacture method of this P type OTP parts.
Background technology
As shown in Figure 1, it is existing P type OTP parts structural representation, silicon substrate 10 is formed N-type trap 15, to be connected the disposal programmable device formed by two PMOS transistor 11,12, first PMOS transistor 11 is as the gate transistor of OTP parts, and second PMOS transistor 12 is as the memory cell of described OTP parts.
The source electrode of described first PMOS transistor 11 comprise be formed at a p type diffusion region 191 in N trap and a P type lightly doped region 19, the drain electrode of described first PMOS transistor 11 comprises p type diffusion region 192 and the P type lightly doped region 19 be formed in N trap, described first PMOS transistor grid 17 is as the wordline of described OTP parts, and described first PMOS transistor 11 source electrode is as the source electrode of described OTP parts.
The grid 16 of described second PMOS transistor 12 is the floating boom of floating, the source electrode of described second PMOS transistor 12 comprise be formed at described p type diffusion region 192 in described N trap and a P type lightly doped region 19, the drain electrode of described second PMOS transistor 12 comprises and is formed at described p type diffusion region 193 in described N trap and a P type lightly doped region 19, the drain electrode of described second PMOS transistor 12 is as the bit line of described OTP parts, and the source electrode of described second PMOS transistor 12 and the drain electrode of described PMOS first transistor 11 share a p type diffusion region 192.Each described P type lightly doped region 19 all extends to the bottom of the described grid 13 or 16 of each described P type lightly doped region 19 correspondence and forms the second coupling regime.
Existing P type OTP parts and logic process completely compatible, do not need to increase any extra light shield, so be widely used.But the source-drain electrode of two PMOS transistor of composition P type OTP parts and the coupling capacitance of grid and the coupling capacitance between described second coupling regime and corresponding described grid less, cause the programming efficiency of this device lower, namely rear differentiable current range is very little before programming for this device.As shown in Figure 3, be existing P type OTP parts not lining bias-voltage time programming before and after working curve; Known device before programming rear differentiable current range is very little.
When existing solution normally reads electric current, N-type trap 15 adds a underlayer voltage and namely serves as a contrast bias-voltage, to increase differentiable current range before and after programming.This will consume the area of a large amount of OTP peripheral circuits.Although each cellar area of P type OTP parts is very little, under the application of such device is limited in the application scenario needing high-density capacity by more peripheral circuit.
As shown in Figure 4, be existing P type OTP parts add 1V serve as a contrast bias-voltage time programming before and after working curve; Device before programming rear differentiable current range becomes large, but the current value before and after programming diminishes.When underlayer voltage is too high, reading electric current can be caused too low, and reading circuit cannot read the electric current of the OTP unit of having programmed; Underlayer voltage is too low, then the OTP unit initial current before programming is excessive, also cannot distinguish the state of OTP unit.So usually will realize providing two accurate voltages to substrate and source by very complicated peripheral reading circuit simultaneously, this can consume very large chip area simultaneously.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of P type OTP parts, described P type OTP parts program performance can be made significantly to be improved, and can improve programmed after the On current of whole device, add device rear differentiable current range before programming, the area of the peripheral circuit realizing OTP function can also be reduced; For this reason, the present invention also provides a kind of manufacture method of this P type OTP parts.
For solving the problems of the technologies described above, P type OTP parts provided by the invention to be connected the disposal programmable device formed by two PMOS transistor, first PMOS transistor is as the gate transistor of OTP parts, and second PMOS transistor is as the memory cell of described OTP parts.
The source electrode of described first PMOS transistor and drain electrode comprise all respectively and are formed at a p type diffusion region in N trap and a P type lightly doped region, described first PMOS transistor grid is as the wordline of described OTP parts, and described first PMOS transistor source electrode is as the source electrode of described OTP parts.
The grid of described second PMOS transistor is the floating boom of floating, the source electrode of described second PMOS transistor and drain electrode comprise all respectively and are formed at a p type diffusion region in described N trap and a P type lightly doped region, the drain electrode of described second PMOS transistor is as the bit line of described OTP parts, and the source electrode of described second PMOS transistor and the drain electrode of described PMOS first transistor share a p type diffusion region.
The threshold voltage injection region of a channel region N-type more than the channel region of described first PMOS transistor of described second PMOS transistor, this threshold voltage injection region is for increasing the absolute value of the threshold voltage of described second PMOS transistor.
Further improvement is, the absolute value of the threshold voltage before the programming of described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
Further improvement is, the injection ion of described threshold voltage injection region is phosphorus, Implantation Energy is 10Kev ~ 100Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
Further improvement is, the injection ion of described threshold voltage injection region is arsenic, Implantation Energy is 30Kev ~ 200Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
For solving the problems of the technologies described above, the manufacture method of P type OTP parts provided by the invention comprises the steps:
Step one, the N-type well region forming effectively isolation on a silicon substrate and place.
Step 2, the channel region of follow-up second PMOS transistor that will be formed carry out N-type ion implantation formed threshold voltage injection region, this threshold voltage injection region is for increasing the absolute value of the threshold voltage of described second PMOS transistor.
Step 3, above described well region, form gate dielectric layer, dielectric layer forms polysilicon; Etch described polysilicon, form the grid of first PMOS transistor and second PMOS transistor, define source region and the drain region of first PMOS transistor and second PMOS transistor, and make the drain region of described first PMOS transistor identical with the region in the source region of second PMOS transistor.
Step 3, with the described polysilicon after etching for autoregistration implanting p-type light dope ion is carried out, at the grid of described first PMOS transistor and the grid both sides P type lightly doped region respectively of described second PMOS transistor in barrier layer.
Step 4, formed the grid of described first PMOS transistor and described second PMOS transistor sidewall, utilize the described sidewall of each described grid and correspondence to carry out described first PMOS transistor for barrier layer and second PMOS transistor P type heavy doping ion is injected, and annealing activates, form source electrode and the drain electrode of described first PMOS transistor and second PMOS transistor, do electrode in the drain electrode of described first PMOS transistor source electrode and grid, described second PMOS transistor to draw, the grid floating of described second PMOS transistor.
Further improvement is, the injection ion of the N-type ion implantation of the injection region of threshold voltage described in step 2 is phosphorus, Implantation Energy is 10Kev ~ 100Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
Further improvement is, the injection ion of the N-type ion implantation of the injection region of threshold voltage described in step 2 is arsenic, Implantation Energy is 30Kev ~ 200Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
Further improvement is; step 2 is by increase by one piece of mask; photoetching process is utilized to define the N-type ion implanted regions of described threshold voltage injection region; namely first on described silicon substrate, one deck photoresist is formed; by photoetching process by the Graphic transitions that defines in described mask on described photoresist; form photoetching offset plate figure, the N-type ion implanted regions of threshold voltage injection region described in described photoetching offset plate figure forms window, and other region is protected with photoresist.
The present invention can make second PMOS transistor threshold voltage of described P type OTP parts increase, described P type OTP parts program performance is significantly improved, and can improve programmed after the On current of whole device, add device rear differentiable current range before programming, the area of the peripheral circuit realizing OTP function can also be reduced.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing P type OTP parts structural representation
Fig. 2 is embodiment of the present invention P type OTP parts structural representation;
Fig. 3 be existing P type OTP parts not lining bias-voltage time programming before and after working curve;
Fig. 4 be existing P type OTP parts add 1V serve as a contrast bias-voltage time programming before and after working curve;
Fig. 5 is the working curve before and after the programming of embodiment of the present invention P type OTP parts.
Embodiment
As shown in Figure 2, for embodiment of the present invention P type OTP parts structural representation, silicon substrate 10 is formed N-type trap 15, to be connected the disposal programmable device formed by two PMOS transistor 11,12, first PMOS transistor 11 is as the gate transistor of OTP parts, and second PMOS transistor 12 is as the memory cell of described OTP parts.
The source electrode of described first PMOS transistor 11 comprise be formed at a p type diffusion region 191 in N trap and a P type lightly doped region 19, the drain electrode of described first PMOS transistor 11 comprises p type diffusion region 192 and the P type lightly doped region 19 be formed in N trap, described first PMOS transistor grid 17 is as the wordline of described OTP parts, and described first PMOS transistor 11 source electrode is as the source electrode of described OTP parts.
The grid 16 of described second PMOS transistor 12 is the floating boom of floating, the source electrode of described second PMOS transistor 12 comprise be formed at described p type diffusion region 192 in described N trap and a P type lightly doped region 19, the drain electrode of described second PMOS transistor 12 comprises and is formed at described p type diffusion region 193 in described N trap and a P type lightly doped region 19, the drain electrode of described second PMOS transistor 12 is as the bit line of described OTP parts, and the source electrode of described second PMOS transistor 12 and the drain electrode of described PMOS first transistor 11 share a p type diffusion region 192.Each described P type lightly doped region 19 all extends to the bottom of the described grid 13 or 16 of each described P type lightly doped region 19 correspondence and forms the second coupling regime.
The threshold voltage injection region 20 of a channel region N-type more than the channel region of described first PMOS transistor 11 of described second PMOS transistor 12, this threshold voltage injection region 20 is for increasing the absolute value of the threshold voltage of described second PMOS transistor.And after the formation of described threshold voltage injection region 20, the absolute value of the threshold voltage before the programming of described second PMOS transistor 12 is greater than the absolute value of the threshold voltage of described first PMOS transistor 11.
The injection ion of described threshold voltage injection region 20 is phosphorus or arsenic.When the injection ion of described threshold voltage injection region 20 is phosphorus, Implantation Energy is 10Kev ~ 100Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.When the injection ion of described threshold voltage injection region 20 is arsenic, Implantation Energy is 30Kev ~ 200Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
The Programming Principle of described P type OTP parts is: described second PMOS transistor 12 under programming state by the coupling capacitance between described source electrode and floating boom 16 by the voltage couples of the source electrode of described second PMOS transistor 12 on described floating boom 16, voltage on the source electrode of described second PMOS transistor 12 uploads to from the source electrode of first PMOS transistor 11, and first PMOS transistor 11 is in conducting state in programming process.Through reasonably calculating, second PMOS transistor 12 can be made under programming state to be in PMOS transistor hot electron injection optimum voltage condition under, thus have a large amount of hot electrons to be injected on described floating boom 16, change the threshold voltage of described second PMOS transistor 12, and then change OTP parts before programming after electric current, complete the function of OTP parts.
The manufacture method of embodiment of the present invention P type OTP parts comprises the steps:
Step one, the N-type trap 15 that silicon substrate 10 is formed effectively isolation and place;
Step 2, by increase by one piece of mask; photoetching process is utilized to define the N-type ion implanted regions of described threshold voltage injection region; described photoetching process is and first on described silicon substrate, forms one deck photoresist; by photoetching process by the Graphic transitions that defines in described mask on described photoresist; form photoetching offset plate figure; the N-type ion implanted regions of threshold voltage injection region described in described photoetching offset plate figure forms window, and other region is protected with photoresist.The N-type ion implanted regions of described threshold voltage injection region is the channel region in follow-up second PMOS transistor 12 that will be formed.
Form threshold voltage injection region 20 with described photoetching offset plate figure for mask carries out N-type ion implantation, this threshold voltage injection region is for increasing the absolute value of the threshold voltage of described second PMOS transistor 12.
The injection ion of described threshold voltage injection region 20 is phosphorus or arsenic.When the injection ion of described threshold voltage injection region 20 is phosphorus, Implantation Energy is 10Kev ~ 100Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.When the injection ion of described threshold voltage injection region 20 is arsenic, Implantation Energy is 30Kev ~ 200Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
Step 3, above described trap 15, form gate dielectric layer, dielectric layer forms polysilicon.Etch polysilicon, form the grid 16 of first PMOS transistor grid 13 and second PMOS transistor, define source region and the drain region of first PMOS transistor and second PMOS transistor, and make the drain region of described first PMOS transistor and the source region of second PMOS transistor be that same active area and region are identical.
Step 4, with the described polysilicon after etching and described grid 13 and 16 for carrying out autoregistration implanting p-type light dope ion, at the grid 13 of described first PMOS transistor 11 and the grid 16 both sides P type lightly doped region 19 respectively of described second PMOS transistor 12 in barrier layer.Each described P type lightly doped region 19 all extends to the bottom of the described grid 13 or 16 of each described P type lightly doped region 19 correspondence and forms the second coupling regime.
Step 5, the sidewall 17 forming the grid 13 and 16 of described first PMOS transistor 11 and described second PMOS transistor 12, the P type heavy doping ion utilizing the described sidewall 17 of each described grid 13,16 and correspondence to carry out described first PMOS transistor 11 and second PMOS transistor 11 for barrier layer inject, and annealing activates formation p type diffusion region 191,192 and 193; Formed the source electrode of described first PMOS transistor 11 by described p type diffusion region 191 and a P type lightly doped region 19, formed the drain electrode of described first PMOS transistor 11 by described p type diffusion region 192 and a P type lightly doped region 19, formed the source electrode of described second PMOS transistor 12 by described p type diffusion region 192 and a P type lightly doped region 19, formed the drain electrode of described second PMOS transistor 12 by described p type diffusion region 193 and a P type lightly doped region 19.Do electrode in the drain electrode of described first PMOS transistor source electrode and grid, described second PMOS transistor to draw, the grid floating of described second PMOS transistor.
The working curve before and after the programming of embodiment of the present invention P type OTP parts as shown in Figure 5.Different with prior art, use the technology introduced herein, can make on substrate without any need for extra voltage, just can improve the On current of whole device after having programmed, add device rear differentiable current range before programming, described P type OTP parts program performance can be made significantly to be improved.So the embodiment of the present invention only need provide a precise voltage when whole OTP control/Design of Read Circuit, thus the area of whole chip can be reduced greatly.Under making the range of application of OTP parts of the present invention can be extended to the application of low-density capacity.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. a P type OTP parts, to be connected the disposal programmable device formed by two PMOS transistor, and first PMOS transistor is as the gate transistor of OTP parts, and second PMOS transistor is as the memory cell of described OTP parts;
The source electrode of described first PMOS transistor and drain electrode comprise all respectively and are formed at a p type diffusion region in N trap and a P type lightly doped region, described first PMOS transistor grid is as the wordline of described OTP parts, and described first PMOS transistor source electrode is as the source electrode of described OTP parts;
The grid of described second PMOS transistor is the floating boom of floating, the source electrode of described second PMOS transistor and drain electrode comprise all respectively and are formed at a p type diffusion region in described N trap and a P type lightly doped region, the drain electrode of described second PMOS transistor is as the bit line of described OTP parts, and the source electrode of described second PMOS transistor and the drain electrode of described PMOS first transistor share a p type diffusion region; Each described P type lightly doped region all extends to the bottom of described grid corresponding to each described P type lightly doped region and forms the second coupling regime;
It is characterized in that: the threshold voltage injection region of a channel region N-type more than the channel region of described first PMOS transistor of described second PMOS transistor, this threshold voltage injection region is for increasing the absolute value of the threshold voltage of described second PMOS transistor.
2. P type OTP parts as claimed in claim 1, is characterized in that: the absolute value of the threshold voltage before the programming of described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
3. P type OTP parts as claimed in claim 1, it is characterized in that: the injection ion of described threshold voltage injection region is phosphorus, Implantation Energy is 10Kev ~ 100Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
4. P type OTP parts as claimed in claim 1, it is characterized in that: the injection ion of described threshold voltage injection region is arsenic, Implantation Energy is 30Kev ~ 200Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
5. a manufacture method for P type OTP parts, is characterized in that, comprises the steps:
Step one, the N-type well region forming effectively isolation on a silicon substrate and place;
Step 2, the channel region of follow-up second PMOS transistor that will be formed carry out N-type ion implantation formed threshold voltage injection region, this threshold voltage injection region is for increasing the absolute value of the threshold voltage of described second PMOS transistor;
Step 3, above described well region, form gate dielectric layer, dielectric layer forms polysilicon; Etch described polysilicon, form the grid of first PMOS transistor and second PMOS transistor, define source region and the drain region of first PMOS transistor and second PMOS transistor, and make the drain region of described first PMOS transistor identical with the region in the source region of second PMOS transistor;
Step 4, with the described polysilicon after etching for autoregistration implanting p-type light dope ion is carried out, at the grid of described first PMOS transistor and the grid both sides P type lightly doped region respectively of described second PMOS transistor in barrier layer; Each described P type lightly doped region all extends to the bottom of described grid corresponding to each described P type lightly doped region and forms the second coupling regime;
Step 5, formed the grid of described first PMOS transistor and described second PMOS transistor sidewall, utilize the described sidewall of each described grid and correspondence to carry out described first PMOS transistor for barrier layer and second PMOS transistor P type heavy doping ion is injected, and annealing activates, form source electrode and the drain electrode of described first PMOS transistor and second PMOS transistor, do electrode in the drain electrode of described first PMOS transistor source electrode and grid, described second PMOS transistor to draw, the grid floating of described second PMOS transistor.
6. the manufacture method of P type OTP parts as claimed in claim 5, it is characterized in that: the injection ion of the N-type ion implantation of the injection region of threshold voltage described in step 2 is phosphorus, Implantation Energy is 10Kev ~ 100Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
7. the manufacture method of P type OTP parts as claimed in claim 5, it is characterized in that: the injection ion of the N-type ion implantation of the injection region of threshold voltage described in step 2 is arsenic, Implantation Energy is 30Kev ~ 200Kev, and the absolute value of the threshold voltage before implantation dosage meets the programming making described second PMOS transistor is greater than the absolute value of the threshold voltage of described first PMOS transistor.
8. the manufacture method of P type OTP parts as claimed in claim 5, is characterized in that: step 2, by increase by one piece of mask, utilizes photoetching process to define the N-type ion implanted regions of described threshold voltage injection region.
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| TW578271B (en) * | 2002-12-18 | 2004-03-01 | Ememory Technology Inc | Fabrication method for flash memory having single poly and two same channel type transistors |
| US7244651B2 (en) * | 2003-05-21 | 2007-07-17 | Texas Instruments Incorporated | Fabrication of an OTP-EPROM having reduced leakage current |
| US7078761B2 (en) * | 2004-03-05 | 2006-07-18 | Chingis Technology Corporation | Nonvolatile memory solution using single-poly pFlash technology |
| CN101872764A (en) * | 2009-04-23 | 2010-10-27 | 上海华虹Nec电子有限公司 | OTP-ROM (One Time Programmable Read Only Memory), memory units thereof and manufacturing, programming and reading method thereof |
| CN102104045B (en) * | 2009-12-18 | 2013-01-09 | 上海华虹Nec电子有限公司 | P-type one time programmable (OTP) device and manufacturing method thereof |
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