CN102104045B - P-type one time programmable (OTP) device and manufacturing method thereof - Google Patents
P-type one time programmable (OTP) device and manufacturing method thereof Download PDFInfo
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- CN102104045B CN102104045B CN2009102019660A CN200910201966A CN102104045B CN 102104045 B CN102104045 B CN 102104045B CN 2009102019660 A CN2009102019660 A CN 2009102019660A CN 200910201966 A CN200910201966 A CN 200910201966A CN 102104045 B CN102104045 B CN 102104045B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 230000008878 coupling Effects 0.000 claims abstract description 35
- 238000010168 coupling process Methods 0.000 claims abstract description 35
- 238000005859 coupling reaction Methods 0.000 claims abstract description 35
- 238000007667 floating Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- 238000002513 implantation Methods 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000012010 growth Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000002784 hot electron Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The invention discloses a P-type one time programmable (OTP) device. The device is a one time programmable device formed by two P-channel metal oxide semiconductor (PMOS) transistors connected in series, wherein the first PMOS transistor is used as a gate transistor, while the second PMOS transistor is used as a storage unit, and the grid of the second PMOS transistor floats; and the source of the second PMOS transistor comprises a coupling region of the source and the floating gate formed by injection of P-type foreign ions so as to increase the coupling capacitance between the source and the gate of the second PMOS transistor. The invention also discloses a method for manufacturing the P-type OTP device, which is to form a coupling region of the source and the gate by P-type foreign ion injection in the second PMOS transistor after polycrystalline silicon is etched. In the invention,, the programming performance of the P-type OTP device is ensured to be greatly improved, the conduction current of the whole device can be improved after programming is completed, the differentiable current ranges of the device before and after programming are increased, and the area of a peripheral circuit for realizing the OTP function can be reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of P type OTP parts, the invention still further relates to the manufacture method of this P type OTP parts.
Background technology
Existing P type OTP parts is the disposal programmable device that is formed by two PMOS transistor series, first PMOS transistor is as gate transistor, in the N-type trap, form the transistorized source electrode of this first PMOS and drain electrode with p type diffusion region, described first PMOS transistor gate is as the word line of whole device, and described first PMOS transistor source is as the source electrode of whole device; Second PMOS transistor is as the memory cell of described OTP parts, described second PMOS transistor gate is floating empty, in the N-type trap, form described second transistorized source electrode of PMOS and drain electrode with p type diffusion region, described second transistorized drain electrode of PMOS is as the bit line of whole device, and first transistorized drain electrode of described second transistorized source electrode of PMOS and described PMOS shares a p type diffusion region.Existing P type OTP parts and logic process are fully compatible, and not needing increases any extra light shield, so used widely.But two transistorized source-drain electrodes of PMOS that form P type OTP parts are less with the coupling capacitance of grid, cause the programming efficiency of this device lower, and namely this device is very little in the differentiable current range in programming front and back.Existing solution is normally during reading current, and making alive on the N-type trap is to increase differentiable current range before and after the programming.This will consume the area of a large amount of OTP peripheral circuits.Although each cellar area of P type OTP parts is very little, more peripheral circuit is needing the application restric-tion of such device under the application scenario of high-density capacity.
Summary of the invention
Technical problem to be solved by this invention provides a kind of P type OTP parts, described P type OTP parts program performance is significantly improved, and can improve the afterwards On current of whole device of having programmed, increase device differentiable current range before and after programming, can also reduce the area of the peripheral circuit of realizing the OTP function; For this reason, the present invention also provides a kind of manufacture method of this P type OTP parts.
For solving the problems of the technologies described above, P type OTP parts provided by the invention, the disposal programmable device monomer structure that is formed by two PMOS transistor series, first PMOS transistor is as gate transistor, in the N-type trap, form the transistorized source electrode of this first PMOS and drain electrode with p type diffusion region, described first PMOS transistor gate is as the word line of whole device, and described first PMOS transistor source is as the source electrode of whole device; Second PMOS transistor is as the memory cell of described OTP parts, described second PMOS transistor gate is floating empty, in the N-type trap, form described second transistorized source electrode of PMOS and drain electrode with p type diffusion region, described second transistorized drain electrode of PMOS is as the bit line of whole device, and first transistorized drain electrode of described second transistorized source electrode of PMOS and described PMOS shares a p type diffusion region; Comprise described second the transistorized source electrode of PMOS that is formed by the p type impurity Implantation and the coupling regime of described second transistorized floating boom of PMOS at described second transistorized source electrode of PMOS, in order to increasing the coupling capacitance between described second transistorized source electrode of PMOS and the floating boom, the Width of the coupling regime that described P type Implantation forms does not carry out source electrode that the PMOS transistor of described P type Implantation generates and grid, drain electrode and grid in logic process the width of coupling regime is large.
The manufacture method of P type OTP parts of the present invention comprises the steps:
The present invention can make second transistorized source electrode of PMOS of described P type OTP parts and grid coupling capacitance increase, described P type OTP parts program performance is significantly improved, and can improve the afterwards On current of whole device of having programmed, increase device differentiable current range before and after programming, can also reduce the area of the peripheral circuit of realizing the OTP function.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is P type OTP parts structural representation of the present invention;
Fig. 2 is PMOS transistor hot electron Injection Current and the poor relation curve of gate source voltage;
Fig. 3 is the flow chart for the manufacture method of P type OTP parts of the present invention;
Fig. 4 is the working curve before and after the existing P type OTP parts programming;
Fig. 5 is the working curve before and after the P type OTP parts programming of the present invention.
Embodiment
As shown in Figure 1, be P type OTP parts structural representation of the present invention, the disposal programmable device that is formed by 12 series connection of PMOS transistor 11 and PMOS transistor.Wherein first PMOS transistor 11 is as gate transistor, in N-type trap 15, form source electrode 191 and the drain electrode 192 of described first PMOS transistor 11 with p type diffusion region, its grid 13 is as the word line of whole device, and described source electrode 191 is as the source electrode of whole device.Second PMOS transistor 12 is as the memory cell of this device, and its grid 16 is floating empty, forms source electrode 192 and the drain electrode 193 of described second PMOS transistor 12 in N-type trap 15 with p type diffusion region, and described drain electrode 193 is as the bit line of whole device.The drain electrode of the source electrode of described second PMOS transistor 12 and described first PMOS transistor 11 shares a P diffusion region 192, can effectively save the area of OTP parts like this, the possibility of having avoided simultaneously latch up to produce.The source electrode 192 of described second PMOS transistor 12 also comprises the source electrode 192 of described second the PMOS transistor 12 that is formed by the p type impurity Implantation and the coupling regime 18 of the floating boom 16 of described second PMOS transistor 12, in order to increasing the coupling capacitance between described second transistorized source electrode of PMOS and the floating boom, the Width of the coupling regime 18 that described P type Implantation forms does not carry out source electrode and the grid that the PMOS transistor of described P type Implantation generates in logic process, drain electrode also is large 30 nanometers of width of PMOS transistor P type lightly doped region 19 to 60 nanometers with the coupling regime 19 of grid.Coupling regime 18 degree of depth, concentration that described P type Implantation forms are identical with the degree of depth, the concentration of PMOS transistor P type lightly doped region 19, and the angle of described P type Implantation is that 7 degree are between 60 degree.The actual value system of selection of the width of the coupling regime 18 that described P type Implantation forms, concentration, the degree of depth makes described second PMOS transistor 12 reach optimal heat electronic injection condition when programming for the source electrode 192 that guarantees described second PMOS transistor 12 satisfies with the size of the coupling capacitance between the floating boom 16.The Programming Principle of described P type OTP parts is: described second PMOS transistor 12 under programming state by the coupling capacitance between its source electrode 192 and the floating boom 16 with the voltage coupling of source electrode 192 to its floating boom 16, upload to and the voltage on the described source electrode 192 is source electrode 191 from first PMOS transistor 11, first PMOS transistor 11 is in conducting state in programming process.Through reasonably calculating, can make second PMOS transistor 12 be in PMOS transistor hot electron under programming state injects under the optimum voltage condition, thereby there is a large amount of hot electrons to be injected on the floating boom 16, changed the threshold voltage of second PMOS transistor 12, and then change the electric current of OTP parts before and after programming, finish the function of OTP parts.PMOS transistor hot electron injects (CHE) and is different from nmos pass transistor, occurring in the transistor polysilicon (can reference: Matsuoka to the less situation of substrate longitudinal electric field, F.et al. " Analysis of Hot-Carrier-Induced Degradation Mode onpMOSFET ' s " .IEEE Transactions on Electron Devices, Vol 37, No.6, June 1990, pages 1487-1495.).As shown in Figure 2, be PMOS transistor hot electron Injection Current and the poor relation curve of gate source voltage, by injecting the formed Injection Current of electronics certain peak Distribution is arranged, its peak Distribution in the voltage difference of grid and source electrode is-1.2V～-0.8V, the programming efficiency of OTP directly depends on hot electron quantity and the energy of generation, and namely the programming efficiency at optimal heat electronic injection condition OTP is the highest.The present invention is by width, concentration, the degree of depth of the coupling regime 18 of the described P type Implantation formation of adjusting, thereby regulate source electrode 192 and the size of the coupling capacitance between the floating boom 16 of described second PMOS transistor 12, when this coupling capacitance makes the coupled voltages of 16 of the source electrode 192 of described second PMOS transistor 12 and floating booms poor during for the 1V left and right sides, described second PMOS transistor 12 reaches the optimal heat electronic injection when programming, can make P type OTP parts programming efficiency of the present invention the highest.
As shown in Figure 3, the flow chart for the manufacture method of P type OTP parts of the present invention comprises the steps:
Existing P type OTP parts will add the voltage higher than source at substrate usually under the state of reading, be illustrated in figure 4 as 2V.And the too high meeting of this underlayer voltage causes that reading current is excessively low, and reading circuit can't read the electric current of the OTP unit of having programmed; Underlayer voltage is excessively low, and then the OTP unit initial current before the programming is excessive, also can't distinguish the state of OTP unit.So usually will realize providing simultaneously two accurate voltages to substrate and source by very complicated peripheral reading circuit, this can consume very large chip area simultaneously.The technology of using this paper to introduce can make on the substrate without any need for extra voltage, as shown in Figure 6; This only need provide a precise voltage when wanting whole OTP control/Design of Read Circuit, reduces greatly the area of whole chip.So that the range of application of this class OTP parts is extended under the application of low-density capacity.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. P type OTP parts, the disposal programmable device that is formed by two PMOS transistor series, first PMOS transistor is as gate transistor, in the N-type trap, form the transistorized source electrode of this first PMOS and drain electrode with p type diffusion region, described first PMOS transistor gate is as the word line of whole device, and described first PMOS transistor source is as the source electrode of whole device; Second PMOS transistor is as the memory cell of described OTP parts, described second PMOS transistor gate is floating empty, in the N-type trap, form described second transistorized source electrode of PMOS and drain electrode with p type diffusion region, described second transistorized drain electrode of PMOS is as the bit line of whole device, and first transistorized drain electrode of described second transistorized source electrode of PMOS and described PMOS shares a p type diffusion region; It is characterized in that: comprise described second the transistorized source electrode of PMOS that is formed by the p type impurity Implantation and the coupling regime of described second transistorized floating boom of PMOS in described second the transistorized source electrode of PMOS position adjacent with grid, the adjacent position of grid in the transistorized source electrode of described first PMOS and drain electrode and described second transistorized drain electrode of PMOS and correspondence all is formed with a P type lightly doped region, and the width of the coupling regime of described second transistorized source electrode of PMOS is greater than the width of described P type lightly doped region.
2. P type OTP parts as claimed in claim 1, it is characterized in that: large 30 nanometers of width of the described P type of the Width of the coupling regime of described second transistorized source electrode of PMOS lightly doped region are to 60 nanometers.
3. P type OTP parts as claimed in claim 1, it is characterized in that: the coupling regime degree of depth, concentration that described P type Implantation forms are identical with the degree of depth, the concentration of PMOS transistor P type lightly doped region, and the angle of described P type Implantation is that 7 degree are between 60 degree.
4. such as claim 1 or 2 or 3 described P type OTP parts, it is characterized in that: the actual value system of selection of the width of the coupling regime that described P type Implantation forms, concentration, the degree of depth makes described second PMOS transistor reach optimal heat electronic injection condition when programming for the size of the coupling capacitance between described second the transistorized source electrode of PMOS of assurance and the floating boom satisfies.
5. P type OTP parts as claimed in claim 4 is characterized in that: described second PMOS transistor reaches optimal heat electronic injection condition when programming be that the transistorized grid coupled voltages of described second PMOS is less than the transistorized source voltage 0.8V～1.2V of described second PMOS.
6. the manufacture method of a P type OTP parts as claimed in claim 1 is characterized in that, comprises the steps:
Step 1, form N-type well region and the place of effectively isolation at silicon substrate, above described well region, form gate dielectric layer, form polysilicon at dielectric layer;
Step 2, etch polysilicon, form first PMOS transistor and second transistorized grid of PMOS, define first PMOS transistor and second transistorized source region of PMOS and drain region, and to make the transistorized drain region of described first PMOS and second transistorized source region of PMOS be same active area;
Step 3, utilize photoetching process, in described second transistorized source region of PMOS, form a photoresist window, utilize photoresist to do the barrier layer and carry out the p type impurity Implantation, remove the coupling regime that photoresist and annealing activate described second the transistorized source electrode of PMOS of formation and described second transistorized floating boom of PMOS;
Step 4, carry out described first and second PMOS transistor P type light dope Implantation, the growth of polysilicon gate sidewall as the barrier layer, utilize described polysilicon gate and sidewall to carry out described first and second PMOS transistor P type heavy doping ion as the barrier layer to inject take polysilicon gate, and annealing activates, form described first and second PMOS transistor source and drain electrode, do electrode and draw, described second transistorized grid floating of PMOS at described first PMOS transistor source and grid, described second transistorized drain electrode of PMOS.
7. the manufacture method of P type OTP parts as claimed in claim 6 is characterized in that: large 30 nanometers of width of the P type lightly doped region that the coupling regime that the Implantation of p type impurity described in the step 3 forms forms than the type of P described in step 4 light dope Implantation are to 60 nanometers.
8. the manufacture method of P type OTP parts as claimed in claim 6 is characterized in that: the implant angle of the Implantation of p type impurity described in the step 3 be 7 degree to 60 degree, the energy of injection is identical with the type of P described in step 4 light dope Implantation with dosage.
9. such as the manufacture method of claim 6 or 7 or 8 described P type OTP parts, it is characterized in that: the angle of injection, energy and dosage concrete technology parameter make described second PMOS transistor reach optimal heat electronic injection condition when the programming to be as the criterion to guarantee that coupling capacitance size between described second transistorized source electrode of PMOS and the floating boom satisfies.
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| CN102881691B (en) * | 2011-07-13 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | P-type OTP (one time programmable) device and preparing method therefore |
| CN102969318B (en) * | 2011-07-13 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | P-type one-time programmable (OTP) device and manufacturing method thereof |
| CN103021950A (en) * | 2011-09-20 | 2013-04-03 | 复旦大学 | Method for preparing embedded storage based on change-resistant gate medium |
| CN103094282B (en) * | 2011-10-28 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | P type disposal programmable device structure |
| CN103390588B (en) | 2012-05-09 | 2015-08-19 | 无锡华润上华半导体有限公司 | A kind of method making MROM memory based on otp memory |
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| CN1967878A (en) * | 2005-11-17 | 2007-05-23 | 力旺电子股份有限公司 | Operation mehtod of single-poly non-volatile memory device |
| CN101005075A (en) * | 2006-01-19 | 2007-07-25 | 力晶半导体股份有限公司 | Non-volatile storage and its producing method |
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| CN1967878A (en) * | 2005-11-17 | 2007-05-23 | 力旺电子股份有限公司 | Operation mehtod of single-poly non-volatile memory device |
| CN101005075A (en) * | 2006-01-19 | 2007-07-25 | 力晶半导体股份有限公司 | Non-volatile storage and its producing method |
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