CN109166853B - Method for forming embedded flash memory structure - Google Patents
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- 239000007924 injection Substances 0.000 claims abstract description 31
- 238000002513 implantation Methods 0.000 claims abstract description 28
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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Abstract
The invention relates to a method for forming an embedded flash memory structure, which comprises the following steps: providing a substrate, and performing a first photomask process to expose a first well injection region in a storage region and a second well injection region in a logic region; performing first ion implantation, and simultaneously performing well implantation in the first well implantation region and the second well implantation region; executing a second photomask process to expose a flash memory unit area of the storage area, wherein the flash memory unit area is positioned in the range of the first well injection area; executing second ion injection to adjust the trap ion concentration of the flash memory unit area; and forming a flash memory cell in the flash memory cell region. The formation method of the embedded flash memory structure can reduce the times of light masks and save the process cost.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a forming method of an embedded flash memory structure.
Background
Flash memory (flash) is a safe and fast memory bank, and becomes the most main carrier of data and programs in embedded systems due to a series of advantages of small volume, large capacity, low cost, no loss of power-down data and the like.
In recent years, with the rapid development of the intelligent electronic product market, the use of various MCUs (micro controller units) and socs (System-on-Chip) has been advanced to various aspects of daily life such as automotive electronics, industrial control, and medical products. And the high-performance MCU or SoC product cannot be supported by an embedded flash (E-flash) kernel. Embedded flash memory has an increasing dominance on SoC designs, both in terms of chip area, system performance and power consumption, and in terms of manufacturing yield and design cycle. Embedded flash combines existing flash with logic modules from a physical or electrical perspective, providing more versatile performance. In the embedded flash memory manufacturing process, a trap ion implantation process is required in both a CELL device area and a logic area. In the prior art, at least three photomask processes are required to inject trap ions into a CELL device region, manufacture a flash memory CELL in a CELL device region and inject the trap ions into a logic region, so that the process complexity is increased.
Disclosure of Invention
The invention provides a forming method of an embedded flash memory structure, aiming at optimizing a well injection method of a CELL device area and a logic area so as to reduce the times of a photomask and save the cost.
In order to solve the problems in the prior art, the invention provides a method for forming an embedded flash memory structure, which comprises the following steps:
providing a substrate, wherein a storage area and a logic area are defined on the substrate, and a floating gate stack layer is formed on the substrate;
executing a first photomask process to expose a first well injection region in the storage area and expose a second well injection region in the logic area;
performing a first ion implantation while performing a well implantation in the first well implantation region and the second well implantation region;
forming a control gate stack layer on the floating gate stack layer;
executing a second photomask process to expose a flash memory unit area in the storage area, wherein the flash memory unit area is positioned in the range of the first well injection area;
executing second ion implantation to adjust the trap ion concentration of the flash memory unit area; and
and forming a flash memory unit in the flash memory unit area.
Optionally, in the method for forming an embedded flash memory structure, the ions implanted during the first ion implantation and the second ion implantation include boron ions or arsenic ions.
Optionally, in the method for forming an embedded flash memory structure, the first ion implantation is performed in three batches: the energy of the first batch of ions is 270-290 kilo-electron volts, and the ion amount per square centimeter is 1 x 1013±5*1012(ii) a The energy of the ions in the second batch is 150-170 kilo electron volts, and the ion amount per square centimeter is1*1013±5*1012(ii) a The energy of the third batch of ions is 80-100 kilo electron volts, and the ion amount per square centimeter is 1 x 1012±5*1011。
Optionally, in the method for forming an embedded flash memory structure, the second ion implantation is performed in two batches: the energy of the first batch of ions is 35-45 kilo electron volts, and the ion amount per square centimeter is 6 x 1012±5*1011(ii) a The energy of the ions in the second batch is 75-85 kilo electron volts, and the ion amount per square centimeter is 9 x 1012±5*1011。
Optionally, in the method for forming the embedded flash memory structure, the floating gate stack layer is a tunneling oxide layer, a floating gate material layer, and a first mask layer deposited in sequence.
Optionally, in the method for forming the embedded flash memory structure, the control gate stack layer is an interlayer dielectric layer, a control gate material layer and a second mask layer deposited in sequence.
Optionally, in the method for forming the embedded flash memory structure, the interlayer dielectric layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, which are sequentially formed by stacking.
Optionally, in the method for forming an embedded flash memory structure, after the first ion implantation is performed and before the interlayer dielectric layer is deposited, the method further includes the following steps:
the first mask layer is removed.
Optionally, in the method for forming the embedded flash memory structure, the storage region is used to form a flash memory unit, and the logic region is used to form a high-voltage device and/or a low-voltage device, where a voltage range of the high-voltage device is 4.5V to 5.5V, and a voltage range of the low-voltage device is 1.2V to 1.8V.
Optionally, in the method for forming the embedded flash memory structure, the flash memory unit includes a split gate flash memory unit, and the high-voltage device includes a 5V NMOS device.
In the forming method of the embedded flash memory structure provided by the invention, a first trap injection area of the storage area and a second trap injection area of the logic area are simultaneously exposed through a first photomask process, first ion injection is simultaneously executed in the first trap injection area and the second trap injection area so as to complete the trap injection process of the logic area, the trap injection process of the storage area is partially completed, and then the concentration of trap ions in the flash memory unit area of the storage area is adjusted through a second photomask process for manufacturing a flash memory unit so that the trap ion concentration of the flash memory unit area reaches the requirement; and finally forming a flash memory unit in the flash memory unit area. Therefore, the trap injection process of the storage area and the logic area can be realized through two photomask processes, the photomask times are reduced, and the process cost is saved.
Drawings
Fig. 1 is a flowchart of a method for forming an embedded flash memory structure according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view illustrating a method for forming an embedded flash memory structure after forming a gate stack layer according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a first ion implantation region according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view illustrating a control gate stack layer formed by a method for forming an embedded flash memory structure according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a second ion implantation region provided in accordance with an embodiment of the present invention;
fig. 6 is a schematic cross-sectional view illustrating a method for forming an embedded flash memory structure after forming a device structure according to an embodiment of the present invention;
wherein, 10-substrate; 11-a storage area; 12-a logical area; 13-shallow trench isolation structures; 20-floating gate stack layer; 21-tunneling oxide layer; 22-a layer of floating gate material; 23-a first mask layer; 30-a photoresist layer; 31-a first ion implantation region; 32-a second ion implantation region; 40-a control gate stack; 41-interlayer dielectric layer; 42-a control gate material layer; 43-second mask layer; 50-flash memory cell.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
The invention provides a method for forming an embedded flash memory structure, and fig. 1 is a flow chart of the method for forming the embedded flash memory structure provided by the embodiment of the invention. Referring to fig. 1, the method for forming the embedded flash memory structure includes the following steps:
s1: providing a substrate, wherein a storage area and a logic area are defined on the substrate, and a floating gate stack layer is formed on the substrate;
s2: executing a first photomask process to expose a first well injection region in the storage area and expose a second well injection region in the logic area;
s3: performing a first ion implantation while performing a well implantation in the first well implantation region and the second well implantation region;
s4: sequentially forming a control gate stacking layer above the floating gate stacking layer;
s5: executing a second photomask process to expose a flash memory unit area in the storage area, wherein the flash memory unit area is positioned in the range of the first well injection area;
s6: executing second ion implantation to adjust the trap ion concentration of the flash memory unit area; and
s7: and forming a flash memory unit in the flash memory unit area.
In the invention, a first trap injection area of the storage area and a second trap injection area of the logic area are simultaneously exposed through a first photomask process, first ion injection is simultaneously executed in the first trap injection area and the second trap injection area to complete the trap injection process of the logic area, the trap injection process of the storage area is partially completed, and then the concentration of trap ions in a flash memory unit area of the storage area is adjusted through a second photomask process for manufacturing a flash memory unit, so that the trap ion concentration of the flash memory unit area reaches the requirement; and finally forming a flash memory unit in the flash memory unit area. Therefore, the trap injection process of the storage area and the logic area can be realized through two photomask processes, the photomask times are reduced, and the process cost is saved.
The method for forming the embedded flash memory structure according to the embodiment of the invention is further described with reference to fig. 2 to 6.
Fig. 2 is a schematic cross-sectional view illustrating a method for forming an embedded flash memory structure after forming a gate stack layer according to an embodiment of the invention. Referring to fig. 2, step S1 is performed: providing a substrate 10, defining a storage region 11 and a logic region 12 on the substrate 10, and forming a floating gate stack layer 20 on the substrate 10.
Specifically, the material of the substrate 10 may be silicon, germanium, silicon carbide, or the like, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be other materials, such as a group iii or v compound such as gallium arsenide. In other embodiments, the substrate 10 may include a doped epitaxial layer, which may be implanted with certain dopant particles to change electrical parameters according to design requirements. In this embodiment, the substrate 10 is an undoped or lightly p-type doped semiconductor substrate comprising silicon. In general, during the manufacture of a flash memory structure, the substrate 10 is divided into a memory area 11 and a logic area 12 to implement the functions of the flash memory structure.
A floating gate stack layer 20 is formed on the substrate 10, and the floating gate stack layer 20 includes a tunneling oxide layer 21, a floating gate material layer 22, and a first mask layer 23 deposited in sequence.
Typically, a shallow trench isolation structure 13 is formed in the substrate 10. The shallow trench isolation structure 13(STI) comprises silicon oxide or other suitable material as an isolation dielectric. The fabrication of the shallow trench isolation structure 13 can be performed by those skilled in the art according to the prior art. As one example, forming an STI includes forming an opening in the substrate 10 by a photolithography or etching process and filling the opening with one or more isolation dielectrics.
In this embodiment, the tunnel oxide layer 21 includes silicon oxide and/or nitrogen-doped silicon oxide, the floating gate material layer 22 includes polysilicon, and the floating gate material layer 22 may also include doped ions. The first mask layer 23 includes silicon nitride, and the first mask layer 23 may protect the floating gate material layer 22.
In this embodiment, the memory area 11 is used to form an embedded flash memory. Specifically, for example, a split gate flash memory may be formed in the storage area 11. The logic region 12 is used to form logic devices, such as logic transistors, which may be high voltage field effect transistors and/or low voltage field effect transistors. The voltage range of the high-voltage field effect transistor is 4.5V-5.5V, and the voltage can be 4.5V, 4.7V, 4.9V, 5V, 5.1V, 5.3V, 5.5V and the like. The voltage range of the low-voltage field effect transistor is 1.2V-1.8V, and the voltage can be 1.2V, 1.4V, 1.5V, 1.6V, 1.8V and the like. In this embodiment, the logic transistor is, for example, a 5VNMOS device. In further embodiments, the substrate 10 may also include other regions besides the memory region 11 and the logic region 12.
Fig. 3 is a schematic cross-sectional view of a first ion implantation region according to an embodiment of the present invention. Referring to fig. 3, in step S2, a first masking process is performed to expose a first well implant region in the storage region 11 and a second well implant region in the logic region 12. The first well implantation region and the second well implantation region are first ion implantation regions 31.
Still referring to fig. 3, next, step S3 is performed to perform a first ion implantation while performing a well implantation in the first well implantation region and the second well implantation region. The ions implanted by the first ion implantation can be boron ions, arsenic ions or phosphorus ions, and preferably boron ions are adopted. Furthermore, the ion implantation of the first well implantation region and the second well implantation region is simultaneous implantation, and the implantation energy and concentration are equal.
In the method for forming an embedded flash memory structure provided in this embodiment, the boron ions of the first ion implantation may be implanted in three batches, wherein the energy of the first batch of ions is 270 to 290 kev, preferably 280 kev, and the amount of ions per square centimeter is 1 x 1013±5*1012Preferably at a concentration of 1 x 1013Per square centimeter; the energy of the second batch of ions is 150-170 keV, preferably 160 keV, and the amount of ions per square centimeter is 1 x 1013±5*1012Preferably at a concentration of 1 x 1013Per square centimeter; the energy of the third batch of ions is 80-100 keV, preferably 90 keV, and the amount of ions per square centimeter is 1 x 1012±5*1011Preferably at a concentration of 1 x 1012Per square centimeter.
After the first ion implantation, the present embodiment may further include the following steps: the first masking layer 23 is removed.
Fig. 4 is a schematic cross-sectional view illustrating a method for forming an embedded flash memory structure after forming a control gate stack layer according to an embodiment of the invention. Referring to fig. 4, step S4 is executed to form a control gate stack 40 on the floating gate stack 20.
The control gate stack layer 40 is an interlayer dielectric layer 41, a control gate material layer 42 and a second mask layer 43 deposited in sequence. The interlayer dielectric layer 41 may include a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, which are sequentially stacked. The control gate material layer 42 comprises polysilicon and the floating gate material layer 22 may also comprise dopant ions. The second mask layer 43 may be silicon nitride.
Fig. 5 is a schematic cross-sectional view of a second ion implantation region according to an embodiment of the present invention. Referring to fig. 5, step S5 is executed to perform a second masking process to expose a flash memory cell 50 area in the storage area 11, where the flash memory cell 50 area is located within the first well implantation area. A dry etch may be used to expose the flash memory cell 50 area. In this embodiment, the control gate stack layer 40 is coated with the photoresist layer 30 and patterned, and the second mask layer 43 not covered by the photoresist layer 30 is etched to form the flash memory cell 50 region.
Since the required trap ion concentrations of the storage region 11 and the logic region 12 are different, the trap ion concentration of the storage region 11 still needs to be adjusted after the first ion implantation. In this embodiment, the trap ion concentration of the storage area 11 is adjusted by selecting the area of the flash memory unit 50 formed by the second mask process, so that the requirement of the trap ion concentration of the storage area 11 can be met, and the number of times of photolithography (i.e., the number of masks/reticles is reduced) can be reduced.
Specifically, in this embodiment, before the flash memory cell 50 is fabricated in the flash memory cell 50 area, step S6 is performed to perform a second ion implantation to adjust the trap ion concentration of the flash memory cell 50 area. The flash memory cell 50 region is the second ion implantation region 32.
The ions implanted by the second ion implantation may be boron ions, arsenic ions or phosphorus ions, and boron ions are preferably used. Further, the second ion implantation may be performed in two batches; wherein the energy of the first batch of ions is 35-45 keV, preferably 40 keV, and the amount of ions per square centimeter is 6 x 1012±5*1011The concentration is preferably 6 x 1012Per square centimeter; the energy of the second batch of ions is 75-85 keV, preferably 80 keV, and the amount of ions per square centimeter is 9 x 1012±5*1011Preferably, the concentration is 9 x 1012Per square centimeter.
Fig. 6 is a schematic cross-sectional view illustrating a device structure formed by a method for forming an embedded flash memory structure according to an embodiment of the present invention. Referring to fig. 6, after adjusting the trap ion concentration of the storage region 11, step S7 is performed to form a flash memory cell 50 in the flash memory cell 50 region. The flash memory cell 50 is, for example, a split-gate flash memory cell, and specifically, referring to fig. 6, the split-gate flash memory cell includes two memory bit units having a common word line. The manufacturing method of the split gate flash memory unit can be implemented by those skilled in the art with reference to the prior art, and is not described herein again.
In summary, in the method for forming an embedded flash memory structure provided by the present invention, the first well implantation region of the storage region and the second well implantation region of the logic region are simultaneously exposed through the first mask process, and the first ion implantation is simultaneously performed in the first well implantation region and the second well implantation region to complete the well implantation process of the logic region, and partially complete the well implantation process of the storage region, and then the concentration of the well ions in the flash memory cell region of the storage region is adjusted through the second mask process for fabricating the flash memory cell, so that the well ion concentration in the flash memory cell region meets the requirement; and finally forming a flash memory unit in the flash memory unit area. Therefore, the trap injection process of the storage area and the logic area can be realized through two photomask processes, the photomask times are reduced, and the process cost is saved.
The foregoing embodiments are merely illustrative of the principles of the invention and its efficacy, and are not to be construed as limiting the invention. Those skilled in the art can make various changes, substitutions and alterations to the disclosed embodiments and technical contents without departing from the spirit and scope of the present invention.
Claims (8)
1. A method for forming an embedded flash memory structure is characterized by comprising the following steps:
providing a substrate, wherein a storage area and a logic area are defined on the substrate, and a floating gate stack layer is formed on the substrate;
executing a first photomask process to expose a first well injection region in the storage area and expose a second well injection region in the logic area;
performing a first ion implantation while performing a well implantation in the first well implantation region and the second well implantation region;
forming a control gate stack layer on the floating gate stack layer;
executing a second photomask process to expose a flash memory unit area in the storage area, wherein the flash memory unit area is positioned in the range of the first well injection area;
executing second ion implantation to adjust the trap ion concentration of the flash memory unit area; and
forming a flash memory unit in the flash memory unit area;
the ions implanted during the first ion implantation and the second ion implantation comprise boron ions or arsenic ions, and the first ion implantation is performed in three batches: the energy of the first batch of ions is 270-290 kilo-electron volts, and the ion amount per square centimeter is 1 x 1013±5*1012(ii) a The energy of the ions in the second batch is 150-170 kilo-electron volts, and the ion amount per square centimeter is 1 x 1013±5*1012(ii) a The energy of the third batch of ions is 80-100 kilo electron volts, and the ion amount per square centimeter is 1 x 1012±5*1011。
2. The method of claim 1, wherein the second ion implantation is performed in two batches: the energy of the first batch of ions is 35-45 kilo electron volts, and the ion amount per square centimeter is 6 x 1012±5*1011(ii) a The energy of the ions in the second batch is 75-85 kilo electron volts, and the ion amount per square centimeter is 9 x 1012±5*1011。
3. The method of claim 1, wherein the floating gate stack layer is a tunnel oxide layer, a floating gate material layer, and a first mask layer deposited in sequence.
4. The method of claim 3, wherein the control gate stack layer is an interlayer dielectric layer, a control gate material layer and a second mask layer deposited in sequence.
5. The method of claim 4, wherein the interlayer dielectric layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer sequentially stacked.
6. The method of claim 4, wherein the step of performing the first ion implantation before depositing the interlevel dielectric layer further comprises the steps of:
the first mask layer is removed.
7. The method of claim 1, wherein the storage region is used to form a flash memory cell and the logic region is used to form a high voltage device and/or a low voltage device, wherein the voltage range of the high voltage device is 4.5V to 5.5V and the voltage range of the low voltage device is 1.2V to 1.8V.
8. The method of claim 7, wherein the flash memory cell comprises a split gate flash memory cell and the high voltage device comprises a 5V NMOS device.
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| KR20050110272A (en) * | 2004-05-18 | 2005-11-23 | 주식회사 하이닉스반도체 | Method of ion implantation for controling threshold voltage in a flash memory device |
| KR20060079004A (en) * | 2004-12-31 | 2006-07-05 | 동부일렉트로닉스 주식회사 | Method for improving the ono charicateristics of embedded flash memory |
| CN106340520A (en) * | 2016-10-11 | 2017-01-18 | 上海华虹宏力半导体制造有限公司 | Formation method of semiconductor device |
| CN108054167A (en) * | 2017-12-08 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | The production method of embedded flash memory |
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