JPH07326684A - Nonvolatile memory cell array - Google Patents

Abstract

PURPOSE:To surely write and erase data by arranging a plurality of nonvolatile memory cells in the source-drain direction and the direction intersecting the source.drain direction. CONSTITUTION:Each of the drain/source region 30A and the source/drain region 30B of nonvolatile memory cells adjacent to the direction intersecting the source drain direction is continuous. The drain/source region 30A of the nonvolatile memory cell is common to the source/drain region 30B of the nonvolatile memory cell adjacent to the source-drain direction. The source/drain region 30B of the nonvolatile memory cell is a region in common with the source/drain region 30A of other nonvolatile memory cell adjacent to the source-drain direction. The drain/source region 30A and the source/drain region 30B correspond to bit lines Di, Di+2 and bil lines Di+1, respectively. Thereby the writing and the erasing of data (extraction and injection of electrons) can be surely performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory cell source,
The present invention relates to a nonvolatile memory cell array having a novel structure capable of high integration, which does not require formation of a normal element isolation region such as LOCOS in the drain direction.

[0002]

2. Description of the Related Art When forming an integrated circuit, a LOC is usually used.
It is necessary to form an element isolation region such as an OS (Local Oxidation of Silicon). From the viewpoint of improving the degree of integration of semiconductor cells, it is desirable to make the area of the element isolation region as small as possible.

As one of means for improving the integration degree of such a memory cell, a buried bit line is buried below a gate portion made of polysilicon, and an element isolation region is not provided in one direction between memory cells. There is a method.

With reference to FIGS. 21, 22 and 23, the structure of a semiconductor memory cell composed of a mask ROM of the embedded bit line system and its operating principle will be described. FIG. 21 is a plan view showing a case where each region of the semiconductor device is projected on a certain plane. 22A is a schematic partial cross-sectional view of the semiconductor device taken along the line AA of FIG. Further, FIG. 22B shows a line BB in FIG.
2 is a schematic partial cross-sectional view of the semiconductor device taken along FIG.
21C is a schematic partial cross-sectional view of the semiconductor device taken along the line CC of FIG.

The method of manufacturing a semiconductor memory cell in this semiconductor device is in the reverse order of the usual method. That is, first,
A source / drain region that also serves as a bit line is formed on a silicon semiconductor substrate by an ion implantation method, then a gate oxide film is formed, and then boron ion implantation is performed to adjust the gate threshold voltage. A gate electrode portion made of polysilicon and also used as a word line is formed. Due to the accelerated oxidation, the oxide film becomes thicker on the source / drain regions,
It is advantageous in terms of pressure resistance. Note that accelerated oxidation refers to a phenomenon in which a thick oxide film is formed in a region of a silicon semiconductor substrate containing a large amount of impurities as compared with other regions. Next, boron is ion-implanted to form an element isolation region to prevent current leakage caused by charge reversal on the surface of the silicon semiconductor substrate between word lines. Since there is no element isolation region having a LOCOS structure in the source / drain direction, this semiconductor memory cell structure has a high degree of integration.

Each semiconductor memory cell is an enhanced type, and the threshold value of each semiconductor memory cell is set to either V _th1 or V _th2 by changing the boron ion implantation conditions for adjusting the gate threshold voltage. . However, for example, V _th1 <3 (V) <V _th2 . The difference (V _th1 or V _th2 ) between the thresholds of the semiconductor memory cells is 1
Corresponds to data of / 0.

Referring to FIG. 23, the operation of the mask ROM to which such an embedded bit line system is applied will be described below. The semiconductor memory cell is operated bit by bit. That is, when reading the data of a semiconductor memory cell (denoted by circles dotted lines in FIG. 23) (corresponding to the drain region) one of the bit lines BL ₃ of the semiconductor memory cells and more to the right bit line BL ₃ All the bit lines BL ₄ ... Which are located are set to 5V, for example. On the other hand, the other bit line BL ₂
(Corresponding to the source region) and the bit line BL ₂ all left bit lines BL ₁ · · · than, for example, 0V. Then, the word line WL ₂ (corresponding to the gate electrode portion) of the semiconductor memory cell from which data is to be read is set to 3V, for example, and the other word lines WL ₁ , WL ₃ ... Are set to 0V, for example. In this way, whether the current flows between the drain and source regions of the semiconductor memory cell from which data should be read
/ 0 data can be determined.

The structure of a flash EEPROM to which such a buried bit line system is applied is schematically shown in the partial cross-sectional view of FIG. A circuit diagram of the memory cell array is shown in FIG. A schematic plan view of this flash EEPROM is almost the same as FIG. FIG. 24A is a schematic partial cross-sectional view of the semiconductor device taken along a line similar to the line AA of FIG. Further, FIG. 24B is a schematic partial cross-sectional view of the semiconductor device taken along a line similar to the line BB of FIG. 21, and FIG.
FIG. 22 is a schematic partial cross-sectional view of the semiconductor device taken along a line similar to the line C-C of FIG. 21.

Data reading is similar to the operation of the mask ROM described with reference to FIG. Data erasing (injection of electrons into the floating gate) can be performed simultaneously on all semiconductor memory cells by setting the control gate to a high voltage and using a tunnel current. On the other hand, writing data (drawing electrons) requires some ingenuity. That is,
The electrons of the floating gate of the semiconductor memory cell in which data is to be written are drawn out to one bit line (drain region) of the semiconductor memory cell by a tunnel current. At this time, the floating of the adjacent semiconductor memory cell connected to this bit line We must prevent electrons from being extracted from the gate.

For this purpose, for example, the document "An Asymmetr
ical Offset Source / Drain Structure for Virtual Gro
und Array Flash Memory with DINOR Operation ", M. O
hi, et al. Technical Digest of 1992 Symposium on VL
SI Technology, June, 1993, Kyoto has an offset region on the source side. A schematic partial sectional view of such a semiconductor memory cell is shown in FIG. 26A, and a circuit diagram of the memory cell array is shown in FIG. 26B. For example, when electrons are extracted from the floating gate of the memory cell marked with “*” in FIG. 26B, the offset region is provided on the source side of the memory cell adjacent to the right of this memory cell. Electrons are not extracted from the floating gate of the adjacent memory cell. However, in the memory cell having such a structure,
The electrons are not extracted from the entire surface of the floating gate, which is the charge storage layer, but from a part of the floating gate.

[0011]

In the manufacturing process of the semiconductor memory cell having the offset region disclosed in this document, the insulating film under the control gate inevitably becomes thick, and punch-through in this region occurs. Is a problem.

Although the control gate is set to a negative potential (-9 V) during writing, the impurity concentration in the channel region is offset at 2 × 10 ¹⁷ cm ^-3 in consideration of variations in the characteristics of the semiconductor memory cell such as the threshold during manufacturing. The region length is required to be 200 nm or more. For this reason,
The size of one semiconductor memory cell is larger than that required for a normal one transistor, although it is composed of one transistor. Furthermore, in practice, high density n-type impurity ion implantation is required to form the source / drain regions, making it difficult to achieve high density, and in the submicron device region of 0.5 μm rule or less. The semiconductor memory cell cannot be made smaller.

Furthermore, in the structure of the non-volatile memory cell array disclosed in the literature, it is unavoidable to perform a so-called write operation in which electrons are extracted from the floating gate to the drain region. Therefore, the structure of the non-volatile memory cell array disclosed in the literature is a semiconductor memory cell that takes in or out electrons or holes from the channel region (for example, MNOS memory, MONOS memory, floating gate non-volatile type that injects or draws out electrons from the channel region). It cannot be applied to memory cells).

In addition, in FIG. As shown in FIG. 7, the configuration of the non-volatile memory cell array disclosed in the literature is a configuration in which electrons are extracted from a part of the floating gate, so that the number of rewrites is limited (up to 10,000 times).
There is. In order to avoid this, it is necessary to have a semiconductor memory cell structure (including floating type) in which electrons are taken in and out from the channel region.

In addition, since the offset region functions as a resistor in series with the channel region, the current driving capability of the memory transistor is reduced, which is disadvantageous for high speed operation. This tendency is remarkable especially in the region where the operating voltage is low, and is disadvantageous in reducing the voltage. In other words, it goes against the current trend of the technology of high speed and low operating voltage.

As described above, in order to cope with the miniaturization of the non-volatile memory cell array, it is indispensable to provide a new high-density non-volatile memory cell array which does not require the formation of the offset region.

Therefore, an object of the present invention is that the formation of an offset region is not necessary, and that data writing and erasing (electron extraction and electron injection) can be surely executed, and further, high speed and low operating voltage are required. It is to provide a new high density non-volatile memory cell array that can meet the demand. A further object of the present invention is to provide a non-volatile memory cell array that allows electrons to be taken in and out of the channel region. A further object of the present invention is to provide a non-volatile memory cell array capable of reading data from a non-volatile memory cell at high speed.

[Means for Solving the Problems]

The above objects are (A) a drain / source region and a source / drain region, (B) a semiconductor channel forming region sandwiched between the drain / source region and the source / drain region, and (C) the A first insulating film including a charge storage layer and a first insulating film formed on the semiconductor channel formation region;
A first laminated structure comprising a conductive gate of
A plurality of non-volatile memory cells each composed of a second laminated structure composed of the insulating film and the second conductive gate, arranged in the source / drain direction and in a direction intersecting with the source / drain direction. The drain / source regions and the source / drain regions of the non-volatile memory cells that are adjacent to each other in the direction intersecting the line are continuous, and the drain / source regions of the non-volatile memory cells are adjacent to each other in the source / drain direction. The source / drain region of the cell is a common region, and the source / drain region of the non-volatile memory cell is a drain / source region of another non-volatile memory cell adjacent in the source / drain direction. The first conductive gate of the nonvolatile memory cell is electrically connected in the source / drain direction, and each nonvolatile memory cell has a first conductive gate. A second conductive gate of Riseru can be achieved by the non-volatile memory cell array of the present invention characterized by being electrically connected in a direction intersecting the source and drain direction.

In the non-volatile memory cell array of the present invention, the second conductive gate is electrically connected by a plurality of non-volatile memory cells in a direction intersecting with the source / drain direction. It is preferable that at least every other nonvolatile memory cell is electrically connected in the drain direction.

Further, in the nonvolatile memory cell array of the present invention, the drain / region is formed in the semiconductor channel formation region located between the first conductive gate and the second conductive gate.
A mode in which an intermediate region having the same conductivity type as the source region and the source / drain region is formed can be included.

In the nonvolatile memory cell array of the present invention, the first insulating film including the charge storage layer can be formed of three layers of an oxide film, a nitride film and an oxide film (so-called ONO film). Alternatively, the first insulating film including the charge storage layer can be composed of three layers of an oxynitride film, a nitride film and an oxide film. Furthermore, the first insulating film including the charge storage layer can be composed of two layers of an oxide film and a nitride film or two layers of an oxynitride film and a nitride film. Furthermore,
The first insulating film including the charge storage layer has three layers (so-called floating gate structure) including an insulating film, a silicon thin film, and an insulating film.
Can consist of: Further, the first insulating film including the charge storage layer can be composed of three layers of an insulating film, a silicon thin film, and a multi-layer insulating film (for example, NO, ONO, etc.).

[0022]

In the nonvolatile memory cell constituting the nonvolatile memory cell array of the present invention, the first stacked structure body corresponding to the memory transistor and the second stacked structure body corresponding to the selection transistor are on the semiconductor channel formation region. Is formed in. Moreover, the drain / source region corresponding to the bit line is a region common to the source / drain regions of the nonvolatile memory cells adjacent in the source / drain direction, while the source / drain region corresponding to the bit line is the source / drain region. Since it is a common region with the drain / source region of another nonvolatile memory cell adjacent in the drain direction,
The size of the memory cell can be made smaller than that of the conventional nonvolatile memory cell composed of two transistors, that is, a memory transistor and a selection transistor.

Further, each of the drain / source regions and the source / drain regions (which correspond to bit lines) of the non-volatile memory cells adjacent to each other in the direction intersecting with the source / drain direction are continuous, so-called embedded bits. Since the line method is used, the LOCO
The semiconductor device can be processed with high accuracy without causing a large step such as S.

Furthermore, unlike the non-volatile memory cell disclosed in the above-mentioned document, the non-volatile memory cell has a second laminated structure corresponding to the selection transistor, and the second laminated structure has a second laminated structure. By the on / off operation, writing and erasing of data (electron extraction and injection) can be surely executed. Furthermore, since there is no offset region that acts as a series resistance in the channel region, it is possible to provide a high density nonvolatile memory cell array that can satisfy the requirements of high speed and low operating voltage.

Further, in the present invention, the second laminated structure corresponding to the selection transistor is provided. Therefore,
The potential of the channel region of a non-volatile memory cell is the potential of the channel region of a non-volatile memory cell that is adjacent in the source / drain direction and has a source / drain region that is common to the drain / source region of the non-volatile memory cell. Can be different. As a result, electrons (carriers) can be taken in and out from the channel region of the nonvolatile memory cell.

In a preferred mode of the non-volatile memory cell array of the present invention, the second conductive gate is electrically connected by a plurality of non-volatile memory cells in a direction intersecting the source / drain direction. At least every other nonvolatile memory cell is electrically connected in the source / drain direction. As a result, as will be described later in detail, the data in the nonvolatile memory cell can be read, for example, in every other second conductive gate, as shown in FIG.
It becomes possible to read data faster than the conventional nonvolatile memory cell array shown in FIG. Further, if the even-numbered non-volatile memory cell and the odd-numbered non-volatile memory cell are considered to be memory cells of different array blocks virtually, all the bits from the external terminals can be treated as one array block at a time. The speed equivalent to writing / erasing and reading can be obtained.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile memory cell array according to the present invention will be described below with reference to the drawings.

(Embodiment 1) A circuit diagram of a nonvolatile memory cell array of the present invention is shown in FIG. Further, FIG. 2 is a plan view showing a case where each region of the nonvolatile memory cell array of the first embodiment is projected on a certain plane. Further, FIG. 3 shows a schematic partial cross-sectional view of the two nonvolatile memory cells taken along the line III-III in FIG.

The non-volatile memory cell array of the present invention comprises a plurality of non-volatile memory cells arranged in the source / drain direction and in the direction intersecting with the direction. For example, in FIG.
At bit lines D _{j + 1} and D _{j + 2 and} word line WW
One non-volatile memory cell (“*”) specified by _{i, 2}
(Marked) will be described below. In addition, "D" was used as a symbol that means a bit line, and "WW" was used as a symbol that means a word line. Further, “BW” is used as a symbol that means a select gate line described later. In the embodiment, one block is composed of k non-volatile memory cells, the subscript “i” means the block in the i-th row, and the subscript “j” means the block in the j-th column. Further, the subscript "k" is added to the k-th non-volatile memory cell in one block.

As shown in FIG. 3, one nonvolatile memory cell includes (A) drain / source region 30A and source / drain region 30B, and (B) drain / source region 30A and source / drain region 30B. The semiconductor channel forming region CH is sandwiched and (C) the first laminated structure TR ₁ and the second laminated structure TR ₂ are formed on the semiconductor channel forming region CH. First laminated structure TR ₁
Is composed of the first insulating film 10 including the charge storage layer 10B and the first conductive gate G1. On the other hand, the second laminated structure TR ₂ is composed of the second insulating film 20 and the second conductive gate G2. In addition, reference number 10C
Is an insulating film, and reference numeral 32 is an interlayer insulating layer.

The first laminated structure TR ₁ functions as a so-called memory transistor, and the second laminated structure TR ₂ functions as a so-called select transistor.

The drain / source regions 30A and the source / drain regions 30B of the non-volatile memory cells adjacent to each other in the direction intersecting the source / drain direction are continuous. That is, as shown in FIGS. 1, 2 and 3, the bit lines D _j , D _{j + 1} ... Correspond to the drain / source regions or the source / drain regions 30A or 30B, which are respectively shown in FIG. As shown in FIG. 5, the plurality of non-volatile memory cells adjacent to each other in the direction intersecting the source / drain direction are continuous.

The drain / source region 30A of the non-volatile memory cell is the source of the non-volatile memory cell adjacent to the source / drain direction (non-volatile memory cell adjacent to the right side in FIGS. 1, 2 and 3). Source / drain region 30B of the non-volatile memory cell is a common region with the other non-volatile memory cell (the left side in FIGS. 1, 2 and 3). It is a common region with the drain / source region 30A of the adjacent non-volatile memory cell). In other words, the drain / source region 30A of the nonvolatile memory cell defined by the bit lines D _j and D _{j + 1} is the bit line D
_This corresponds to _{j + 1} , and the source / drain region 30B corresponds to D _j . On the other hand, the drain / source region 30A of the nonvolatile memory cell defined by the bit lines D _{j + 1} and D _{j + 2} corresponds to the bit line D _{j + 2} , and the source / drain region 30B corresponds to the bit line D _{j +.} Equivalent to ₁ .

The first conductive gate G1 of each nonvolatile memory cell is electrically connected in the source / drain direction. That is, each of the first conductive gates G1 is continuous across a plurality of non-volatile memory cells adjacent in the source / drain direction. In the first embodiment, the word line WW is used.
_{i, 1} , WW _{i, 2} ... On the other hand, the second conductive gate G2 of each nonvolatile memory cell is electrically connected in a direction intersecting the source / drain direction. That is, each of the second conductive gates G2 is continuous across a plurality of (for example, 2k) non-volatile memory cells adjacent to each other in the direction intersecting the source / drain direction.

Further, as shown in FIGS. 1 and 2, at least every other nonvolatile memory cell in the source / drain direction (in the first embodiment, every other nonvolatile memory cell in the source / drain direction). , The second conductive gate G2
Are electrically connected by the select gate lines BW _i , BW _{i + 1} ... The plurality of (one block) non-volatile memory cells are shown by being surrounded by a chain line in FIG. Further, FIG. 7 illustrates a relationship between the plurality of blocks, the second conductive gate G2, and the select gate line BW as a schematic circuit diagram.

In FIGS. 4, 5 and 6, the line IV-I of FIG.
V is a schematic partial cross-sectional view of a plurality of nonvolatile memory cells along line V-V and line VI-VI. FIG. 4 is a schematic partial cross-sectional view when a plurality of nonvolatile memory cells are cut along a vertical plane including the second conductive gate G2 in a direction intersecting the source / drain direction. Figure 5 shows the source
The first laminated structure TR ₁ in the direction intersecting the drain direction
FIG. 9 is a schematic partial cross-sectional view when a plurality of nonvolatile memory cells are cut along a vertical plane including (corresponding to a memory transistor). The first stacked structure TR ₁ (corresponding to a memory transistor) arranged in a direction intersecting the source / drain direction is electrically isolated by an element isolation region 31. FIG. 6 shows the drain / source region or the source / drain in the direction crossing the source / drain direction.
FIG. 6 is a schematic partial cross-sectional view when a plurality of nonvolatile memory cells are cut along a vertical plane including a drain region 30 (bit line). The first conductive gate G1 extends in the direction perpendicular to the paper surface of FIGS. 4, 5 and 6, and is drawn including the three first conductive gates G1.

The operation of the non-volatile memory cell array having the circuit shown in FIG. 1 will be described below. The voltages described below are all examples, and one nonvolatile memory cell defined by the bit lines D _{j + 1} and D _{j + 2 and the} word line WW _{i, 2} (marked with “*” in FIG. 1). Access) will be described. In addition, this one non-volatile memory cell,
Hereinafter, it is also referred to as an access memory cell. Although the first laminated structure TR ₁ corresponding to the memory transistor is of the MONOS type, it may be of the floating gate type or the like. In this case, the applied voltage may be changed according to the structure of the first laminated structure TR ₁ .

[Extraction of Electrons from _First Laminated Structure TR ₁ (Memory Transistor)] In the nonvolatile memory cell array of the present invention, all the nonvolatile memory cells are first brought to the "1" state. That is, the first laminated structure T
Extracts electrons from R ₁ (memory transistor). In this case, the first laminated structure TR ₁ (memory transistor)
Electrons are extracted from the bit line to the bit line in units of word lines, and the nonvolatile memory cells connected to the word lines are set to the "1" state. Therefore, the word line WW _{i, 2}
Is set to, for example, −6V, and 0V is set except for this word line.
All the bit lines are set to 0V, or if that is insufficient, only the bit lines of the nonvolatile memory cells connected to the word line WW _{i, 2} are set to have a necessary voltage (for example, 1V). On the other hand, all the second laminated structure TR ₂ (selection transistor) is turned off. What is important here is that the first stacked structure body TR ₁ (memory transistor) is not made to be a depletion type by drawing out too many electrons. However, even if it becomes a depletion type, by appropriately selecting the potential of the bit line of the non-volatile memory cell to be kept in the state of “1” at the time of writing the next “0”,
The gate threshold voltage of the first stacked structure TR ₁ (memory transistor) in the 1 ″ state can be adjusted to the enhancement side.

[Injection of electrons into the first laminated structure TR ₁ (memory transistor)] The access memory cell is set to "0".
In this case, it is necessary to inject electrons into the first laminated structure TR ₁ (memory transistor) of the access memory cell. In this case, WW _{i, 2} is, for example, 7 V, other word lines are all 0 V, and bit line D _{j + 2} is 0 V, and the other bit lines D _j , D _{j + 1} , D _{j + 3} , D _{j + are set. 4} , ... is set to 3V. On the other hand, all the second laminated structure TR ₂ (selection transistor) is turned off. Although 3V is applied to the bit line D _{j + 3} (corresponding to the source / drain region) of the nonvolatile memory cell adjacent to the right side, the second stacked structure TR ₂ (selection) of this nonvolatile memory cell is selected. Transistor) is off. Therefore, when injecting electrons into the access memory cell, the adjacent non-volatile memory cell on the right side is not affected. By this operation, the gate threshold voltage of the first laminated structure TR ₁ (memory transistor) of the access memory cell is set to the state of “0”.

[Reading of data] Select gate line BW _i
Is set to 5V, and the selection gate line BW _{i + 1 is set} to 0V. As a result, the second conductive gate G2 of the second stacked structure TR ₂ (selection transistor) connected to the selection gate line BW _i becomes 5V. On the other hand, the select gate line BW
The second conductive gate G2 of the second stacked structure TR ₂ (selection transistor) connected to _{i + 1} becomes 0V. Further, the bit lines D _j , D _{j + 2} , D _{j + 4} ... Are set to 3V, and the bit lines D _{j + 1} , D _{j + 3} ... The gate threshold voltage of the first stacked structure TR ₁ (memory transistor) in the “0” state and the first stacked structure TR in the “1” state
The voltage between the gate threshold voltage of ₁ (memory transistor) is sequentially applied to the word line (for example, WW _{i, 1} → WW _{i, 2} → ・
.., WW _{i, k-1} → WW _{i, k} ) is applied to read the data in each nonvolatile memory cell.

In this state, a pair of bit lines (D
Second laminated structure TR ₂ (selection transistor) of the non-volatile memory cell sandwiched by _j , D _{j + 1} ) and (D _{j + 2} , D _{j + 3} )
Is off. On the other hand, a pair of bit lines (D _{j + 1} , D
The second stacked structure TR ₂ (selection transistor) of the nonvolatile memory cell sandwiched between _{j + 2} ) and (D _{j + 3} , D _{j + 4} ) is in the ON state. Therefore, a pair of bit lines (D _j ,
D _{j + 1} ), (D _{j + 2} , D _{j + 3} ) ... Can not read the data of the non-volatile memory cell, while the pair of bit lines (D _{j + 1} , D _{j + 2} ), (D _{j + 3} , D _{j + 4} ) ...
・ The data in the non-volatile memory cell sandwiched between can be read. That is, the data in the non-volatile memory cell can be read every other word line WW.

When the reading of the data up to the word line WW _{i, k} is completed, the next select gate line (BW _{i + 1} ) is set to 5 V, the select gate line (BW _i ) is set to 0 V, and the pair of bit lines (D Data of the non-volatile memory cell sandwiched by _j , D _{j + 1} ), (D _{j + 2} , D _{j + 3} ) ... Are sequentially read by the same method.

In the nonvolatile memory cell array having the structure described with reference to FIG. 24, the data of one nonvolatile memory cell defined by the bit lines D _{j + 1} and D _{j + 2 and the} word line WW _{i, 2} is stored. In the case of richness, the bit line D _{j + 1} and the bit line located on the left side thereof are set to 0 V, and the bit line D _j
It is necessary to set the voltage of the bit line located on the right side of _{j + 2} to 3V, and only one nonvolatile memory cell data can be read on one word line WW.
Therefore, in the non-volatile memory cell array of the present invention, the data in the non-volatile memory cell can be read at a higher speed than the conventional one.

[0044] Also, when the electron injection into the first multilayer structure TR ₁ (memory transistor), or, when electrons are extracted from the first laminated structure TR ₁ (memory transistor), the second The laminated structure TR ₂ (selection transistor) is turned off. Therefore, data can be surely erased or written in the nonvolatile memory cell, and there is no influence on other nonvolatile memory cells at all.

Next, a method of manufacturing the nonvolatile memory cell array of the first embodiment will be described with reference to FIGS. The first laminated structure TR ₁ (memory transistor) is MON
OS type. In the manufacturing method of the nonvolatile memory cell array, the drain / source region and the source / drain region may be collectively referred to as a source / drain region.

[Step-100] First, the surface of the silicon semiconductor substrate 1 is oxidized by a conventional method to form a second insulating film 20 (gate oxide film) made of SiO _{2 on} the surface of the silicon semiconductor substrate 1. . Next, after a polysilicon layer is formed on the entire surface by the CVD method, the polysilicon layer and the second insulating layer 20 are selectively removed by using the photolithography technique and the dry etching technique, and the polysilicon layer is formed. A second stacked structure TR _{2 including} the second conductive gate G2 and the second insulating layer 20 formed thereunder is formed. In this way, a structure having a schematic partial cross-sectional view shown in FIG. 8A and a schematic partial plan view shown in FIG. 8B can be obtained. Note that FIG. 8A is a cross-sectional view taken along the line AA of FIG. 8B. The second conductive gate G2 is electrically connected in a direction intersecting the source / drain direction. More specifically, the second conductive gate G2 is continuous for a plurality of (for example, 2k) non-volatile memory cells in a direction intersecting the source / drain direction. In FIG. 8B, a certain second conductive gate G
A region where 2 is discontinuous is also shown.

[Step-110] Next, a resist 2 is formed on the entire surface excluding a part of the second conductive gate G2 made of polysilicon and the regions where the source / drain regions are to be formed.
Then, for example, n-type impurities are ion-implanted. In this case, there is an advantage that a part of the source / drain region can be formed by self-alignment. In this way, it is possible to obtain a structure in which a schematic partial sectional view is shown in FIG. 9A and a schematic partial plan view is shown in FIG. 9B. 9A is a sectional view taken along the line AA in FIG. 9B. In addition, in FIG. 9B,
Illustration of the resist 2 is omitted. As a result, although the high-concentration impurity has already been added to the second conductive gate G2, the high-concentration impurity is taken in and the source / drain region 30 is formed. Source / drain region 3
0 (drain / source region and source / drain region)
Are continuous over a plurality of nonvolatile memory cells formed later in a direction intersecting the source / drain direction. The source / drain region 30 corresponds to the bit line D.

Thus, as shown in FIG. 9, the semiconductor channel forming region CH sandwiched between the source / drain regions 30.
And the second insulating film 20 (gate oxide film) and the second conductive gate G2 formed on the semiconductor channel formation region CH.
The second laminated structure TR ₂ (corresponding to the selection transistor) can be formed.

[Step-120] Next, the resist 2 is removed, and the oxide film is further etched (in some cases, the unnecessary second insulating film 20 is selectively etched at the same time), so that the silicon semiconductor substrate 1 is processed. The surface and the surface of the second conductive gate G2 are oxidized by, for example, a low temperature oxidation method at 800 to 900 ° C. to form an oxide film 10A made of SiO ₂ (see FIG. 10A). The oxide film 10A corresponds to a part of the first insulating film 10. That is, the oxide film 10A on the first stacked structure formation planned region TR ₁ A corresponds to a tunnel oxide film, and the thickness thereof is set to, for example, 2 nm. The oxide film 10A is formed of an ONO insulating film.
Will be the lowermost oxide film (bottom oxide film) of the insulating film 10. Source / drain region 30 and second conductive gate G
Since 2 has been doped with a high concentration of impurities, it is 2 to 2 times larger than the region of the silicon semiconductor substrate previously covered with the resist 2 (corresponding to the first stacked structure formation planned region TR ₁ A). An oxide film 10C that is four times thicker is formed.
Incidentally, such a phenomenon is called accelerated oxidation.

[Step-130] Next, a SiN film is formed on the entire surface by a normal CVD method, and the surface of the SiN film is further oxidized. As a result, an oxide film of SiO ₂ /
SiN nitride films (oxide film / nitride film) 10B and S
The first insulating film 10 made of the ONO insulating film made of the oxide film 10A made of iO ₂ is formed (see FIG. 10B). The nitride film and the oxide film formed thereon (these two layers are collectively indicated by reference numeral 10B) correspond to the charge storage layer.

[Step-140] After that, a polysilicon layer (if necessary, a silicide layer such as tungsten silicide is further formed on the polysilicon layer) is formed on the entire surface by a normal CVD method, and then a photolithography technique and a dry etching technique are used. The polysilicon layer is selectively removed to form the first conductive gate G1 (corresponding to the word line WW). If necessary, the first insulating film in the region not covered with the first conductive gate G1 is also removed at the same time. As a result, the first insulating film 10 including the charge storage layer 10B and the first conductive gate G are formed on the semiconductor channel formation region CH.
A first laminated structure TR ₁ (corresponding to a MONOS type memory transistor) composed of 1 is completed. The first conductive gates G1 of the plurality of nonvolatile memory cells are electrically connected in the source / drain direction. This state is shown in FIG.
1 (A) is a schematic partial cross-sectional view, and FIG. 11 (B).
Is shown in a schematic partial plan view of FIG. In addition, (A) of FIG.
FIG. 12 is a sectional view taken along the line AA of FIG.

[Step-150] Then, boron is ion-implanted into the entire surface to form the element isolation region 31 (see the schematic partial plan view of FIG. 12).

[Step-160] Next, an interlayer insulating layer 32 made of, for example, SiO ₂ is formed on the entire surface by, for example, a CVD method, and a photo is formed on the interlayer insulating layer 32 above a desired portion of the second conductive gate G2. The opening 33 is formed by using the lithography technique and the dry etching technique. After that, a metal wiring material layer made of aluminum or an aluminum alloy is deposited on the interlayer insulating layer 32 including the inside of the opening 33, and the metal wiring material layer is patterned into a desired shape by using a photolithography technique and a dry etching technique. . As a result, the second conductive gate G2 is electrically connected in the source / drain direction, for example, every other nonvolatile memory cell. The patterned metal wiring material layer corresponds to the select gate line BW. This state is shown in the schematic partial cross-sectional view of FIG. 13A and the schematic partial plan view of FIG. 13B. Note that FIG. 13A is a cross-sectional view taken along the line AA in FIG. 13B, and the region drawn in FIG. 13A is the area in FIG.
Corresponding to the region along the line XIII-XIII in FIG.

This non-volatile memory cell comprises a first laminated structure TR ₁ (memory transistor) which constitutes one bit.
Since there is no source / drain region between the second stacked structure TR ₂ (selection transistor) and the _second stacked structure TR ₂ (selection transistor), compared with the conventional non-volatile memory cell composed of one selection transistor and one memory transistor, The feature is that one non-volatile memory cell can be made smaller. Further, when forming the source / drain regions, there is an advantage that a part is formed by self-alignment.

Further, as in the prior art, only the data of one nonvolatile memory cell is read on one word line WW, and the data is read from a plurality of nonvolatile memory cells which are not adjacent on one word line WW. The data in the non-volatile memory cell can be read faster than before. When erasing data or writing data, the second stacked structure TR ₂
Since the (selection transistor) is turned off, data can be surely erased or written to the nonvolatile memory cell, and it may affect other nonvolatile memory cells. Not at all.

(Embodiment 2) Embodiment 2 is a modification of the method for manufacturing the non-volatile memory cell array described in Embodiment 1, and is an example in which [Step-120] of Embodiment 1 is changed.
Hereinafter, only the step corresponding to [Step-120] of Example 1 will be described with reference to FIG.

[Step-200] [Step-11 in Example 1]
0], the resist 2 is removed, and the surface of the silicon semiconductor substrate and the surface of the second conductive gate G2 are removed by, for example, 800
Oxidation is performed by a low temperature pyrogenic oxidation method of up to 900 ° C to form an oxide film 10C made of SiO ₂ (Fig. 14).
(A)). Unlike the first embodiment, the oxide film 10C on the first stacked structure formation planned region TR ₁ A is about 10
It was set to 0 nm. As in the first embodiment, the oxide film 10C having a thickness of 200 to 400 nm is formed on the source / drain regions 30 and the second conductive gate G2 by the accelerated oxidation.

[Step-210] After that, the oxide film 10 formed in the portion of the first stacked structure forming planned region TR ₁ A is formed.
C is removed (see FIG. 14B). Such oxide film 1
The partial removal of 0C can be performed by etching the oxide film 10C over the entire surface.

[Step-220] After that, the exposed surface 1A of the silicon semiconductor substrate (corresponding to the first stacked structure forming planned region TR ₁ A) is again oxidized by, for example, a dilution oxidation method to have a thickness, for example. A 2 nm tunnel oxide film 10A is formed (see FIG. 14C). This tunnel oxide film 1
0A serves as the lowermost oxide film (bottom oxide film) of the first insulating film 10 made of the ONO insulating film. After that, [Step-130] to [Step-160] of Example 1 are performed to complete the nonvolatile memory cell.

According to the method described in the second embodiment, since the dilution oxidation method is used, the controllability of the thickness of the bottom oxide film is excellent, and the occurrence of variations in the characteristics of the semiconductor memory cells can be effectively generated. Can be suppressed. Moreover, since the thick oxide film 10C can be formed on the second conductive gate G2,
The breakdown voltage between the first conductive gate G1 and the second conductive gate G2 is improved.

(Example 3) In Example 3, first,
A first stacked structure (corresponding to a memory transistor) is formed, and then a second stacked structure (corresponding to a selection transistor) is formed. FIG. 15 shows a circuit diagram of the nonvolatile memory cell array of the third embodiment. The structure of the nonvolatile memory cell array according to the third embodiment is essentially the same as the structure of the nonvolatile memory cell array described in the first embodiment. The difference from the nonvolatile memory cell array of the first embodiment shown in FIG. 1 is that an intermediate region (shown by a dotted line in FIG. 15) is formed. Hereinafter, with reference to FIG. 16 and FIG.
A method of manufacturing the nonvolatile memory cell of Example 3 will be described.

[Step-300] First, the surface of the silicon semiconductor substrate is oxidized to form a tunnel oxide film 10A made of SiO _2, and a nitride film made of SiN is formed on the entire surface by a normal CVD method. Further, the surface of the nitride film is oxidized to form an oxide film made of SiO ₂ . As a result, the first insulating film 10 made of the ONO insulating film is formed. The nitride film and the oxide film formed thereon indicated by reference numeral 10B correspond to the charge storage layer.

[Step-310] After that, a polysilicon layer is formed on the entire surface by a CVD method, and an etching stop layer 40 made of SiN is further formed thereon. The etching stop layer 40 may be made of any material that is not etched by the etchant used when the second conductive gate G2 is formed by etching in the next [Step-320] or is not easily etched. Then, the etching stop layer 4 is formed by using the photolithography technique and the dry etching technique.
0, the polysilicon layer and, if necessary, the first insulating film 10
Are selectively removed to form the first insulating film 10 including the charge storage layer 10B and the first conductive gate G1 (see FIG. 16A). The etching stop layer 40 is left on the top surface of the first conductive gate G1. The first conductive gate G1 and the like extend in the direction perpendicular to the paper surface of FIG.

[Step-320] Next, a second insulating film 20 (gate oxide film) made of SiO ₂ is formed on the surface of the silicon semiconductor substrate by a conventional oxidation method, and then a polysilicon layer is formed on the entire surface. Then, the second conductive gate G2 is formed by using the photolithography technique and the dry etching technique (see FIG. 16B). At the time of dry etching, the etching stop layer 40 made of SiN formed on the first conductive gate G1 is present, so that the first conductive gate G1 can be prevented from being etched. The second conductive gate G2 extends, for example, by 2k nonvolatile memory cells in the direction perpendicular to the plane of the drawing.

[Step-330] After that, ion implantation is performed to form an LDD structure, for example, an n ^-- type layer is formed. After further forming a SiO ₂ layer on the entire surface,
The SiO ₂ layer is etched back to form LDD sidewalls 41 on the sidewalls of the first and second conductive gates (see FIG. 16C). The first conductive gate G1 and the second conductive gate G1
Since during the conductive gate G2 narrow, this area SiO ₂
Filled with layer 41A. The n ⁻ -type layer formed on the silicon semiconductor substrate 1 in the region between the first conductive gate G1 and the second conductive gate G2 corresponds to the intermediate region 30C.

[Step-340] Next, ion implantation of impurities is performed to form the source / drain regions 30 (FIG. 1).
7 (A)). n ⁺ type source / drain region 30
Can be formed by self-alignment.

[Step-350] After that, the first conductive gate G1 and the like are selectively removed by using the photolithography technique and the etching technique, and the first conductive gate is formed only in the region where the nonvolatile memory cell is to be formed. Leave G1 etc. Next, boron is ion-implanted into the entire surface to form the element isolation region 31.
Are formed between the first conductive gates G1 of the nonvolatile memory cells adjacent to each other in the direction intersecting the source / drain direction (see FIG. 18).

[Step-360] After that, the interlayer insulating layer 32 made of SiO _{2 is} formed by, for example, a low temperature pyrogenic oxidation method at 800 to 900 ° C. (FIG. 17B).
reference). An interlayer insulating layer 32 made of a thick oxide film is formed on the source / drain regions 30 and the second conductive gate G2 by accelerated oxidation. The etching stop layer 40 of SiN on the first conductive gate G1 is only slightly oxidized. The etching stop layer 4
The oxide film formed on the oxide film 0 is indicated by reference numeral 32A.

[Step-370] Next, wet etching or dry etching for a very short time is performed to form Si.
Oxide film 32A on etching stop layer 40 made of N
To remove. Next, the etching stop layer 40 is removed by, for example, heated phosphoric acid. The etching stop layer 40 and the oxide film 32A thereon may be removed by using a photolithography technique and a dry etching technique. As a result, the first conductive gate G1 is exposed and the second conductive gate G1 is exposed.
Conductive gate G2 remains covered with the interlayer insulating layer 32.

[Step-380] After that, a metal wiring material layer made of aluminum or an aluminum-based alloy is formed on the entire surface by, for example, a sputtering method, and then the metal wiring material layer is patterned into a desired shape to form the metal wiring. The word line WW made of a material layer electrically connects the first conductive gate G1 in the source / drain direction (FIG. 1).
7 (C)). When the word line WW is composed of polysilicon or silicide, [Step-350]
Can be omitted. In this case, the word line WW is formed by the photolithography technique and the etching technique, and further, the first conductive gate G is self-aligned.
1 can be etched. Then, after the first conductive gate G1 is selectively removed, boron is ion-implanted into the entire surface, so that the element isolation region 31 has the first conductivity of the non-volatile memory cell adjacent in the direction intersecting the source / drain direction. It may be formed between the gates G1.

[Step-390] Next, a second interlayer insulating layer (not shown) is formed on the entire surface by, eg, CVD, and the second and first portions above the desired portion of the second conductive gate G2 are formed. An opening is formed in the interlayer insulating layer by using a photolithography technique and a dry etching technique. Then, a metal wiring material layer made of aluminum or an aluminum alloy is deposited on the second interlayer insulating layer including the inside of the opening,
The metal wiring material layer is patterned into a desired shape by using a photolithography technique and a dry etching technique.
As a result, the second conductive gate G2 is electrically connected in the source / drain direction, for example, every other nonvolatile memory cell. The patterned metal wiring material layer corresponds to the select gate line BW. FIG. 18 is a plan view showing each region of the non-volatile memory cell of Example 3 manufactured in this way, which is assumed to be projected on a certain plane. In FIG. 18, a region forming one nonvolatile memory cell is shown by a chain line. If the opening is formed in the interlayer insulating layer 32 above the second conductive gate G2 before or after [Step-370] without forming the second interlayer insulating layer, the word line WW can be formed. Selection gate line BW
Can be formed.

The non-volatile memory cell of the third embodiment includes a first laminated structure TR ₁ (corresponding to a memory transistor) and a second laminated structure TR ₂ (corresponding to a selection transistor) which form 1 bit. Only the intermediate region 30C is formed between the two, and one non-volatile memory cell can be made smaller than the conventional non-volatile memory cell composed of one select transistor and one memory transistor. There is. Further, there is an advantage that the source / drain regions can be formed by self-alignment.

Furthermore, as in the prior art, only the data of one non-volatile memory cell is read in one word line WW, and the data is read from a plurality of non-volatile memory cells not adjacent in one word line WW. The data in the non-volatile memory cell can be read faster than before. When erasing data or writing data, the second stacked structure TR ₂
Since the (selection transistor) is turned off, data can be surely erased or written to the nonvolatile memory cell, and it may affect other nonvolatile memory cells. Not at all.

(Embodiment 4) In Embodiment 4, similarly to Embodiment 1, first, a second laminated structure (corresponding to a selection transistor) is formed, and thereafter, a first laminated structure (memory) is formed. Corresponding to a transistor). The structure of the nonvolatile memory cell array according to the fourth embodiment is essentially the same as the structure of the nonvolatile memory cell array described in the first embodiment. In Example 4, unlike Example 1,
The source / drain regions are formed by self-alignment. Further, unlike the nonvolatile memory cell array of the first embodiment, the intermediate region is formed. The circuit diagram of the nonvolatile memory cell array of the fourth embodiment is substantially the same as that of FIG. Hereinafter, with reference to FIG. 19 and FIG. 20, Example 4
A method for manufacturing the non-volatile memory cell will be described.

[Step-400] First, the surface of the silicon semiconductor substrate 1 is oxidized by a conventional method to form a second insulating film 20 (gate oxide film) made of SiO _{2 on} the surface of the silicon semiconductor substrate 1. . Next, after forming a polysilicon layer on the entire surface by, for example, a CVD method, an etching stop layer 40 made of SiO ₂ or SiN is formed thereon. The etching stop layer 40 is formed in [Step-42
[0], any insulating material may be used as long as it is a material that is not etched or is not easily etched by the etchant used when forming the first conductive gate G1 by etching. Then, the etching stop layer 40, the polysilicon layer and the second insulating film 20 are formed by using the photolithography technique and the dry etching technique.
Are selectively removed to form a second conductive gate G2 made of polysilicon (see FIG. 19A). The second conductive gate G2 extends in the direction perpendicular to the paper surface of FIG. 19, for example, by 2k non-volatile memory cells.

[0076] [Step -410] Next, the entire surface insulating film 10A made of SiO _2, composed of an ONO insulating film of oxide film 10B made of nitride film and the SiO ₂ composed of SiN, including the exposed surface of the silicon semiconductor substrate 1 The formed first insulating film 10 is formed. The nitride film and the oxide film formed thereon indicated by reference numeral 10B correspond to the charge storage layer (see FIG. 19B).

[Step-420] After that, a polysilicon layer is deposited on the entire surface by a CVD method, and then the polysilicon layer and optionally the first insulating film 10 are selectively formed by a photolithography technique and a dry etching technique. Then, the first conductive gate G1 is formed (see FIG. 19C). Under the first conductive gate G1, ONO is provided.
The first insulating film 10 made of a film is left. Since the etching stop layer 40 is present on the second conductive gate G2 during the dry etching, the second conductive gate G2 can be prevented from being etched. The first conductive gate G1 and the like extend in the direction perpendicular to the paper surface of FIG.

[Step-430] After that, ion implantation is performed to form an LDD structure, and further SiO ₂ is formed on the entire surface.
After forming the layer, the SiO ₂ layer is etched back to form the first layer.
And an LDD sidewall 4 on the sidewall of the second conductive gate.
1 is formed (see FIG. 20A). Since the space between the first conductive gate G1 and the second conductive gate G2 is narrow, this region is filled with the SiO ₂ layer 41A. The n ⁻ -type layer formed on the silicon semiconductor substrate 1 in the region between the first conductive gate G1 and the second conductive gate G2 corresponds to the intermediate region 30C.

[Step-440] Next, ion implantation of impurities is performed to form the source / drain regions 30 (FIG. 2).
0 (see (B)). The source / drain regions 30 can be formed by self-alignment.

[Step-450] After that, the first conductive gate G1 and the like are selectively removed by using the photolithography technique and the etching technique, and the first conductive gate is formed only in the region where the nonvolatile memory cell is to be formed. Leave G1 etc. Then, boron is ion-implanted into the entire surface to form an element isolation region (not shown) between the first conductive gates G1 of the nonvolatile memory cells adjacent to each other in the direction intersecting the source / drain direction.

[Step-460] After that, the interlayer insulating layer 32 made of SiO _{2 is} formed by a low temperature pyrogenic oxidation method at 800 to 900 ° C., for example. An interlayer insulating layer 32 made of a thick oxide film is formed on the source / drain regions 30 and the second conductive gate G1 by accelerated oxidation. In order to form an opening on the first conductive gate G1 by using an etch-back method or a photolithography technique and an etching technique, and electrically connect each of the first conductive gates G1 with a polysilicon layer. The word line WW is formed (see FIG. 20C).
When the word line WW is made of polysilicon or silicide, [Step-450] can be omitted. In this case, the first conductive gate G1 is selectively removed and boron is ion-implanted on the entire surface by the same method as that described in [Step-380] of the third embodiment to form the element isolation region. May be formed between the first conductive gates G1 of the nonvolatile memory cells adjacent to each other in the direction intersecting the source / drain direction.

[Step-470] Next, a second interlayer insulating layer (not shown) is formed on the entire surface by, eg, CVD method to form second and first insulating layers above the desired portion of the second conductive gate G2. An opening is formed in the interlayer insulating layer by using a photolithography technique and a dry etching technique. Then, a metal wiring material layer made of aluminum or an aluminum-based alloy is deposited on the second interlayer insulating layer including the inside of the opening, and the metal wiring material layer is patterned into a desired shape by using photolithography technology and dry etching technology. To do. As a result, the second conductive gate G2 is electrically connected in the source / drain direction, for example, every other nonvolatile memory cell. The patterned metal wiring material layer corresponds to the select gate line BW. A plane projection view assuming that each region of the nonvolatile memory cell of Example 4 thus manufactured is projected on a certain plane is substantially the same as the plane projection view shown in FIG.

The nonvolatile memory cell of the fourth embodiment also includes a first laminated structure TR ₁ (corresponding to a memory transistor) and a second laminated structure TR ₂ (corresponding to a selection transistor) which form 1 bit. Only the intermediate region 30C is formed between the two, and one non-volatile memory cell can be made smaller than the conventional non-volatile memory cell composed of one select transistor and one memory transistor. There is. Further, there is an advantage that the source / drain regions can be formed by self-alignment.

The nonvolatile memory cell array of the present invention has been described above based on the preferred embodiments, but the nonvolatile memory cell array of the present invention is not limited to these embodiments. In the embodiment, the first insulating film is turned on exclusively.
Although the O insulating film is used, the first insulating film is not limited to this. For example, the first insulating film, oxide film / S 3-layer structure of oxide film made of a nitride film / SiO ₂ composed of oxynitride film / SiN consisting SiON from below, from bottom of SiO ₂
A two-layer structure of a nitride film made of iN and a two-layer structure of an oxynitride film made of SiON / a nitride film made of SiN can be formed from the bottom. In addition, the first insulating film, from the bottom 4-1
So-called floating gate type composed of 0 nm thick insulating film / impurity 10 ¹⁹ to 10 ²⁰ cm ⁻³ doped silicon thin film / insulating film made of polysilicon, or 4 to 10 nm thick insulating film / impurity from the bottom From 10 ¹⁹ to
Silicon thin film / multi-layer insulating film (eg, ONO film or NO film) made of 10 ²⁰ cm ⁻³ doped polysilicon
It may be a floating gate type composed of a film).

Instead of forming the first and second conductive gates from a polysilicon layer, a silicide layer or, alternatively,
A polycide structure composed of two layers of a polysilicon layer and a silicide layer can also be used. In the first conductive gate (corresponding to the word line WW) in the first embodiment, a metal wiring layer made of aluminum, an aluminum-based alloy, or the like can be formed thereon. Further, the word line and the select gate line in the third or fourth embodiment may be made of polysilicon, or polysilicon / silicide from the bottom, or the interlayer insulating layer 32 may be formed by the CVD method. .

The nonvolatile memory cell array of the present invention is not only formed on a silicon semiconductor substrate, but also for example SOI.
It can be formed on a substrate having a structure.

[0087]

In the non-volatile memory cell array of the present invention, since the element isolation region in the source / drain direction is unnecessary, the non-volatile memory cell can be highly integrated. Further, the size of the memory cell can be made smaller than that of the conventional non-volatile memory cell composed of the two transistors of the memory transistor and the selection transistor, and the non-volatile memory cells can be integrated with high density. Moreover, since it is a nonvolatile memory cell of the type in which charges (electrons or holes) are injected or extracted from the channel formation region to the charge storage layer, a high number of times of rewriting can be achieved. Further, since the second laminated structure (corresponding to the selection transistor) is provided, the current driving capability of the first laminated structure (corresponding to the memory transistor) is not reduced, and the adjacent nonvolatile Write to the first laminated structure (corresponding to a memory transistor) of the non-volatile memory cell can be prevented.

In a preferred mode of the non-volatile memory cell array of the present invention, the second conductive gate is electrically connected by a plurality of non-volatile memory cells in a direction intersecting the source / drain direction. At least every other nonvolatile memory cell is electrically connected in the source / drain direction. As a result, for example, the data in the nonvolatile memory cell can be read every other second conductive gate, and the data can be read faster than the conventional nonvolatile memory cell array. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a nonvolatile memory cell array according to a first embodiment.

FIG. 2 is a plan view of each area of the nonvolatile memory cell array according to the first embodiment.

FIG. 3 is a partial cross-sectional view of the nonvolatile memory cell array according to the first embodiment.

FIG. 4 is a partial cross-sectional view of the nonvolatile memory cell array according to the first embodiment.

FIG. 5 is a partial cross-sectional view of the nonvolatile memory cell array according to the first embodiment.

FIG. 6 is a partial cross-sectional view of the nonvolatile memory cell array according to the first embodiment.

FIG. 7 is a schematic circuit diagram showing an outline of a nonvolatile memory cell array of the present invention.

FIG. 8 is a partial cross-sectional view of a semiconductor substrate or the like for explaining the method for manufacturing the nonvolatile memory cell array according to the first embodiment.

FIG. 9 is a partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the nonvolatile memory cell array according to the first embodiment, following FIG. 8;

10 is a partial cross-sectional view of the semiconductor substrate or the like for explaining the manufacturing method of the nonvolatile memory cell array of the first embodiment, following FIG. 9;

11 is a partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the nonvolatile memory cell array according to the first embodiment, following FIG.

FIG. 12 is a partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the nonvolatile memory cell array according to the first embodiment, following FIG. 11;

FIG. 13 is a partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the nonvolatile memory cell array according to the first embodiment, following FIG. 12;

FIG. 14 is a partial cross-sectional view of a semiconductor substrate and the like for explaining the method for manufacturing the nonvolatile memory cell array according to the second embodiment.

FIG. 15 is a circuit diagram of a nonvolatile memory cell array according to a third embodiment.

FIG. 16 is a partial cross-sectional view of a semiconductor substrate or the like for explaining the method for manufacturing the nonvolatile memory cell array according to the third embodiment.

FIG. 17 is a partial cross-sectional view of the semiconductor substrate etc. for explaining the manufacturing method of the nonvolatile memory cell array of the third embodiment, following FIG. 16;

FIG. 18 is a plan view of each area of the nonvolatile memory cell array according to the third embodiment.

FIG. 19 is a partial cross-sectional view of a semiconductor substrate or the like for explaining the method for manufacturing the nonvolatile memory cell array according to the fourth embodiment.

FIG. 20 is a partial cross-sectional view of the semiconductor substrate etc. for explaining the manufacturing method of the nonvolatile memory cell array of the third embodiment, following FIG. 19;

FIG. 21 is a schematic plan view of a semiconductor device including a conventional mask ROM to which an embedded bit line system is applied.

FIG. 22 is a schematic cross-sectional view of a semiconductor device including a conventional mask ROM to which a buried bit line system is applied.

FIG. 23 is a diagram for explaining the operation of the semiconductor device including the conventional mask ROM to which the embedded bit line system is applied.

FIG. 24 is a schematic partial cross-sectional view of a flash EEPROM to which a buried bit line system is applied.

FIG. 25 is a circuit diagram of a conventional flash EEPROM to which an embedded bit line system is applied.

FIG. 26 is a schematic partial cross-sectional view and circuit diagram of a conventional flash EEPROM in which an offset region is provided on the source side.

[Explanation of symbols]

1 Silicon Semiconductor Substrate D Bit Line WW Word Line BW Select Gate Line TR ₁ First Laminated Structure G1 First Conductive Gate 10 First Insulating Film 10A Oxide Film 12 Charge Storage Layer TR ₂ Second Laminated Structure G2 Second conductive gate 20 Second insulating film 30, 30A, 30B Drain / source region or source / drain region CH Semiconductor channel forming region 32 Interlayer insulating layer 33 Opening

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (9)

[Claims] 1. (A) Drain / source region and source /
A drain region, (B) a semiconductor channel forming region sandwiched between the drain / source region and the source / drain region, and (C) a first region including a charge storage layer formed on the semiconductor channel forming region. A plurality of non-volatile memory cells each including a first laminated structure including an insulating film and a first conductive gate, and a second laminated structure including a second insulating film and a second conductive gate are provided. And the drain / source regions and the source / drain regions of the non-volatile memory cells adjacent to each other in the direction intersecting the source / drain direction are continuous, The drain / source region of the non-volatile memory cell is a common region with the source / drain region of the non-volatile memory cell adjacent in the source / drain direction. The source / drain region of the non-volatile memory cell is a region common to the drain / source regions of other non-volatile memory cells adjacent in the source / drain direction, and the first conductive gate of each non-volatile memory cell is the source.・
The second conductive gate of each nonvolatile memory cell is electrically connected in the drain direction, and
A nonvolatile memory cell array, which is electrically connected in a direction intersecting with a drain direction. 2. The second conductive gate includes a plurality of non-volatile memory cells in a direction intersecting the source / drain direction,
The non-volatile memory cell array according to claim 1, wherein the non-volatile memory cell array is electrically connected, and at least every other non-volatile memory cell is electrically connected in the source / drain direction. 3. The semiconductor channel forming region located between the first conductive gate and the second conductive gate has a drain /
The nonvolatile memory cell array according to claim 1 or 2, wherein an intermediate region having the same conductivity type as the source region and the source / drain region is formed. 4. The first insulating film including a charge storage layer is formed of three layers of an oxide film, a nitride film and an oxide film, according to claim 1. Non-volatile memory cell array. 5. The first insulating film including a charge storage layer is composed of three layers of an oxynitride film, a nitride film, and an oxide film, according to any one of claims 1 to 3. Non-volatile memory cell array. 6. The nonvolatile memory according to claim 1, wherein the first insulating film including the charge storage layer is composed of two layers of an oxide film and a nitride film. Cell array. 7. The nonvolatile memory according to claim 1, wherein the first insulating film including the charge storage layer is composed of two layers of an oxynitride film and a nitride film. Memory cell array. 8. The first insulating film including a charge storage layer comprises three layers of an insulating film, a silicon thin film, and an insulating film, according to any one of claims 1 to 3. Non-volatile memory cell array. 9. The first insulating film including a charge storage layer comprises three layers of an insulating film, a silicon thin film, and a multi-layer insulating film, according to any one of claims 1 to 3. Non-volatile memory cell array.