JP2000049313A - Non volatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non volative semiconductor memory device which keeps a small erasing block and a rapid responsiveness and has a long-time reliability, and also provide a method for manufacturing such a device. SOLUTION: When writing data in a memory 15, a selection gate 8, a drain diffused layer 2, and a source diffusion layer 13 are applied with positive bias, a source diffused layer 3 is grounded, and an erasing gate 9 is opened. By applying relatively large positive bias to the drain diffused layer 2 side, hot electrons generated in a channel region on the drain diffused layer 2 side are injected into a floating gate 5. In this method for injection using hot electrons, a thicker gate oxide film than in FN tunneling can be used even at the same potential. When erasing the data, the electrons are pulled away from the floating gate 5 into an eraser gate 9 by applying the eraser gate 9 with positive bias and the selection gate 8 with 0V or a negative bias and opening the other terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device called a split gate type used for an EEPROM or a flash EEPROM and a method for manufacturing the same, and more particularly to a field requiring a large capacity and high reliability. The present invention also relates to a nonvolatile semiconductor memory device suitable for use and a method for manufacturing the same.

[0002]

2. Description of the Related Art Flash memories having a larger storage capacity per unit area than conventional nonvolatile memories are currently the mainstream of nonvolatile memories. Flash memory has achieved a great deal of integration by eliminating the erasing function for each single bit. Therefore, in most cases, erasing of the flash memory is performed in units of a certain area (called a block in this specification). In recent years, flash memories have achieved a tremendous degree of high integration, and as a result, large-capacity flash memories have been realized. On the other hand, high-density and large-capacity flash memories tend to have larger erase blocks. The flash memory was primarily used as a replacement for the UV-EPROM of the ultraviolet erasing type, and the size of the erasing block did not matter. However, considering other applications, it has become necessary that the erase block can be made smaller and that it can be set arbitrarily as needed.

An example of a flash memory cell is disclosed in US Pat. No. 5,280,446 (prior art 1). This memory has a so-called contactless NOR structure using a buried diffusion layer, and adopts a connection method like a virtual ground array in which adjacent memory cells share a diffusion layer. Therefore, the area per bit is small in spite of having the split gate structure. Further, the memory of the prior art 1 is:
Erasure can be performed independently for each drain diffusion layer. For this reason, there is an advantage that an erase block can be made smaller than a flash memory employing another method. Further, since a data block is provided for each drain diffusion layer, there is no need to switch the potential of the drain diffusion layer when writing or reading data of the same data block, which is advantageous for speeding up. In the memory of the prior art 1, the erasing operation uses FN tunneling from the floating gate to the drain diffusion layer.

As a method not using FN tunneling in a gate region, there is a method of performing erasing using an erasing gate. When an erase gate is used, the erase operation uses FN tunneling between the floating gate and the erase gate. Therefore, the thickness of the gate oxide film below the floating gate can be increased, and the gate oxide film does not deteriorate due to erasure. Therefore, long-term reliability of device characteristics and charge retention characteristics can be easily ensured. There is a flash memory having an erase gate disclosed in Japanese Patent Application Laid-Open No. 9-129853 (prior art 2). The memory cell used in the prior art 2 is a split gate type having excellent operation stability, and has a buried diffusion layer structure of a virtual ground configuration.
It is also advantageous for high integration.

[0005]

In the memory of the prior art 1, the erasing operation is performed by the F operation from the floating gate to the drain diffusion layer.
N tunneling is used. For this reason, the thickness of the gate oxide film under the floating gate needs to be practically 10 nm or less, and in order to meet the recent demand for lowering the voltage, the thickness must be further reduced. . When FN tunneling is repeatedly performed on such an extremely thin film, the gate oxide film itself is deteriorated. Therefore, if the write / erase operation is repeatedly performed, the device characteristics and the charge retention characteristics are deteriorated. This means
An obstacle to ensuring long-term reliability.

In the prior art 2, the erase gate and the diffusion layer are orthogonal to each other. For this reason, when the erase block is a data block, it is necessary to switch the potential of the diffusion layer when writing or reading data in the same data block, which is disadvantageous for speeding up. Thus, it has been difficult to fundamentally improve the long-term reliability of device characteristics and charge retention characteristics while maintaining small erase blocks and high-speed response.
Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same in a flash memory, which maintain a small erase block and high-speed responsiveness and ensure long-term reliability.

[0007]

In a nonvolatile semiconductor device according to the present invention, memory cells formed on a semiconductor substrate of a first conductivity type having a main plane are arranged in a matrix of rows and columns on the main plane. Each memory cell is a MOS type memory having a source diffusion layer, a drain diffusion layer, a floating gate, a selection gate, and an erase gate.
A strip-shaped second conductivity type diffusion layer serving as a source diffusion layer and a drain diffusion layer is formed in the column direction, and memory cells adjacent to each other with the drain diffusion layer interposed therebetween share a drain diffusion layer so as to share the drain diffusion layer. A channel is formed symmetrically with respect to the memory cell region, a channel is formed between the source diffusion layer and the drain diffusion layer in the memory cell region, and a floating gate whose length in the channel length direction is shorter than the distance between the source diffusion layer and the drain diffusion layer is formed by the source diffusion layer. A drain diffusion layer is formed for each memory cell via the first insulating film between the drain diffusion layers, and the drain diffusion layer is formed on the drain diffusion layer via the second insulating film; A band-shaped erase gate shared by the memory cells arranged on both sides of the memory cell is arranged. Further, in the upper layer, a memory cell arranged in the row direction of the array is shared and a memory cell selection gate is provided. Word line serving as a gate electrode is, the floating gate and the semiconductor substrate of the source diffusion layer are those formed through the third insulating film.

Writing is performed by applying a positive bias to the select gate and the drain diffusion layer and injecting hot electrons generated on the drain diffusion layer side of the channel region into the floating gate via the first insulating film. Erasing is performed by applying a positive bias to the erasing gate and FN tunneling from the floating gate to the erasing gate via the second insulating film. As described above, in the present invention, FN tunneling in the channel region is not used for injecting / extracting electrons to / from the floating gate. For this reason, the first insulating film thickness conventionally required to be 10 nm or less can be made larger. In addition, the first problem caused by performing FN tunneling
Since the insulating film does not deteriorate, the device characteristics and charge retention can be greatly improved. Further, since the drain diffusion layer and the erase gate are formed in the same direction so as to correspond one-to-one, the speed of the erase block is not lost while maintaining the small size of the erase block.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS It is preferable to use a laminated film of a silicon oxide film / silicon nitride film / silicon oxide film as a third insulating film. As a result, higher reliability can be obtained with a thinner film thickness as compared with the case where a simple silicon oxide film is used, so that the operation voltage can be reduced and the charge retention ability can be further improved. It is preferable that the floating gate and the drain diffusion layer have a region overlapping in the channel length direction with the first insulating film interposed therebetween. As a result, when a positive bias is applied to the drain diffusion layer, a positive bias can be applied to the floating gate due to the capacitive coupling by the overlap region. Hot electrons can be generated on the side of the source diffusion layer in the channel portion, so that the channel current can be controlled by the select gate, so that the hot electrons can be more efficiently injected into the floating gate, leading to lower power consumption. .

As an array system of the nonvolatile semiconductor memory device according to the present invention, drain diffusion layers and source diffusion layers are alternately formed, and a memory cell group sharing one drain diffusion layer is used as a block, and adjacent blocks are connected to each other. It is preferable that they are connected so as to share a source diffusion layer with each other. As a result, there is no need to provide an element isolation region between erase blocks, and the element area per bit can be reduced. Further, it is preferable that the source diffusion layer and the drain diffusion layer are each connected to a metal bit line via a block selection transistor, and all erase gates in a block selected by the block selection transistor are electrically connected to each other. . As a result, the area selected by the block selection transistor and the erase block can be made the same.

Further, the size of the erase block can be freely set by changing the number of elements between the block selection transistors. Further, by using the block selection transistor, the bit line capacity at the time of reading can be significantly reduced, and the reading time at the time of random access can be reduced.
Further, the metal bit line is formed in a direction parallel to the source diffusion layer and the drain diffusion layer, the gate of the block selection transistor is formed in a direction orthogonal to the metal bit line, and an erasing line common to all erasing gates in the block. Also, it is preferable that they are formed in a direction orthogonal to the metal bit lines. As a result, the gate of the block select transistor does not overlap with the erase gate and the erase line, which is advantageous in the production process.

A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes the following steps (a) to (g). (A) forming an element isolation layer between bits on a semiconductor substrate of a first conductivity type, and then forming a first insulating film on the semiconductor substrate; and (b) forming a first polysilicon layer serving as a floating gate. After the deposition, a step of patterning the polysilicon layer so as to open the drain diffusion layer region and the source diffusion layer region, and (c) implanting a second conductivity type impurity into the semiconductor substrate using the pattern of the polysilicon layer as a mask. Performing, forming a strip-shaped drain diffusion layer and a source diffusion layer,
(D) forming a second insulating film on the surface of the polysilicon layer, on the source diffusion layer and on the drain diffusion layer using thermal oxidation, and (e) further depositing a second polysilicon layer, Patterning the polysilicon layer to form a strip-shaped erase gate in a direction parallel to the source diffusion layer and the drain diffusion layer, and simultaneously etching a portion of the first polysilicon layer that protrudes from the erase gate pattern. Forming a floating gate, (f) forming a third insulating film on the entire surface of the semiconductor substrate, and (g) forming a third insulating film thereon.
After forming a polysilicon layer, patterning is performed,
Forming a select gate in a direction orthogonal to the source diffusion layer, the drain diffusion layer, and the erase gate; Since the etching pattern of the second type 2 polysilicon for the floating gate is used as it is for the implantation of the source diffusion layer and the drain diffusion layer, the number of lithography can be reduced and the process can be simplified.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. 1A and 1B are diagrams illustrating an embodiment of a semiconductor memory device, wherein FIG. 1A is a plan view, and FIG.
It is sectional drawing in A '. A strip-shaped N serving as source diffusion layers 3 and 13 and a drain diffusion layer 2 is formed on a P-type silicon substrate 1.
Diffusion layers are formed in parallel with each other and alternately in a column direction (a vertical direction in (a) and a vertical direction in the drawing in (b)). The memory cells are arranged symmetrically with respect to the drain diffusion layer 2 so as to share each drain diffusion layer 2, and are separated in the column direction by a field oxide film 10.

The source diffusion layer 3 has a length in the channel length direction.
A floating gate 5 made of polysilicon having N-type conductivity shorter than the distance between the drain diffusion layers 2 forms a gate oxide film (first insulating film) between the source diffusion layer and the drain diffusion layer.
4, each of the memory cells is formed closer to the drain diffusion layer 2 side. On the drain diffusion layer 2, an insulating layer 6 is interposed, and on the upper and side surfaces of a part of the floating gate 5, a silicon oxide film (second insulating film) 20 is interposed on both sides of the drain diffusion layer 2. A band-shaped erase gate 9 shared by the memory cells is formed in parallel with the drain diffusion layer 2. Furthermore, in the upper layer, band-shaped select gates 8 and 18 in the row direction shared by the memory cells of each row of the array are provided. The semiconductor substrate 1 between the source diffusion layers 3 and 13 and the floating gate 5 is a silicon oxide film ( Via the third insulating film) 11, the source diffusion layers 3 and 13 via the silicon oxide film 7, the floating gate 5 via the silicon oxide film 21, and the erase gate 9 via the silicon oxide film 23. Have been. 15 is 1
Represents the number of memory cells.

The operation of this memory is performed as follows. Writing of data to the memory 15 is performed by applying a positive bias to the selection gate 8, applying a positive bias to the drain diffusion layer 2 and the source diffusion layer 13, setting the source diffusion layer 3 to ground, and opening the erase gate 9. . Floating gate 5
And the select gate 8 are capacitively coupled via the silicon oxide film 21. Therefore, a channel is formed between the source diffusion layer 3 and the drain diffusion layer 2 under the select gate 8 and the floating gate 5. At this time, by applying a relatively large positive bias to the drain diffusion layer 2 side, the drain diffusion layer 2
Hot electrons generated in the side channel region can be injected into the floating gate 5. In this hot electron injection, a thicker gate oxide film can be used even at the same voltage as compared with FN tunneling. For erasing, a positive bias is applied to the erasing gate 9 and 0 V or a negative bias is applied to the selection gate 8 to open other terminals, and to extract electrons from the floating gate 5 to the erasing gate 9 through the silicon oxide film 20. Done by

As described above, in the present invention, the FN tunneling via the gate oxide film is not used for the write / erase operation.
Therefore, it is possible to make the gate oxide film 10 nm or more. Further, there is no deterioration of the gate oxide film due to FN tunneling. For this reason, it is easy to secure long-term reliability of the memory such as deterioration of device characteristics and charge retention. Further, in the present invention, since the drain diffusion layer and the erase gate are formed in the same direction and correspond one-to-one,
When writing or reading data in the same data block, there is no need to switch the potential of the diffusion layer, and high-speed data writing and reading are maintained.

Further, it is preferable that the silicon oxide film 21 is a laminated film of a silicon oxide film / silicon nitride film / silicon oxide film. In this case, higher reliability can be obtained with a thinner film thickness as compared with the case where a simple silicon oxide film is used, so that the operation voltage can be reduced and the charge holding ability can be improved.

Next, an outline of the manufacturing process will be described with reference to FIG. FIG. 2 is a process diagram showing a top view of one embodiment of the manufacturing method. (A) An island-shaped field oxide film 10 is formed as a device isolation layer between bits on a P-type silicon substrate. Next, thermal oxidation is performed on the entire surface of the silicon substrate to form a gate oxide film (first insulating film). Next, after n-type polysilicon is deposited on the entire surface of the silicon substrate, the polysilicon is patterned to form a floating gate 5. (B) Next, arsenic (As) is implanted by using normal lithography and ion implantation to form the drain diffusion layer 2 and the source diffusion layers 3 and 13.

(C) Subsequently, the entire surface of the silicon substrate is oxidized by thermal oxidation to form a silicon oxide film (second insulating film).
To form After n-type polysilicon is deposited on the entire surface of the silicon substrate, patterning of the polysilicon is performed to form an erase gate 9. (D) Next, the entire surface is oxidized using thermal oxidation to form a silicon oxide film. An n-type polysilicon and a tungsten silicide are sequentially formed thereon and patterned,
The selection gates 8 and 18 are formed.

FIGS. 3A and 3B are views showing another embodiment of the semiconductor memory device, wherein FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along the line AA 'shown in FIG. A strip-shaped N-type diffusion layer serving as source diffusion layers 3 and 13 and a drain diffusion layer 2 is formed on a P-type silicon substrate 1 in the column direction as in FIG. Further, an n-type diffusion layer 16 having a lower concentration than the diffusion layer 2 is formed so as to surround the diffusion layer 2, and the diffusion layers 2 and 16 constitute a drain diffusion layer. The memory cells are arranged symmetrically with respect to the drain diffusion layer 2 so as to share the drain diffusion layer 2.

The length in the channel length direction is equal to the source diffusion layer 3-
A floating gate 5 made of polysilicon having an N-type conductivity shorter than the distance between the drain diffusion layers 2 is moved toward the drain diffusion layer 2 via the gate oxide film 4 between the source diffusion layer and the drain diffusion layer. And is formed for each memory cell. On the drain diffusion layer 2, a silicon oxide film 2 is formed on the upper surface and some side surfaces of the floating gate 5 via an insulating layer 6.
A band-like erase gate 9 shared by the memory cells arranged on both sides of the drain diffusion layer 2 is formed through the drain gate 0. Further in the upper layer, band-shaped select gates 8 and 18 in the row direction shared by the memory cells of each row of the array are provided. The semiconductor substrate 1 between the source diffusion layer 3 and the floating gate 5 is a silicon oxide film (third layer). Through the source diffusion layers 3 and 13
Are formed via the silicon oxide film 7, the floating gate 5 is formed via the silicon oxide film 21, and the erase gate 9 is formed via the silicon oxide film 23.

The operation of this memory is performed as follows. Writing of data to the memory 15 is performed by applying a positive bias to the selection gate 8, applying a positive bias to the drain diffusion layer 2 and the source diffusion layer 13, setting the source diffusion layer 3 to ground, and opening the erase gate 9. . Floating gate 5
And the drain diffusion layer 2 are capacitively coupled via the gate oxide film 4. Therefore, a channel is formed between the source diffusion layer 3 and the drain diffusion layer 2 under the select gate 8 and the floating gate 5. At this time, by applying a relatively large positive bias to the drain diffusion layer 2 side, the drain diffusion layer 2
Hot electrons generated in the side channel region can be injected into the floating gate 5. In this hot electron injection, a thicker oxide film can be used even at the same voltage as compared with FN tunneling.

Further, in the present invention, the application of a bias to the floating gate 5 uses capacitive coupling with the drain diffusion layer 2. For this reason, since the channel current can be controlled by the selection gate 8, electrons can be more efficiently injected. Erasing is performed by applying a positive bias to the erasing gate 9 and applying 0 V or a negative bias to the selection gate, leaving other terminals open, and extracting electrons from the floating gate 5 to the erasing gate 9 through the silicon oxide film 20. Do.

In this embodiment, as in the embodiment of FIG.
The drain diffusion layer and the erase gate are formed in the same direction and correspond one-to-one without using FN tunneling via the gate oxide film in the write / erase operation, so that device characteristics and charge retention are reduced. Thus, long-term reliability of the memory can be ensured, and high-speed data writing and reading can be ensured. In the embodiment of FIG.
3 overlaps only a part of the upper surface of the floating gate 5, but differs from the embodiment of FIG. 3 in that the erase gate 9 overlaps the entire upper surface of the floating gate 5.

Next, the manufacturing process of the embodiment of FIG.
This will be described with reference to FIG. FIG. 4 is a process diagram showing the manufacturing method by a top view, and shows a manufacturing method different from FIG. (A) An island-shaped field oxide film 10 is formed as a device isolation layer between bits on a P-type silicon substrate. Next, phosphorus is implanted using a normal lithography method and ion implantation to form a low-concentration n-type diffusion layer 16 constituting a drain diffusion layer. (B) Next, thermal oxidation is performed on the entire surface of the semiconductor substrate to form a gate oxide film. Next, n-type polysilicon to be the floating gate 5 is deposited on the entire surface of the semiconductor substrate. Further, a resist pattern is formed so as to open the drain diffusion layer 2 and the source diffusion layers 3 and 13 and the field oxide film, and the polysilicon is patterned using the resist pattern as a mask. Next, As is implanted using the polysilicon pattern as a mask to form a drain diffusion layer 2 and source diffusion layers 3 and 13.

(C) Subsequently, the entire surface of the semiconductor substrate is oxidized by using thermal oxidation to form an interlayer film made of a silicon oxide film on the surface of the polysilicon pattern for the floating gate 5, and the source diffusion layer 3 is formed. , 13 and an insulating layer made of silicon oxide film 6 is formed on drain diffusion layer 2. Next, n-type polysilicon is deposited on the entire surface of the semiconductor substrate, and the polysilicon is patterned to form an erase gate 9. At this time, the floating gate 5
The portion of the polysilicon pattern that protrudes from the erase gate 9 is simultaneously etched to form the floating gate 5. (D) Next, the entire surface of the semiconductor substrate is oxidized using thermal oxidation to form a silicon oxide film. Further, n-type polysilicon and tungsten silicide are sequentially formed thereon, patterned, and the select gates 8 and 18 are formed. In this manufacturing method, since the etching pattern of the floating gate 5 is used as it is for implantation of the source diffusion layer and the drain diffusion layer, the number of times of lithography can be reduced and the process can be simplified.

Next, an embodiment of the memory cell array is shown in FIG.
This will be described with reference to FIG. FIG. 5 is a schematic circuit diagram showing a memory block of the embodiment. The memory element 51 is as shown in FIG. 1 or FIG. The memory elements are connected in parallel by a source diffusion layer 3 and a drain diffusion layer 2, and elements adjacent to each other with the drain diffusion layer 2 interposed therebetween share the drain diffusion layer 2 and have a source diffusion layer 13. Are arranged symmetrically. Further, the erase gate 9 is formed so as to correspond one-to-one with the drain diffusion layer 2 in the same direction as the drain diffusion layer 2. For this reason, the erase block 52 is constituted by a memory sharing one drain diffusion layer. Further, adjacent erase blocks 52 are arranged so as to share the source diffusion layer lines 3 and 13. By employing this method, it is not necessary to form an element isolation region between erase blocks, and the element area per bit can be reduced.

FIG. 6 is a schematic circuit diagram showing the memory block of FIG. 5 together with block select transistors. The drain diffusion layer 2 and the source diffusion layer 3, which are memory diffusion layers,
Reference numerals 13 are connected to the metal bit lines 61 via the block selection transistors 62, respectively. Further, the erase gates 9 in the memory block 64 are all collected in the block and taken out in the row direction. By employing such a configuration, the area selected by the block selection transistor 62 and the erase block can be made the same.

Further, the gate 63 of the block select transistor 62 and the erase gate 9 do not overlap, which is advantageous in the manufacturing process. Further, by changing the number of elements (four in the figure) between the block selection transistors, the size of the erase block can be freely set. Further, by using the block selection transistor 62, the bit line capacity at the time of reading can be significantly reduced, and the reading time at the time of random access can be reduced.

[0030]

In the nonvolatile semiconductor memory device according to the present invention, the FN tunneling via the gate oxide film is not used for the write / erase operation.
nm or more, and there is no deterioration of the gate oxide film due to FN tunneling. For this reason, it is easy to secure long-term reliability of the memory such as deterioration of device characteristics and charge retention. Further, since the drain diffusion layer and the erase gate are formed in the same direction and correspond one-to-one, high-speed data writing and reading can be maintained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of a semiconductor memory device;
(A) is a plan view, and (b) is a cross-sectional view along AA 'shown in (a).

FIG. 2 is a process diagram showing one embodiment of a manufacturing method by a top view.

3A and 3B are diagrams illustrating another embodiment of the semiconductor memory device, wherein FIG. 3A is a plan view, and FIG. 3B is an AA ′ shown in FIG.
FIG.

FIG. 4 is a process diagram showing another embodiment of the manufacturing method by a top view.

FIG. 5 illustrates an embodiment of a memory cell array with reference to FIG. FIG. 5 is a schematic circuit diagram showing a memory block of the embodiment.

FIG. 6 is a schematic circuit diagram showing the memory block of FIG. 5 together with a block selection transistor.

[Explanation of symbols]

 2 Drain diffusion layer 3, 13 Source diffusion layer 4 Gate oxide film 5 Floating gate 6 Insulating layer 7, 11 Silicon oxide film 8 Select gate 9 Erase gate 10 Field oxide film

Claims (6)

[Claims] 1. A memory cell formed on a semiconductor substrate of a first conductivity type having a main plane is formed so as to be arranged in a matrix of rows and columns on the main plane. A MOS type memory having a diffusion layer, a drain diffusion layer, a floating gate, a select gate, and an erase gate, wherein a strip-shaped second conductivity type diffusion layer serving as a source diffusion layer and a drain diffusion layer is formed in a column direction. Adjacent memory cells sandwiching the diffusion layer are symmetrically arranged with respect to the drain diffusion layer so as to share the drain diffusion layer, and a channel is formed between a source diffusion layer and a drain diffusion layer in a memory cell region. A floating gate having a length in a channel length direction shorter than a distance between the source diffusion layer and the drain diffusion layer is formed between the source diffusion layer and the drain diffusion layer by a first insulating film. And formed on each of the memory cells by being shifted toward the drain diffusion layer side through a second insulating film on the drain diffusion layer via a second insulating film. A band-shaped erase gate to be shared is arranged, and a word line shared by memory cells arranged in the row direction of the array and serving also as a select gate electrode of the memory cell is further provided in the upper layer. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor substrate between the layers is formed with a third insulating film interposed therebetween. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a stacked film of a silicon oxide film / silicon nitride film / silicon oxide film is used as said third insulating film. 3. The non-volatile semiconductor memory device according to claim 1, wherein the floating gate and the drain diffusion layer have a region overlapping in a channel length direction via the first insulating film. 4. The drain diffusion layer and the source diffusion layer are alternately formed, and a group of memory cells sharing one drain diffusion layer is used as a block, and adjacent blocks are connected so as to share a source diffusion layer with each other. The nonvolatile semiconductor memory device according to claim 1, wherein: 5. The source diffusion layer and the drain diffusion layer are each connected to a metal bit line via a block selection transistor, and all the erase gates in a block selected by the block selection transistor are electrically connected to each other. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is connected. 6. A method for manufacturing a nonvolatile semiconductor memory device, comprising the following steps (a) to (g). (A) forming a device isolation layer between bits on a semiconductor substrate of a first conductivity type and then forming a first insulating film on the semiconductor substrate; (b) a first polysilicon layer serving as a floating gate Patterning the polysilicon layer so as to open the drain diffusion layer region and the source diffusion layer region, and (c) forming a second conductivity type on the semiconductor substrate using the pattern of the polysilicon layer as a mask. Implanting impurities to form a strip-shaped drain diffusion layer and a source diffusion layer; (d) forming a second layer on the surface of the polysilicon layer, on the source diffusion layer and on the drain diffusion layer by thermal oxidation;
(E) further depositing a second polysilicon layer and patterning the second polysilicon layer to form a strip in a direction parallel to the source diffusion layer and the drain diffusion layer. Forming an erase gate and simultaneously etching a portion of the first polysilicon layer protruding from the erase gate pattern to form a floating gate; (f) a third insulating film on the entire surface of the semiconductor substrate (G) forming a third polysilicon layer thereon and then patterning to form a selection gate in a direction orthogonal to the source diffusion layer, the drain diffusion layer and the erase gate. Process.