JP2003347439A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high integration and high reliability by eliminating variation in the memory cell characteristics due to misalignment. <P>SOLUTION: In the semiconductor memory where a plurality of memory cells are formed while being arranged on a semiconductor substrate, an isolation trench is made at least in a part of the semiconductor substrate between respective memory cells, a part of the isolation trench is filled with an insulating film for isolation and the remainder of the isolation trench is filled with a conductive film, at least a part of the side face of the isolation trench filled with the conductive film is a part of the tunnel part of a memory cell transistor. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a MOS structure, and more particularly to a nonvolatile semiconductor memory device having a floating gate (charge storage layer) and a control gate.

[0002]

2. Description of the Related Art In the field of nonvolatile memory, an electrically rewritable nonvolatile memory device using a memory cell having a MOSFET structure having a floating gate is known as an EEPROM. A memory array of this type of EEPROM is configured by arranging a memory cell at each intersection of a row line and a column line that cross each other. On an actual pattern, the drains of the two memory cells are made common, and the column lines are brought into contact with each other so that the cell occupation area of the contact portion is made as small as possible. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell.

On the other hand, recently, there has been proposed an EEPROM in which memory cells are connected in series to form a NAND cell and the number of contacts can be greatly reduced. In this NAND cell, after performing the entire erasure (batch erasure) of emitting electrons from the floating gate in a lump, writing for injecting electrons into the floating gate is performed only in the selected memory cell. At the time of full erasing, the control gate is set to the "L" level and the well is set to the "H" level. In the selective writing, writing is performed in order from the cell on the source side to the cell on the drain side. In this case, the potential of the selected cell is changed from the "L" level to the intermediate level at the drain and the "H" level at the control gate, whereby electrons are injected into the floating gate from the substrate.

In a non-selected cell located on the drain side of the selected cell, the potential of the control gate is made substantially equal to the potential applied to the drain in order to transmit the potential applied to the drain to the selected cell. There is a need. Because,
This is because the voltage applied to the drain is transmitted to the source only up to a voltage obtained by subtracting the threshold voltage of the cell from the voltage applied to the control gate.

However, in the conventionally proposed NAND cell, since the floating gate is arranged across the channel region, the threshold voltage of the cell is uniquely determined by the potential of the floating gate. Therefore, when the threshold voltage of the cell becomes higher than the voltage (normally Vcc) applied to the control gate of the non-selected cell at the time of reading, the non-selected cell is not turned on and the data of the selected cell cannot be read. .

FIG. 14 shows a threshold voltage distribution of the memory cell in this case. At the time of reading, the control gate (C
G) is applied with Vcc = 4.5-5.5 V to turn on both the write side and erase side memory cells. If the write-side memory cell threshold becomes higher than Vcc (for example, 6 V)
, The selected cell is not turned on and cannot be read.

When the threshold voltage of a memory cell is determined by the floating gate potential in this way, the threshold voltage of a certain memory cell increases as a result of variations in the threshold voltage at the time of writing. There is a possibility that the memory cell cannot be turned on by the control gate voltage of the non-selected cell at the time of reading.

Conventionally, FIGS.
A NAND cell as shown in a circuit diagram and a sectional view has been proposed.
ing. That is, the substrate 1 separated by the element isolation region 2
The diffusion layer 7 forming the source / drain is formed in the region of FIG.
And the first gate insulating film 3_TwoThrough
Floating gate 4 (4₁~ 4_Four), Second gate insulating film 3 ₁
And a third gate insulating film 3_ThreeThrough the control gate 6 (6
₁~ 6_Four) Are provided, and a bit line is
9 are arranged. This NAND cell has a floating gate
4 has a structure that extends over a part of the channel portion.
The state that the play gate 4 does not completely cross the channel region
State, that is, the channel region is divided with respect to the channel width direction.
11 and 12 in the uncovered part.
Transistor (T₁~ T_Four) Form the memory cell
The threshold voltage of the floating gate 4
Not be determined by the part of the channel region
Features.

However, this cell has the following problem. In other words, there is a problem that when the misalignment between the element region and the floating gate occurs, the element characteristics greatly change.
As shown in FIG. 11 and FIG. 13 (a), the cause overlap x is the change in the floating gate 4 and the gate insulating film 3 ₂ by misalignment of the element region and the floating gate, by a change in the x, floating gates The characteristics of the memory cells in particular, especially the coupling ratio, change, whereby the write voltage and read current change significantly. In addition, the characteristics of Tr (T _{1 to} T _{4 in} FIGS. 11 and 12) in the portion not covered by the floating gate also vary, and due to the misalignment, the characteristics of the memory cell as a whole largely change.

Further, when the channel width is reduced in accordance with the high integration, the misalignment is further increased, which affects the characteristics of the memory cell. For this reason, when the degree of integration and miniaturization are increased, the problem of misalignment becomes more apparent, which has hindered the degree of integration and miniaturization. Further, the problem of the misalignment can be similarly applied not only to the NAND cell but also to the NOR cell.

[0011]

As described above, in the conventional memory cell in which the floating gate partially covers the channel portion,
There has been a problem that the misalignment between the floating gate and the element region greatly changes the characteristics of the memory cell. further,
This problem increases with miniaturization, and is a major factor hindering miniaturization.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to eliminate variations in memory cell characteristics due to misalignment and achieve high integration and high reliability. Is to provide.

[0013]

(Structure) In order to solve the above-mentioned problem, the present invention employs the following structure.

That is, according to the present invention, a plurality of memory cells are arrayed and formed on a semiconductor substrate, and an element is provided on at least a part of the semiconductor substrate between the memory cells along a channel length direction of a cell transistor constituting the memory cell. A semiconductor memory device in which an isolation groove is formed, a part of the element isolation groove is embedded with an element isolation insulating film, and the remaining part of the element isolation groove is embedded with a conductive film. At least a part of the side surface of the element isolation trench buried with a film was set as a part of a channel portion of the transistor, and a threshold value thereof was set higher than a read voltage applied to a gate electrode of the selected cell transistor. It is characterized by the following.

Further, according to the present invention, a first conductive layer is provided on a semiconductor substrate via a first insulating film, and a second conductive layer is provided on the first conductive layer.
A memory array is formed by connecting a plurality of memory cells each having a second conductive layer formed thereon through an insulating film and arranging them in a matrix, and forming at least a part of an isolation region of the memory cells. An element isolation groove is formed in a semiconductor substrate along a channel length direction of a cell transistor constituting the memory cell, a part of the element isolation groove is buried with an element isolation insulating film, and the element isolation groove is formed. Is a non-volatile semiconductor memory device in which the remaining portion is embedded with the second conductive layer, wherein the first conductive layer at least partially covers a first channel region on a substrate surface in a channel width direction;
Forming a two-level memory cell having the first conductive layer as a charge storage layer and the second conductive layer as a control gate, wherein a side surface of the element isolation trench buried with the second conductive layer; At least a part of the second channel region, a transistor using the second conductive layer as a gate, and a threshold voltage of the transistor using the second conductive layer as a gate,
It is characterized in that the voltage is higher than the voltage applied to the control gate selected at the time of reading.

Further, according to the present invention, a first conductive layer is provided on a semiconductor substrate via a first insulating film, and a second conductive layer is provided on the first conductive layer.
A memory array is formed by connecting a plurality of memory cells each having a second conductive layer formed thereon through an insulating film and arranging them in a matrix, and forming at least a part of an isolation region of the memory cells. An element isolation groove is formed in a semiconductor substrate along a channel length direction of a cell transistor constituting the memory cell, a part of the element isolation groove is buried with an element isolation insulating film, and the element isolation groove is formed. Is a non-volatile semiconductor memory device in which the remaining portion is embedded with the second conductive layer, wherein the first conductive layer at least partially covers a first channel region on a substrate surface in a channel width direction;
The first conductive layer is a charge storage layer, the second conductive layer is a control gate, and a memory cell for storing at least n levels of n levels is formed and buried with the second conductive layer. Forming a transistor in which at least a part of the side surface of the device isolation groove is a part of a second channel region and using the second conductive layer as a gate, wherein the second conductive layer is a gate. The threshold voltage of the transistor to be changed from the lower threshold to n−1
The voltage is higher than the voltage applied to the control gate selected at the time of reading to determine the nth and nth levels.

(Operation) According to the semiconductor memory device of the present invention, the side surface of the element isolation groove formed in the semiconductor substrate is used as a channel of a transistor, and the substrate surface is configured as a memory cell via a floating gate. In addition, unlike a conventional memory cell in which a portion of the substrate surface not covered by the floating gate has a channel, a memory cell having uniform characteristics can be obtained without causing variations in characteristics due to misalignment.

Further, since the side surface of the groove is used as a channel, a fine memory can be formed without increasing the area of the memory cell, and the cost can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

1 to 3 illustrate a nonvolatile semiconductor memory device (NAND type EEPROM) according to an embodiment of the present invention. FIG. 1 is a plan view showing two NAND cell portions, and FIG. 3 is a sectional view taken along the line AA 'of FIG. 1 (memory cell portion), and FIG. 3 is a sectional view taken along the line BB' of FIG. In FIG. 1, M (M _{1 to} M ₈ ) denotes a memory cell, and S (S ₁ , S ₂ ) denotes a selection transistor.

1 to 3, an n-type silicon substrate 10
Is provided with an element isolation groove (trench) 11, and an insulating film 12 is buried in the element isolation groove (trench) 11. A first gate insulating film (tunnel oxide film) 13 is formed on the surface of the n-type silicon substrate 10, and a first gate electrode (floating gate) made of a first conductive film is formed on the gate insulating film 13. g) 30 (30 ₁ to 30 ₈₎ is formed. Further, a second gate electrode (control gate) 29 made of a second conductive film is provided so as to fill the trench via the second gate insulating film, and an interlayer insulating film is provided thereon. 24 are formed. Reference numeral 17 denotes an element isolation region, 18 denotes an element region, and 23 denotes a source / drain diffusion layer.

As described above, in the present embodiment, the floating gate 30 and the control gate 29 are formed on the substrate surface via the tunnel oxide film 13, and the control gate 29 covering the side surface of the trench used for element isolation is formed. The transfer transistor is included as a gate electrode. With such a structure, a change in characteristics of the memory cell due to misalignment is suppressed. Further, in the memory cell according to the present embodiment, since the side wall of the floating gate is also used as the capacitance between the floating gate and the control gate, the coupling ratio can be increased, and the coupling ratio can be increased in consideration of the gate width. It has the characteristic that it can be controlled.

FIG. 4 shows an example of an equivalent circuit of the NAND cell shown in FIGS. FIG. 4 shows four cells connected in series. T _{1 to} T ₄ are transfer transistors each having the side surface of the trench isolation as a channel, and M _{1 to} M ₄
Denotes a memory cell portion having a floating gate formed on a substrate.

The operating voltage of each part of the NAND cell shown in FIGS. 1 to 3 is as shown in the following (Table 1).

[0025]

[Table 1] FIG. 1 shows the threshold distribution of the memory cell according to the present embodiment.
It is shown in FIG. Of memory cell threshold (floating gate - DOO portion of threshold), the unselected gates - Tr (T ₁ through T ₄₎ of the memory cell even if the above Vcc is applied to the bets is turned ON For this reason (the threshold value of T _{1 to} T ₄ is about 0 to ₄ V), it is not necessary to set the threshold value in the range of 0.5 to 3.5 V. FIG.
Then, after writing, it is in the range of about 1 to 7V.

The threshold values of the parts T _{1 to} T ₄ are set in the following ranges. The lower limit of the threshold is determined by the voltage applied to the selected control gate when reading. In this case, it is 0V. The upper limit of the threshold value is determined by the voltage applied to the unselected control gate at the time of reading. In this case, 4.
5 to 5.5V. That is, the threshold value must be set in the range of 0 to 4.5V.

Next, the manufacturing process of the memory cell of this embodiment will be described with reference to FIG. These drawings correspond to the cross section taken along the line AA 'in FIG.

First, for example, as shown in FIG.
For example, a surface silicon concentration of 1
A p-well 40 of × 10 ¹⁶ cm ^-3 is formed, and an appropriate channel implantation is performed in a region where a gate is formed to adjust a threshold value. Subsequently, a thermal oxide film (gate insulating film) 13 having a thickness of, for example, 10 nm is formed on the surface of the p-well 40, and a first-layer polycrystalline silicon film 30 is deposited to have a thickness of, for example, 400 nm as a gate electrode. Next, an oxide film (not shown) is formed on the polycrystalline silicon film 30 by, for example, 18 nm.
After that, an oxide film 19 serving as a mask at the time of trench RIE is formed thereon by a CVD method to a thickness of, for example, 350 nm.
Deposited to a thickness of

Next, as shown in FIG. 5B, after patterning a resist for forming an element isolation region by a photolithography process, CVD oxidation is performed using this resist pattern (not shown) as a mask. Membrane 19,
The polycrystalline silicon film 30 and the gate oxide film 13 are selectively etched by anisotropic etching, and the surface of the p well 40 is selectively etched by anisotropic etching to form an element isolation trench (trench) 11. At this time, the etching is performed by CVD using a resist pattern as a mask.
Etching from the oxide film 19 to the silicon substrate 10,
Finally, the resist pattern may be stripped, or the resist pattern may be stripped after etching the CVD oxide film 19 using the resist pattern as a mask, and the polycrystalline silicon film 30 may be stripped using the CVD oxide film 19 as a mask. The gate oxide film 13 and the silicon substrate 10 may be etched.

Next, in order to remove the damage generated at the time of forming the trench, a heat treatment is performed in, for example, a nitrogen atmosphere or an inert gas atmosphere. The trench side wall is thermally oxidized in an oxidizing atmosphere containing water vapor. Here, an impurity may be implanted into the side wall of the trench or the bottom of the trench to prevent field inversion.

Thereafter, as shown in FIG. 5C, a CV using TEOS gas is
By the method D, the SiO ₂ film 12 is deposited to a thickness of, for example, 1000 nm. Next, until the polycrystalline silicon film 30 is exposed and a part of the Si substrate on the side wall of the trench is exposed.
The oxide film 12 is etched back by RIE. At this time, the polycrystalline silicon film 30 functions as an etch-back stopper. For this etch back, an etch back technique using a resist may be used, or polishing may be used.

Next, the polycrystalline silicon film 30 is doped with, for example, phosphorus, so that the polycrystalline silicon film 30 has a phosphorus concentration of 1%.
× 10 ²⁰ cm ^-3 . This polycrystalline silicon doping may be performed immediately after the polycrystalline silicon film 30 is deposited. Next, for example, B (boron) is supplied at 30 keV, 1 × 1.
Ion implantation is performed at an angle of 0 ¹³ cm ^{-2 at an} oblique angle of 60 degrees so that the threshold value at the side wall of the trench is, for example, 2V. further,
A silicon oxide film or an oxide film 31 such as ONO is formed on the polycrystalline silicon film 30 and on the side walls of the trench by, for example, 20 nm.
Formed to a thickness of At this time, for example, 850 to 900 ° C.
When thermal oxidation in a dry O ₂ for, although on the polycrystalline silicon is approximately 10~20nm thickness forming an oxide film of approximately 40nm thick trench sidewall portion is grown. This film functions as a capacitance film between the floating gate and the control gate, and serves as a gate insulating film of the transfer transistor on the side wall of the trench.

Next, as shown in FIG. 6A, a second layer polycrystalline silicon film 29 serving as a control gate is formed in the cell portion.
A second-layer polycrystalline silicon film serving as a gate electrode is deposited to a thickness of, for example, 200 nm in the peripheral portion.

Next, as shown in FIG. 6B, the second-layer polycrystalline silicon film 29 (20) and the oxide film 3 are formed using the linear resist pattern in the word line direction as a mask.
1. The first layer polycrystalline silicon film 30 (15) is selectively etched by RIE to separate a memory cell and a select transistor in the word line direction. Then, a source / drain diffusion layer is formed, the entire surface is covered with a CVD oxide film, a contact hole is opened, and a bit line 28 is provided with an Al film, thereby completing a memory cell.

Next, FIG. 7 will be described with respect to a memory cell according to another embodiment.

In the example shown in FIG. 7A, the SiO ₂ film buried in the trench isolation (groove) is deeply etched every other trench to form a channel portion of the trench Tr (transfer transistor). I do. By deeply etching the SiO ₂ film on only one side of the control gate 30 in this way, the controllability of the channel width of the transfer transistor is further improved as compared with the case where both sides are deeply etched.

In the example shown in FIG. 7B, about half of the width direction of the SiO ₂ film embedded in the trench isolation (groove) is deeply etched. As shown in the figure, by etching about half of the width direction of the SiO ₂ film to the bottom of the trench, the controllability of the channel width is further improved.

Next, still another embodiment of the present invention will be described.

In the memory cell according to the above embodiment,
Although the insulating film between the floating gate and the control gate and the gate insulating film of the transfer transistor are formed at the same time, in this embodiment, they are formed separately.

The steps up to FIGS. 8A and 8B are described in FIG.
Since these steps are the same as steps (a) and (b), the description is omitted.
In the present embodiment, the CVD SiO ₂ buried in the trench is used.
The twelve etch-back steps of the membrane are different. That is, FIG.
As shown in (c), the RIE is adjusted so that the etch-back RIE is stopped at the side wall of the polycrystalline silicon film 30.

Next, as shown in FIG. 9A, a film serving as an insulating film between the floating gate and the control gate, for example,
An ONO film 71 having a thickness of nm is formed, for example, a polycrystalline silicon film 72 is deposited to a thickness of 50 nm, and an oxidation resistant film, for example, a SiN film 73 is deposited to a thickness of 30 nm. At this time, the SiN film 73 is deposited thick on the floating gate 30 and thin on the trench.

Next, as shown in FIG.
Removes the SiN film 73 on the trench element isolation.
At this time, since the floating gate is thickly deposited, S
The iN film 73 can be left without being entirely removed. Next, the polycrystalline silicon film 72 on the trench element isolation, ON
The O film 71 and the SiO ₂ film buried in the upper part of the trench are removed by etching.

Thereafter, as shown in FIG. 10A, a gate oxide film 74 of the transfer transistor is formed to a thickness of, for example, 50 nm by, for example, thermal oxidation. Further, the SiN film 73 on the side wall of the floating gate 30 is selectively removed with, for example, hot phosphoric acid.

Next, as shown in FIG. 10B, for example, a polycrystalline silicon film 75 is deposited to a thickness of 300 nm.
Perform doping. At this time, the previously formed polycrystalline silicon film 72 and polycrystalline silicon film 75 are in electrical contact with each other and serve as a control gate. Hereinafter, a memory cell structure is obtained by the same steps as in the previous embodiment.

In this embodiment, since the insulating film between the floating gate and the control gate and the transfer gate insulating film can be formed separately, there is an advantage that the design of each transistor is facilitated.

Next, another embodiment of the present invention will be described with reference to FIGS. In this embodiment, 4 cells are stored in one cell.
1 shows a so-called multi-valued logic cell, which makes up one memory level. FIG. 16 shows a threshold value of a conventional quaternary memory cell. The Vth of the conventional memory cell is, for example, Vth <-1V at "0" level and 0.5V <Vth <at "1" level.
1.5V, "2" level is 2.5V <Vth <3.5V,
The “3” level is 4.5V <Vth <5.5V. This is because the memory cell must be turned on with a voltage (in this case, 6.5 to 7.5 V) applied to the non-selected cell (CG), as shown in FIG. The following Table 2 shows the voltage relationship at the time of reading.

[0047]

[Table 2] FIG. 17 shows a threshold value of a memory cell when the cell of this embodiment is applied to multi-valued logic. Even if the threshold voltage of the memory cell becomes higher than the unselected word line voltage of 6.5 to 7.5 V, the transfer Tr (T1 to T4) becomes O.
Since it is N, it is not necessary to control the threshold width of the level “3” to be narrow, and in this example, it can be set to about 5.5 to 9V.
For this reason, it is possible to increase the threshold width of the levels “1” and “2”. In this example, the level “1” is 0.
5V to 1.5V, and the "2" level is 3.0V to 4.5V, which can be 0.5V wider than the conventional example.

The threshold value of the transfer Tr is
In this embodiment, the voltage is 5 V or more and 6.5 V or less. If the voltage is 5 V or less, the transfer gate is turned on even if the threshold value of the floating gate is "3", and the level is set to "2" or less. Also, if 6.5V
If it is above, it does not turn on when not selected and the selected cell cannot be read. That is, the threshold value of the transfer Tr is higher than the voltage applied to the selected control gate of the NAND cell selected at the time of reading which determines “2” and “3”, and the selected NAND cell is not selected. It must be lower than the voltage applied to the control gate.

In this embodiment, a quaternary multi-valued logic cell is shown. However, the present invention can be applied to ternary, octal and 16-valued multi-valued logic cells. For example, consider an n-valued multi-valued logic cell. Transfer T in this case
The threshold value of r is higher than the voltage applied to the selected control gate of the selected NAND cell at the time of reading to determine the (n-1) th and the nth from the lower side of the threshold value. It must be set to a value lower than the voltage applied to the unselected control gates.

Next, the case of a NOR type cell will be described.

FIG. 18A is a plan view showing the above cell, FIG. 18B is an equivalent circuit diagram thereof, and FIG.
FIG. 19A is a sectional view taken along the line XX ′, and FIG.
It is sectional drawing of the ZZ 'direction of (a). FIG. 20 shows a threshold distribution in the case of four values.

In this case, the threshold value of the transfer Tr must be equal to or higher than the control gate voltage for judging the levels of “2” and “3”, that is, 6 V or higher. If the voltage is 6 V or more, the transfer Tr is turned on and normal reading cannot be performed. In the case of the n value, the transfer Tr must have a threshold higher than the voltage applied to the control gate selected in the read operation for determining the (n-1) th and the nth from the lower threshold. .

FIG. 21A is a sectional view of the element structure.
As shown in the equivalent circuit diagram in FIG. 2B, a transistor in series with the transistor in the floating gate portion can be formed by burying a gate electrode (control gate) in a groove formed in the substrate. The transistor formed in the groove is connected in series to a memory cell (having a floating gate) transistor. This cell is applicable to the NOR type cell shown in FIG. In this case,
The punch-through resistance between the source and the drain, which has hindered miniaturization, is improved, and further miniaturization is possible.

FIG. 21 shows a structure in which the control gate is filled with the poly-Si in the entire groove, but it may be part of the groove. Further, the poly-Si of the floating gate may be partially formed in the groove. FIG. 22 shows an equivalent circuit diagram when this cell is applied to a NAND type.

FIGS. 23 to 25 show an embodiment in which a cell in which a floating gate transistor and a transfer transistor are connected in series is applied to a so-called ground array cell in which the source and the drain are shared. FIG. 23 is a plan view, FIG. 24 is an equivalent circuit diagram, and FIG. 25 is a sectional view taken along line AA ′ of FIG. The hatched portion in FIG. 23 is a floating gate. In FIG. 25, reference numeral 80 denotes a Tr gate oxide film having a control gate embedded in the trench as a gate electrode.

The operation of this embodiment will be described. The operating voltages are as shown in (Table 3) below.

[Table 3] This is the case where the cell marked with a circle in FIG. 24 is selected.

In the read operation, a current flows from BL1 to the source via the cell and is detected. Erasing is performed by injecting electrons into the floating gate. For writing, a voltage is applied to BL and WL2, and floating gate to drain (FIG. 25)
The electron is removed to n ⁺ ). 5V or 0 at BL during writing
When V is applied to remove electrons, the erased state is maintained without removing electrons.

FIGS. 26 to 29 show still another embodiment.
These cells can be implemented by replacing the cell part of the embodiment shown in FIGS.

FIG. 26 shows a case where a floating gate is formed only at the bottom of a groove and a side wall is a transistor.
FIG. 28 shows a structure in which the n ⁺ layer on one side is extended to the floating gate portion, FIG. 28 shows a structure in which the floating gate is formed on the substrate surface, and FIGS. 29A and 29B show a case in which the floating gate is formed on the substrate surface. An n + layer is formed.

FIGS. 30A and 30B are equivalent circuit diagrams in the case where the n ⁺ portion of the ground array is separated from the adjacent cells. These are shown in FIGS. 31A and 31B and FIG.
This can be implemented with the cross-sectional structure shown in FIG. That is, an n ⁺ portion is formed on the side surface of the groove to serve as a source or a drain, and is separated from an adjacent n ⁺ layer by groove separation. These operations are the same as those shown in the above (Table 3).

FIG. 33 shows still another embodiment. FIG.
FIG. 4 shows a diagram in which the cells shown in FIG. 33 are arranged in an array. The erase gate (EG) is provided in parallel with the CG.
The operating voltage is shown in Table 4 below.

[0062]

[Table 4] The program injects charge into the floating gate by hot electron injection, and Erase removes electrons from the floating gate to the EG. Also in the case of this cell, it is possible to dispose the side gate electrode of the groove as shown in FIGS. By doing so, the effective gate length of both the floating gate portion and the control gate portion can be increased, and problems such as punch-through between the source and drain can be avoided even when the device is miniaturized.

The present invention is not limited to the above embodiments. In the above embodiments, the NAND cell type EEPROM has been described as an example, but the present invention is not limited to this, and can be applied to various EEPROMs and EPROMs. Specifically, the control gate type EEPR
EEP using MNOS type memory cells, not limited to OM
It can also be applied to ROM. Further, the present invention can be applied to a so-called mask ROM in which a MOS transistor in which information is fixedly written by channel ion implantation or the like is used as a memory cell instead of an EEPROM.

Further, the present invention can be applied to a ground array type, a FACE type, and an AND type cell having a diffusion layer bit line. Furthermore, a DINOR having a sub-bit line
Applicable to molds. In addition, the present invention can be widely applied to various memories other than those described above, and can be variously modified and implemented without departing from the gist of the present invention.

[0065]

As described above in detail, according to the present invention, since the trench element isolation side surface is used as a transfer transistor, the characteristics of the element can be stabilized without variation and non-uniformity due to misalignment. A memory cell can be formed. As a result, the occupation area does not increase, and a high-density and low-cost memory can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view showing a memory cell according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a sectional view taken along the line BB ′ of FIG. 1;

FIG. 4 is an equivalent circuit diagram of a memory cell according to one embodiment of the present invention.

FIG. 5 is a sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

FIG. 6 is a sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

FIG. 7 is a sectional view showing a memory cell according to another embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a memory cell according to still another embodiment of the present invention.

FIG. 9 is a sectional view showing a manufacturing process of a memory cell according to still another embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing step of a memory cell according to still another embodiment of the present invention.

FIG. 11 is a plan view of a conventional memory cell.

FIG. 12 is an equivalent circuit diagram of a conventional memory cell.

FIG. 13 is a sectional view taken along line AA ′ and BB ′ in FIG. 10;

FIG. 14 is a diagram showing a threshold distribution of a conventional memory cell.

FIG. 15 is a diagram showing a threshold distribution of a memory cell according to an embodiment of the present invention.

FIG. 16 is a diagram showing a threshold distribution when a conventional memory cell is applied to multi-valued logic.

FIG. 17 is a view showing a threshold distribution when a memory cell according to one embodiment of the present invention is applied to multi-valued logic.

FIG. 18 is a plan view and an equivalent circuit diagram when the present invention is applied to a NOR type cell.

FIG. 19 is a cross-sectional view in the XX ′ direction and the ZZ ′ direction of FIG.

FIG. 20 is a diagram showing a threshold value distribution in the case of four values in a NOR type cell.

21A and 21B are an element structure cross-sectional view and an equivalent circuit diagram illustrating an example in which a transistor in series with a transistor in a floating gate portion is formed by embedding a control gate in a trench.

FIG. 22 is an equivalent circuit diagram when the configuration in FIG. 21 is applied to a NAND type.

FIG. 23 is a plan view showing an embodiment in which the present invention is applied to a ground array cell.

FIG. 24 is an equivalent circuit diagram showing an embodiment in which the present invention is applied to a ground array cell.

FIG. 25 is a sectional view taken along line AA ′ of FIG. 23;

FIG. 26 is a sectional view of an element structure and an equivalent circuit diagram showing still another embodiment of the present invention.

FIG. 27 is an element structure sectional view showing still another embodiment of the present invention.

FIG. 28 is an element structure sectional view showing still another embodiment of the present invention.

FIG. 29 is a sectional view of an element structure showing still another embodiment of the present invention.

FIG. 30 is an equivalent circuit diagram in a case where an n + portion of the ground array is separated from an adjacent cell.

FIG. 31 is a sectional view of an element structure for realizing the circuit of FIG. 30;

FIG. 32 is an element structure sectional view for realizing the circuit of FIG. 30;

FIG. 33 is an equivalent circuit diagram showing still another embodiment of the present invention.

FIG. 34 is a diagram in which the cells shown in FIG. 33 are arranged in an array.

[Explanation of symbols]

1, 40 ... p-type well, floating consisting 2,17 ... isolation region 3 ... gate insulating film 3 ₁ ... gate insulating film 3 ₂ ... tunnel insulating film 3 ₃ ... sidewall insulating films 4, 30 ... first conductive layer Gates 6, 29: Control gates made of a second conductive film 7, 23 ... Source / drain diffusion layers 8, 24 ... Interlayer insulating film 9 ... Bit line 11 ... Trench for element isolation 12 ... Buried insulating film 13 ... Gate Insulating film 20: gate electrode 72 made of second conductive film Polysilicon film 73 SiN film 74 Transfer gate insulating film 75 polycrystalline film

   ────────────────────────────────────────────────── ─── Continuation of front page    F term (reference) 5F083 EP02 EP18 EP25 EP27 EP30                       EP35 EP55 EP76 EP77 ER02                       ER03 ER15 ER22 JA04 JA19                       JA36 NA01 PR03 PR12 PR33                       PR36 PR39 ZA21                 5F101 BA02 BA29 BA36 BA46 BB04                       BC02 BC11 BD13 BD33 BD34                       BD35 BF05 BH03 BH09 BH14                       BH16

Claims (9)

[Claims] A plurality of memory cells are arrayed and formed on a semiconductor substrate, and at least a part of the semiconductor substrate between the memory cells is provided with an element isolation groove along a channel length direction of a cell transistor constituting the memory cell. A semiconductor memory device in which a part of the element isolation groove is embedded with an element isolation insulating film, and the remaining part of the element isolation groove is embedded with a conductive film. At least a part of the side surface of the element isolation groove is used as a part of a channel portion of the transistor, and a threshold thereof is set higher than a read voltage applied to a gate electrode of the selected cell transistor. Semiconductor storage device. 2. The method according to claim 1, wherein the first insulating film is formed on the semiconductor substrate via a first insulating film.
A plurality of memory cells each having a second conductive layer formed on the first conductive layer via a second insulating film are connected to each other and arranged in a matrix to form a memory array. An element isolation groove is formed in at least a part of a semiconductor substrate of an isolation region of the memory cell along a channel length direction of a cell transistor constituting the memory cell, and a part of the element isolation groove is formed. Is embedded in an insulating film for element isolation, and the remainder of the trench for element isolation is embedded in the second conductive layer, wherein the first conductive layer is formed on a first surface of a substrate surface. Forming a two-level memory cell that at least partially covers the channel region in the channel width direction, uses the first conductive layer as a charge storage layer, and uses the second conductive layer as a control gate. Device isolation embedded with a conductive layer of At least a part of the side surface of the groove is used as a part of the second channel region, and the second conductive layer is formed as a gate.
Wherein the threshold voltage of the transistor having the gate of the second conductive layer is higher than the voltage applied to the control gate selected at the time of reading. Storage device. 3. A first insulating film on a semiconductor substrate with a first insulating film interposed therebetween.
A plurality of memory cells each having a second conductive layer formed on the first conductive layer via a second insulating film are connected to each other and arranged in a matrix to form a memory array. An element isolation groove is formed in at least a part of a semiconductor substrate of an isolation region of the memory cell along a channel length direction of a cell transistor constituting the memory cell, and a part of the element isolation groove is formed. Is embedded in an insulating film for element isolation, and the remainder of the trench for element isolation is embedded in the second conductive layer, wherein the first conductive layer is formed on a first surface of a substrate surface. At least partially covering the channel region in the channel width direction, the first conductive layer as a charge storage layer, and the second conductive layer as a control gate,
A memory cell for storing n levels of two or more levels is formed, and at least a part of a side surface of the element isolation groove buried with the second conductive layer is a part of a second channel region. A transistor using the second conductive layer as a gate, and setting the threshold voltage of the transistor using the second conductive layer as a gate to the (n-1) th and nth from the lower threshold.
A non-volatile semiconductor memory device characterized in that the voltage is higher than a voltage applied to the control gate selected at the time of reading in which a third level is determined. 4. The transistor according to claim 1, wherein a transistor having at least a part of a side surface of said isolation trench as a channel portion shares a source and drain diffusion layer with said cell transistor. Or a semiconductor memory device according to any one of the above. 5. The NOR type cell according to claim 1, wherein a plurality of said memory cells are connected in parallel to form a NOR type cell.
The semiconductor memory device according to any one of the above. 6. A plurality of memory cells are arrayed and formed on a semiconductor substrate, and element isolation trenches are formed in at least a part of the semiconductor substrate between the memory cells along a channel width direction of a cell transistor constituting the memory cell. A semiconductor memory device in which a part of the element isolation groove is embedded with an element isolation insulating film, and the remaining part of the element isolation groove is embedded with a conductive film. A semiconductor memory device, wherein at least a part of the side surface of the element isolation groove is used as a channel portion of a transfer transistor, and the cell transistor and the transfer transistor are connected in series. 7. A semiconductor device comprising: a first insulating film on a semiconductor substrate;
A plurality of memory cells each having a second conductive layer formed on the first conductive layer via a second insulating film are connected to each other and arranged in a matrix to form a memory array. An element isolation groove is formed in at least a part of a semiconductor substrate of an isolation region of the memory cell along a channel width direction of a cell transistor constituting the memory cell, and a part of the element isolation groove is formed. Is filled with an element isolation insulating film, and the remaining part of the element isolation groove is the first or second element isolation groove.
A non-volatile semiconductor memory device embedded with a conductive layer, wherein the first conductive layer at least partially covers a first channel region on a substrate surface in a channel width direction; A two-level cell transistor having a charge accumulation layer and a second conductive layer as control gates is formed, and at least a part of a side surface of the element isolation groove buried with the second conductive layer is formed as a second layer. A transfer transistor having the second conductive layer as a gate as a part of the channel region of
A semiconductor memory device, wherein the cell transistor and the transfer transistor are connected in series. 8. A semiconductor device comprising: a first insulating film on a semiconductor substrate;
A plurality of memory cells each having a second conductive layer formed on the first conductive layer via a second insulating film are connected to each other and arranged in a matrix to form a memory array. An element isolation groove is formed in at least a part of a semiconductor substrate of an isolation region of the memory cell along a channel width direction of a cell transistor constituting the memory cell, and a part of the element isolation groove is formed. Is filled with an element isolation insulating film, and the remaining part of the element isolation groove is the first or second element isolation groove.
Wherein the first conductive layer is formed along one side surface of the element isolation trench, and the second conductive layer is embedded in the element isolation trench. Are formed along the other side surface, one side surface of the element isolation groove is a first channel region, the first conductive layer is a charge storage layer, and the second conductive layer is a control gate. A two-level cell transistor is formed, and the other side surface of the trench is
And a transfer transistor using the second conductive layer as a gate, wherein the cell transistor and the transfer transistor are connected in series. 9. A semiconductor device comprising: a first insulating film formed on a semiconductor substrate;
A plurality of memory cells each having a second conductive layer formed on the first conductive layer via a second insulating film are connected to each other and arranged in a matrix to form a memory array. An element isolation groove is formed in at least a part of a semiconductor substrate of an isolation region of the memory cell along a channel width direction of a cell transistor constituting the memory cell, and a part of the element isolation groove is formed. Is filled with an element isolation insulating film, and the remaining part of the element isolation groove is the first or second element isolation groove.
Wherein the first conductive layer is formed at the bottom of the element isolation groove, and the second conductive layer is formed in the element isolation groove. 1
A two-level cell transistor formed on the conductive layer having a bottom portion of the device isolation groove as a channel region, the first conductive layer as a charge storage layer, and the second conductive layer as a control gate. A transfer transistor having a side surface of the device isolation groove as a second channel region and a gate of the second conductive layer, wherein the cell transistor and the transfer transistor are connected in series. A semiconductor memory device characterized by the following.