CN102956537A - Shallow slot isolation structure and manufacturing method - Google Patents

Shallow slot isolation structure and manufacturing method Download PDF

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CN102956537A
CN102956537A CN2011102494430A CN201110249443A CN102956537A CN 102956537 A CN102956537 A CN 102956537A CN 2011102494430 A CN2011102494430 A CN 2011102494430A CN 201110249443 A CN201110249443 A CN 201110249443A CN 102956537 A CN102956537 A CN 102956537A
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trap
layer
semiconductor substrate
silicon nitride
oxide layer
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CN102956537B (en
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刘金华
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

Provided is a shallow slot isolation structure and a manufacturing method. The shallow slot isolation structure is formed by secondary etching, secondary filling and secondary polishing, and a formed STI structure is not a rectangular structure or a trapezoid structure in the prior art but a stereostructure with a wide middle and a narrow top and a narrow bottom. Therefore, even if two sides of the STI structure of an n pit and a p pit are not symmetrical caused by mask shifting during the n pit or the p pit manufacturing, active area communication of the p pit and the n pit is not caused, or active area communication of the n pit and the p pit is not caused due to the existing of the wide middle of the STI structure. Since an upper area of the STI structure is manufactured, the manufactured STI structure is guaranteed to be in a semiconductor substrate and is not higher than the semiconductor substrate. Therefore, by the aid of the method and the STI structure, during subsequent n pit or p pit manufacturing and under the condition of the mask shifting, active areas in the p pit and the n pit are guaranteed to be completely isolated or active areas in the n pit and the p pit are guaranteed to be completely isolated. And by the aid of the method and the STI structure, an active area of the semiconductor substrate is guaranteed to be completely isolated.

Description

A kind of shallow groove isolation structure and manufacture method
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of making shallow groove isolation structure and manufacture method.
Background technology
In the manufacturing process of semiconductor device, comprise and make shallow-trench isolation (STI, Shallow Trench Isolation) structure on the Semiconductor substrate, the making of sti structure is a kind of technique of isolated area between the transistor active area that substrate is made.
Fig. 1 is prior art is made sti structure in Semiconductor substrate method flow diagram, and the process cross-sectional view of making sti structure in conjunction with the prior art shown in Fig. 2 a～Fig. 2 d in Semiconductor substrate is elaborated:
Step 101, provide Semiconductor substrate 11, Semiconductor substrate 11 is carried out oxidation, form the first oxide layer 12, shown in Fig. 2 a;
Step 102, at formed the first oxide layer 12 surface depositions the first silicon nitride layer 13, shown in Fig. 2 b;
In this step, the deposition of the first silicon nitride layer 13 adopts low-pressure chemical vapor deposition (LPCVD) mode to carry out, the first silicon nitride layer 13 that deposits is on the one hand in the hard mask protection Semiconductor substrate of follow-up conduct, on the other hand in follow-up polishing process as etching stop layer;
Step 103, employing photoetching and etching technics form sti structure grooves 14 in Semiconductor substrate 11, and this sti structure groove 14 is used for isolating follow-up n trap and the p trap that forms in Semiconductor substrate 11, shown in Fig. 2 c;
The detailed process of this step is: after the first silicon nitride layer 13 applies photoresist layer, adopt sti structure graph exposure and the photoresist layer that develops, form the sti structure pattern at photoresist layer, then take photoresist layer with this sti structure pattern as mask, Semiconductor substrate 11 is carried out dry method ion etching, form sti structure groove 14;
In this step, formed sti structure is rectangular structure, perhaps is inverted trapezoidal structure.
Step 104, at Semiconductor substrate 11 surface depositions the second silicon oxide layer, then form sti structures 15 as the etching stop layer polishing is rear in Semiconductor substrate 11 with the first silicon nitride layer 13, remove the first silicon nitride layer 13 and the first silicon oxide layer 12, shown in Fig. 2 d.
Like this, just formed sti structure in Semiconductor substrate.
After having formed sti structure, form respectively n trap and p trap on the both sides of sti structure, forming process is: the sti structure right half part on Semiconductor substrate 11 surfaces adopts photoetching process to make n trap mask layer, this mask layer can be photoresist layer, then with this n trap mask layer for blocking, carry out the n trap and inject, form the n trap after, remove n trap mask layer, as shown in Figure 3; Similarly, adopt photoetching process to make p trap mask layer in the sti structure left-half on Semiconductor substrate 11 surfaces, then with this p trap mask layer for blocking, carry out the p trap and inject, form the p trap after, removal p trap mask layer.
Follow-uply adopt the mode of Implantation to be manufactured with respectively the source region at p trap and n trap again.
But, form respectively in the process of n trap and p trap on the both sides of sti structure, the photoetching process that adopts is in exposure process, reason owing to exposure bench location semiconductor or manual operation, possibly so that at this moment p trap mask layer or the skew of n trap mask layer, will cause according to p trap and the n trap of p trap mask layer or n trap mask layer made asymmetric on the sti structure both sides, for example the n trap is larger, and the p trap is smaller.Therefore, the follow-up active area of making at the p trap just probably can't be by sti structure and the isolation of n trap, and as shown in Figure 4, perhaps the follow-up active area of making at the p trap just probably can't be by sti structure and the isolation of n trap, so that final semiconductor device failure of making.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of shallow groove isolation structure, the method can guarantee the sti structure of made, in the situation that active area in p trap and the n trap is isolated in the mask skew fully when making n trap or p trap, perhaps isolates the active area in n trap and the p trap fully.
The present invention also provides a kind of shallow groove isolation structure, this structure can guarantee in the situation that when making n trap or p trap the mask skew isolate active area in p trap and the n trap fully, perhaps isolate the active area in n trap and the p trap fully.
Technical scheme of the present invention is achieved in that
A kind of manufacture method of shallow-trench isolation, the method comprises:
Semiconductor substrate is provided, on Semiconductor substrate, forms successively the first oxide layer and the first silicon nitride layer;
Adopt photoetching and etching technics successively etching the first silicon nitride layer and the first oxide layer, form the first groove;
Deposit the second silicon oxide layer, take the first silicon nitride layer as etching stop layer, behind the dry etching, form the second groove in Semiconductor substrate;
Continue to adopt dry etching, between the n of Semiconductor substrate trap and p trap, form with the second groove with the 3rd wide groove;
In the 3rd groove, fill silica, form T-shaped isolation structure in Semiconductor substrate;
Wet-cleaned is carried out the epitaxial growth of Semiconductor substrate after falling the first silicon nitride layer and the first oxide layer, obtains epitaxial loayer;
After the Semiconductor substrate with epitaxial loayer deposits the second oxide layer and the second nitration case, behind the second silicon nitride layer deposition the 3rd silicon oxide layer, be polished to the second silicon nitride layer, form the upper area of sti structure;
Remove the second nitration case and the second oxide layer, formed sti structure.
Adopt photoetching and etching technics successively the process of etching the first silicon nitride layer and the first oxide layer be:
After the first silicon nitride layer applies photoresist layer, adopt width greater than pattern exposure and the photoresist layer that develops of " 1 " the partial width pattern in the T-shaped isolation structure, form width greater than the pattern of " 1 " the partial width pattern in the T-shaped isolation structure at photoresist layer, then take photoresist layer with this pattern as mask, to the first silicon nitride layer and the first oxide layer dry method ion etching, in the first silicon nitride layer and the first oxide layer, form width greater than first groove of " 1 " the partial width pattern in the T-shaped isolation structure.
Described width is not less than the thickness of subsequent deposition the second oxide layer greater than amount.
The described chemical-mechanical planarization CMP method of using that is finished to.
" 1 " part in the described T-shaped isolation structure is inverted trapezoidal structure.
The method also comprises:
On the both sides of described sti structure, make respectively n trap and p trap;
In n trap and p trap, be manufactured with respectively the source region.
A kind of shallow groove isolation structure comprises: have between the n trap in Semiconductor substrate and the p trap: T-shaped structural region and upper area structure, wherein,
T-shaped structural region is positioned at upper area structure below, is made of silica, and the upper area structure consists of by three layers, and three layers is that bottom oxide layer, silicon nitride layer and top layer silicon oxide layer consist of, and width is less than " one " part width of T-shaped structural region.
Described T-shaped structural region " 1 " be inverted trapezoidal structure partly.
Can find out from such scheme, the shallow groove isolation structure of made of the present invention, and be an etching unlike prior art, filling and polishing form, but passed through secondarily etched, secondary filling and second polishing form, formed sti structure and be rectangular structure or inverted trapezoidal structure unlike prior art, but middle wide, narrow stereochemical structure up and down, like this, even mask skew when making n trap or p trap and the n trap and the p trap that cause are asymmetric on the sti structure both sides, because the existence of the wide part in centre of sti structure can not cause the active area in p trap and the n trap to be communicated with yet, and perhaps can not cause the active area in n trap and the p trap to be communicated with.The upper area of sti structure is made and has been guaranteed that the sti structure of made is in Semiconductor substrate, be not higher than Semiconductor substrate, therefore, method provided by the invention and sti structure guaranteed in the situation that when follow-up making n trap or p trap the mask skew isolate active area in p trap and the n trap fully, perhaps isolate the active area in n trap and the p trap fully.
Description of drawings
Fig. 1 is prior art is made sti structure in Semiconductor substrate method flow diagram;
Fig. 2 a～Fig. 2 d is prior art is made sti structure in Semiconductor substrate process cross-sectional view;
Fig. 3 is prior art is made two traps in Semiconductor substrate cross-sectional view;
The sti structure of the made that causes owing to mask skew that Fig. 4 provides for prior art can't be isolated the generalized section of the active area in p trap and the n trap fully;
Fig. 5 is the method flow diagram of making sti structure in Semiconductor substrate provided by the invention;
Fig. 6 a～Fig. 6 j is process generalized section of making sti structure in Semiconductor substrate provided by the invention;
Even the mask skew was also so that sti structure is isolated the generalized section of the active area in p trap and the n trap fully when Fig. 7 was the two trap of making of the present invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The sti structure of prior art made can't be isolated the active area in p trap and the n trap fully, the reason of perhaps isolating the active area in n trap and the p trap fully is: mask skew when making n trap or p trap and cause the p trap on sti structure both sides and n trap asymmetric, finally cause the active area in p trap and the n trap to be communicated with, or cause the active area in n trap and the p trap to be communicated with.In order to overcome this problem, even just must be so that mask skew when making n trap or p trap, sti structure still can be isolated the active area in p trap and the n trap fully, perhaps isolates the active area in n trap and the p trap fully.
Therefore, the shallow groove isolation structure of made of the present invention, and be an etching unlike prior art, filling and polishing form, but passed through secondarily etched, secondary filling and second polishing form, formed sti structure and be rectangular structure or inverted trapezoidal structure unlike prior art, but middle wide, narrow stereochemical structure up and down, like this, even mask skew when making n trap or p trap and the n trap and the p trap that cause are asymmetric on the sti structure both sides, because the existence of the wide part in centre of sti structure can not cause the active area in p trap and the n trap to be communicated with yet, and perhaps can not cause the active area in n trap and the p trap to be communicated with.The sti structure that the upper area making of sti structure has guaranteed made is not higher than Semiconductor substrate in Semiconductor substrate,
Fig. 5 is the method flow diagram of making sti structure in Semiconductor substrate provided by the invention, and in conjunction with the process generalized section of making sti structure in Semiconductor substrate provided by the invention shown in Fig. 6 a～Fig. 6 j, the present invention is described in detail:
Step 501, provide Semiconductor substrate 11, Semiconductor substrate 11 is carried out oxidation, form the first oxide layer 12, at formed the first oxide layer 12 surface depositions the first silicon nitride layer 13, shown in Fig. 6 a;
In this step, the deposition of the first silicon nitride layer 13 adopts the LPCVD mode to carry out, and the first silicon nitride layer 13 that deposits is on the one hand in the hard mask protection Semiconductor substrate of follow-up conduct, on the other hand in follow-up polishing process as etching stop layer;
Step 502, employing photoetching and etching technics be etching the first silicon nitride layer 13 and the first oxide layer 12 successively, shown in Fig. 6 b;
In this step, described photoetching process is: after the first silicon nitride layer 13 applies photoresist layer, adopt width greater than sti structure lower zone graph exposure and the photoresist layer that develops, form width greater than the pattern of sti structure lower zone pattern at photoresist layer, then take photoresist layer with this pattern as mask, the first silicon nitride layer 13 and the first oxide layer 12 are carried out dry method ion etching, in the first silicon nitride layer 13 and the first oxide layer 12, form width greater than the groove of sti structure lower zone;
In this step, width is not less than the thickness of subsequent deposition the second oxide layer 51 greater than amount;
Step 503, behind Semiconductor substrate 11 surface depositions the second silicon oxide layer 51, take the first silicon nitride layer 13 as etching stop layer, carry out dry etching after, obtain the structure shown in Fig. 6 c;
Dry etching is adopted in step 504, continuation, forms grooves 52 in Semiconductor substrate 11, shown in Fig. 6 d;
Step 505, in groove 52, fill silica after, take the first silicon nitride layer 13 as stop-layer, polish, form T-shaped isolation structure 53 in Semiconductor substrate 11, shown in Fig. 6 e;
In this step, chemical-mechanical planarization (CMP) method is adopted in polishing;
In this step, " 1 " in the illustrated T-shaped isolation structure 53 is inverted trapezoidal structure;
Step 506, wet-cleaned are fallen the first silicon nitride layer 13 and the first oxide layer 12, shown in Fig. 6 f;
Step 507, carry out the epitaxial growth of Semiconductor substrate 11, obtain epitaxial loayer 54; Shown in Fig. 6 g;
Step 508, at Semiconductor substrate 11 deposition the second oxide layer 55 and the second nitration cases 56 that have epitaxial loayer 54, shown in Fig. 6 h;
Step 509, behind the second silicon nitride layer 56 deposition the 3rd silicon oxide layer 57, be polished to the second silicon nitride layer 55, form the upper area of sti structure, shown in Fig. 6 i;
In this step, the CMP mode is adopted in polishing;
Step 510, removal the second nitration case 52 and the second oxide layer 53 have formed sti structure 58, shown in Fig. 6 j.
The present invention also provides a kind of shallow groove isolation structure, shown in Fig. 6 j, comprising: have between the n trap in Semiconductor substrate and the p trap: T-shaped structural region and upper area structure, wherein,
T-shaped structural region is positioned at upper area structure below, is made of silica, and the upper area structure consists of by three layers, and three layers is that bottom oxide layer, silicon nitride layer and top layer silicon oxide layer consist of, and width is less than " one " part width of T-shaped structural region.
In this sti structure, described T-shaped structural region " 1 " be inverted trapezoidal structure partly.
After Semiconductor substrate forms sti structure of the present invention, form respectively n trap and p trap on the both sides of sti structure, forming process is: the sti structure right half part on Semiconductor substrate 11 surfaces adopts photoetching process to make n trap mask layer, this mask layer can be photoresist layer, then with this n trap mask layer for blocking, carry out the n trap and inject, behind the formation n trap, remove n trap mask layer; Similarly, adopt photoetching process to make p trap mask layer in the sti structure left-half on Semiconductor substrate 11 surfaces, then with this p trap mask layer for blocking, carry out the p trap and inject, form the p trap after, removal p trap mask layer.
The follow-up mode of Implantation that adopts in p trap and n trap again is manufactured with respectively the source region.
Even the mask skew was also so that sti structure is isolated the generalized section of the active area in p trap and the n trap fully when Fig. 7 was the two trap of making of the present invention, as shown in the figure, because mask skew, the n trap of made will be far longer than the p trap on Semiconductor substrate 11, so that the n trap on sti structure both sides and p trap are asymmetric, follow-up when being manufactured with the source region respectively in n trap and p trap, the active area in n trap and the p trap still can be by the zone line isolation of sti structure.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.

Claims (8)

1. the manufacture method of a shallow-trench isolation, the method comprises:
Semiconductor substrate is provided, on Semiconductor substrate, forms successively the first oxide layer and the first silicon nitride layer;
Adopt photoetching and etching technics successively etching the first silicon nitride layer and the first oxide layer, form the first groove;
Deposit the second silicon oxide layer, take the first silicon nitride layer as etching stop layer, behind the dry etching, form the second groove in Semiconductor substrate;
Continue to adopt dry etching, between the n of Semiconductor substrate trap and p trap, form with the second groove with the 3rd wide groove;
In the 3rd groove, fill silica, form T-shaped isolation structure in Semiconductor substrate;
Wet-cleaned is carried out the epitaxial growth of Semiconductor substrate after falling the first silicon nitride layer and the first oxide layer, obtains epitaxial loayer;
After the Semiconductor substrate with epitaxial loayer deposits the second oxide layer and the second nitration case, behind the second silicon nitride layer deposition the 3rd silicon oxide layer, be polished to the second silicon nitride layer, form the upper area of sti structure;
Remove the second nitration case and the second oxide layer, formed sti structure.
2. the method for claim 1 is characterized in that, adopt photoetching and etching technics successively the process of etching the first silicon nitride layer and the first oxide layer be:
After the first silicon nitride layer applies photoresist layer, adopt width greater than pattern exposure and the photoresist layer that develops of " 1 " the partial width pattern in the T-shaped isolation structure, form width greater than the pattern of " 1 " the partial width pattern in the T-shaped isolation structure at photoresist layer, then take photoresist layer with this pattern as mask, to the first silicon nitride layer and the first oxide layer dry method ion etching, in the first silicon nitride layer and the first oxide layer, form width greater than first groove of " 1 " the partial width pattern in the T-shaped isolation structure.
3. method as claimed in claim 2 is characterized in that, described width is not less than the thickness of subsequent deposition the second oxide layer greater than amount.
4. the method for claim 1 is characterized in that, the described chemical-mechanical planarization CMP method of using that is finished to.
5. the method for claim 1 is characterized in that, " 1 " part in the described T-shaped isolation structure is inverted trapezoidal structure.
6. such as the described method of claim 1～5 any one, it is characterized in that, the method also comprises:
On the both sides of described sti structure, make respectively n trap and p trap;
In n trap and p trap, be manufactured with respectively the source region.
7. shallow groove isolation structure comprises: have between the n trap in Semiconductor substrate and the p trap: T-shaped structural region and upper area structure, wherein,
T-shaped structural region is positioned at upper area structure below, is made of silica, and the upper area structure consists of by three layers, and three layers is that bottom oxide layer, silicon nitride layer and top layer silicon oxide layer consist of, and width is less than " one " part width of T-shaped structural region.
8. structure as claimed in claim 7 is characterized in that, described T-shaped structural region " 1 " be inverted trapezoidal structure partly.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116978788A (en) * 2023-09-25 2023-10-31 粤芯半导体技术股份有限公司 LDMOS device with multi-layer field plate structure and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347439A (en) * 1994-08-31 2003-12-05 Toshiba Corp Semiconductor memory
US20100230778A1 (en) * 2009-03-16 2010-09-16 Shen-De Wang Method of fabricating a flash memory and an isolating structure applied to a flash memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347439A (en) * 1994-08-31 2003-12-05 Toshiba Corp Semiconductor memory
US20100230778A1 (en) * 2009-03-16 2010-09-16 Shen-De Wang Method of fabricating a flash memory and an isolating structure applied to a flash memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116978788A (en) * 2023-09-25 2023-10-31 粤芯半导体技术股份有限公司 LDMOS device with multi-layer field plate structure and preparation method thereof

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